JPS60246095A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the action margin to the noises generated at a power supply line by connecting in series FETs which are controlled by the power supply voltage and the earth potential and feeding back the noises produced with the power supply voltage and the earth potential respectively. CONSTITUTION:The P and W type FETQ2 and Q3 forming an NOR gate of an address buffer ADB are controlled by an address Ai. The P type FETQ5 and Q6 which are always kept on are connected in series between the FTEQ2 and Q3 and the power supply voltage VCC and the earth potential respectively. The FETQ5 and Q6 are controlled by the VCC and the earth potential respectively, and the noises produced with the VCC and the earth potential are fed back. An NOR gate is inactive when those noises are produced. Thus no malfunction is produced to the noises. As a result, the action margin is improved to the noises of a semiconductor IC of an address buffer circuit, etc.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device, such as an internally synchronous RAM that detects changes in address signals and forms timing signals necessary for the operation of internal circuits. (
It relates to techniques that are effective for use in random access memory (random access memory).

[Background technology]

Prior to the present invention, the inventors of the present application devised a pseudo-static RAM that detects changes in address signals and forms various timing signals necessary for the operation of internal circuits. That is, a dynamic memory cell is used, which is composed of a capacitor that stores information in the form of charge, and an address selection MO3FET, and its peripheral circuit is composed of an 0MO3 (complementary MOS) static type circuit, and the address signal is By detecting changes and obtaining necessary timing signals, it can be treated externally in the same way as a static RAM.

In this case, the inventor's research has revealed that the following problem occurs. That is, when a data output buffer that drives a data bus or the like operates, relatively large noise is generated on the power supply line. For example, when the data output buffer forms a low-level output signal in a state where a high level is accumulated in the stray capacitance of the data bus, etc., a relatively large discharge current flows through the circuit's ground potential line. The potential will rise. As a result, the logic threshold voltage of the CMOS inverter circuit constituting the address buffer becomes substantially high, and a high level address signal is erroneously determined to be low level. As a result, the internal address signal passed through the address buffer changes, and the timing generation circuit responds to this change. As a result, for example, before rewriting information that is about to be destroyed by reading, the word line is switched and a selection operation according to the above address signal is started. An object of the present invention is to provide a semiconductor integrated circuit device that improves the operating margin against noise.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, input M receives a signal supplied from an external terminal.
MOSFETs that are constantly turned on in response to the power supply voltage and/or the ground potential of the circuit are provided in series with the OS FET to feed back noise generated in the power supply voltage or the ground potential of the circuit.

〔Example〕

FIG. 1 shows a block diagram of one embodiment of the invention.

In the same figure, each circuit block surrounded by a dotted line is made of ISH such as single crystal silicon, V cc , V
ss is its external terminal, and power is supplied to the terminals Vcc and Vss from an appropriate external power supply device (not shown).

The circuit symbol M-ARY is a memory array, which includes a storage capacitor and an address selection MOS F.
Known 1MO3 type memory cells made up of ET are arranged in a matrix.

In this embodiment, although not particularly limited, the memory cells are a pair of complementary data cells arranged in parallel! J! D.

2 whose input/output nodes are connected to either one of D
Arranged in an intersection manner.

The circuit symbol PCI indicates a complementary data line precharge circuit, which is composed of a MOSFET that receives a precharge pulse φpcr, shorts the complementary data line D, and precharges it to Vcc/2. .

What is indicated by the circuit symbol SA is a sense amplifier, in which a pair of power switches MO3FET each consisting of a P-channel MO3FET and an N-channel MO3FET are connected to the power supply voltage Vcc and the circuit ground potential Vss, although this is not particularly limited. 0MO3 provided (complementary MO3)
It is composed of a launch circuit, and its pair of input/output nodes are coupled to the complementary data line D. The timing pulse φpa shown as a representative is for controlling the -E power switch MO3FET. Note that the above power switch MOSFET is an N-channel MOSFET.
Since it is composed of a FET and a P-channel MO5FET, a complementary timing pulse consisting of a non-inverted timing pulse φpa and an inverted timing pulse φpa (not shown) is used as the timing pulse φpa.

The pair of power switch MO3FETs are turned off immediately before precharging. As a result, the complementary data lines D maintain the Vcc and Vss levels in a floating state.

The precharging operation of the memory array of this embodiment is not particularly limited, but is performed by simply shorting a pair of complementary data lines (the same applies to a common complementary data line to be described later) to bring the level to an intermediate level of approximately Vcc/2. It is. As a result, the amount of level change is smaller than that of a charge amplifier from O volts to Vcc level, and the precharge M
The gate voltage of the OS FET is set to the normal logic level (Vc
Even with the use of c), since it can be turned on in a sufficiently non-saturated state, the precharge operation can be performed at high speed and with low power consumption. As mentioned above, since the precharge level is set to an intermediate level of approximately Vcc/2, even when reading the memory cell, the gate voltage (
normal logic level (Vcc) as word line selection voltage)
Since the capacitor can be turned on in a sufficiently unsaturated state even when using the capacitor, it is possible to read out the entire charge of the information storage capacitor without using a bootstrap voltage. In addition, the read reference voltage can be set by using the precharge level of the data line on which no memory cell is selected.
A dummy cell that forms a read reference voltage becomes unnecessary.

Denoted by circuit symbol C-5W is a column switch that couples a selected complementary data line to a common complementary data line in accordance with a column selection signal.

The circuit symbol R-ADB is a row address buffer which receives external address signals from external terminals AO-88 and outputs internal complementary address signals aO-a13 .
Process and form aQ to a8.

In the following description and drawings, a pair of internal complementary address signals, for example aO, aO, will be referred to as an internal complementary address signal aO.
I will express it as Therefore, the internal complementary address signals aO to a13. aQ-aQ represents internal complementary address signals 10 to 8.

The circuit symbol C-ADB is a column address buffer, which receives external address signals from external terminals A9 to A14 and outputs internal complementary address signals a9 to a1.
4. Form a9 to a14. In addition, in accordance with the way of representing the internal complementary address signals described above, in the drawings and the following description, the internal complementary address signals a9 to a14, 39 to a
14 is represented as an internal complementary address signal 19-14.

The circuit symbol R-DCR is rowat j/
It receives an internal complementary address signal aO"- and 8 via a multiplexer MPX, which will be described later, and
A word line selection signal for ARY is formed. This word line selection signal is transmitted to the M-A RY in synchronization with the word line selection timing pulse.

The circuit symbol C-DCR is a column address decoder, which receives internal complementary address signals from main 9 to 114.
In response to this, an M-ARY data line selection signal is formed.

This data line selection signal is transmitted to the column switch CSW in synchronization with the data line selection timing signal φy.

What is indicated by the circuit symbol PC2 is a precharge circuit for the common complementary data line, which may include, but is not particularly limited to, a MOSFET similar to the above-mentioned bridge circuit PCI that short-circuits the common complementary data line in response to the precharge pulse φpcd.
It is made up of.

The circuit symbol MA indicates a main amplifier, which has the same circuit configuration as the sense amplifier SA described above. The timing pulse φma shown as a representative is for controlling the N-channel M, 03FET of the pair of power switches MO3FET. In addition, like the sense amplifier SA mentioned above, P channel MOS F
The inverted timing pulse φma is omitted to control ET.

The circuit symbol DOB is a data output cover sofa, which transfers the readout from the main amplifier MA to the external terminal Do- by the readout timing pulse φrw.
Each is sent to D7. In addition, during writing, this DOB is made inactive (output high impedance) by the readout disabling pulse φrll.

A data input buffer is indicated by the circuit symbol DIR, and transmits write data from external terminals DO to D7 to a common complementary data line in response to a write timing pulse φrtn. Note that during reading, this DIB is made inactive by the write timing pulse φrw.

The various timing signals described above are formed by the following circuit blocks.

Although not particularly limited, what is indicated by the circuit symbol RATD is an address signal change detection circuit that receives address signals aO to a8 (or 10 to a8) and detects a change in the rise or fall of the address signals. Circuit symbol CA T”
Although not particularly limited, D is an address signal change detection circuit that receives address signals a9 to a14 (or 19 to 114) and detects changes in their rising or falling edges.

The address signal change detection circuit RATD includes, but is not particularly limited to, an exclusive OR circuit that receives each of the address signals aO to a8 and their delayed signals, and an OR circuit that receives the output signals of these exclusive OR circuits. It is composed of That is, an exclusive circuit for receiving an address signal and a delayed signal of that address signal is provided for each address signal. In this case, nine exclusive OR circuits are provided, and the output signals of the 9 IVA exclusive OR circuits are input to the OR circuit. This address signal change detection circuit RATD detects the address signals aO to a8.
When any one of them changes, an address signal change detection pulse φr synchronized with the change timing is generated.

The address signal change detection circuit CATD has the same configuration as the address signal change detection circuit REG.

That is, it is comprised of exclusive OR circuits that receive address signals a9 to a14 and their delayed signals, respectively, and an OR circuit that receives output signals from these exclusive OR circuits. This address signal change detection circuit CAT
Similarly to the address signal change detection circuit RATD, when any of the address signals a9 to a14 changes, D forms an address signal change detection pulse φC synchronized with the change timing.

The circuit symbol TG is a timing generation circuit, which forms the main timing signals etc. shown as the representative above. In other words, this timing generation circuit'l
'G, address signal change detection pulses φr, φC, etc.
The series of timing pulses described above is formed by receiving the write enable signal WE and chip selection signal C3 supplied from an external terminal.

A multiplexer is indicated by the circuit symbol MPX, and the above-mentioned address buffer R-AD is
The internal complementary address signal aO-a8 formed by B and the internal complementary address signal 10 to Saturday and Sunday formed by the automatic reflex/nosh circuit REF are selectively input to the decoder R-.
Tell DCH.

The circuit symbol Vbb-G indicates a substrate bias voltage generation circuit.

The circuit symbol REF is an automatic refresh circuit, which includes a fresh address counter, a timer, etc., and receives a refresh signal RE from an external terminal.
It is activated by setting S H to low level. That is, when the refresh signal qizEsH is set to a low level while the chip selection signal C8 is at a high level, the automatic refresh circuit REF switches the multiplexer MPX using the control signal φrcJ, and transfers the internal address signal from the built-in refresh address counter to the row decoder R.
-DCH to perform a refresh operation (auto refresh) by selecting one word line.

Further, when the refresh signal RESH is kept at a low level, a timer is activated, and the refresh address counter is incremented at regular intervals, and a continuous refresh operation (self-refresh) is performed during this period.

FIG. 2 shows the address buffer R-ADB.

A circuit diagram of a specific embodiment of C-ADB is shown.

In this embodiment, address buffers R-A are
In order to prevent the DB and C-ADB from malfunctioning, the following feed hack MOS FET is provided.

That is, the signal from the external address signal terminal At is sent to the P channel MO3 which constitutes a NOR gate circuit.
FETQ2 and N-channel MO3Fl: Commonly supplied to the gate of TQ3. In addition, the chip selection signal C8
The timing pulse φ formed by the above is commonly supplied to the gates of the P-channel MO3FETQI and the N-channel MO3FETQ4 that constitute the NOR gate circuit. As a result, the address signal is taken in from the external terminal Ai only when the timing pulse φ is at a low level in the chip selection state.

Then, as mentioned above, the power line noise is transferred to the input circuit (
Although not particularly limited, a P-channel MO3FETQ5 whose gate is constantly supplied with the ground potential of the circuit is provided between the P-channel MO5FETQI and the power supply voltage Vcc in order to provide feedback to the NOR gate circuit. Furthermore, an N-channel MO3FET Q6 whose gate is constantly supplied with the power supply voltage Vcc is provided between the N-channel MO3FET Q3 which receives the address signal supplied from the external terminal At and the ground potential point of the circuit.

Note that the output signal of the NOR gate circuit is supplied to a CMOS inverter circuit IVI, and a non-inverted address signal ai is sent from its output. Further, the output signal of this inverter circuit IVI is supplied to a CMOS inverter circuit IV2, where an inverted address signal ai is formed.

Next, the operation of this embodiment circuit will be explained according to the timing diagram of FIG.

Any address signal A supplied from an external terminal in a chip selection state where the chip selection signal C3 is at a low level.
When i changes, the address signal change detection circuit RATD
(CATD) causes address signal change detection detection pulse φ
r(φC) is formed.

The timing generation circuit TO synchronizes with the address signal change detection pulses φr and φC to generate the memory array M-ARY.
Temporarily reset the selection circuit.

That is, the timing pulse φρa puts the sense amplifier SA into a non-operating state, and the complementary data line is connected.

5 in a floating state. Further, the word line selection timing signal φX and the data line selection signal φy are set to low level to put them in a non-selected state.

Then, the precharge pulse φpcr is once set to high level, and the half precharge operation as described above is performed.

After this precharge operation is completed, the word line selection timing signal φX is set to high level, and the word line is selected in accordance with the fetched address signal.

Next, the timing pulse φp-a causes the sense amplifier S
A is put into operation and a complementary data line is provided, the stored information of the memory cell read to D is amplified and the complementary data line is provided,
Tell D. The charge as stored information in the memory cell, which is once destroyed by the word line selection operation, is recovered by receiving the level of the amplified complementary data line D as it is.

Next, a selection operation of the column switch circuit C-CW is performed in synchronization with the rise of the data line selection timing signal φy, and the read signal read out to the common complementary data line is amplified by the main amplifier MA. Then, the data output buffer DOB is activated by the low level of the timing pulse φr-, and outputs the read output pout from the external terminal. At this time, for example, when the data output buffer DOB forms a low level output signal with a high level accumulated in the stray capacitance of the data bus, etc., a relatively large discharge current flows to the ground potential Vss of the circuit. The ground potential Vss of will rise. In addition,
Although not shown, when a data bus or the like sends out a low-level output signal and a high-level output signal, the power supply voltage Vcc decreases. Even if there is noise in the power supply line, the feedback MOS in the embodiment circuit shown in FIG.
FETQ5. Since Q6 is provided, the operating margin can be expanded. That is, as shown in the figure, when noise occurs in the ground potential Vss of the circuit, the ground potential of the circuit rises, and the logic threshold voltage of the input circuit becomes substantially higher, so that the high level side of the input signal At This reduces the noise margin of However, at this time, the circuit ground potential Vs
P channel MO3F which is in the on state after receiving s
The conductance characteristics of ETQ5 become small, making it difficult for current to flow. This can prevent a malfunction in which the input circuit erroneously outputs a low level supplied from the external terminal Ai as a high level. In other words, as shown in the figure, it is possible to prevent a malfunction equivalent to when the address signal At changes due to the noise. Furthermore, although not shown, if noise occurs in the power supply voltage Vcc, it will conversely reduce the noise margin on the low level side of the input signal At. However, at this time, the conductance characteristic of the N-channel MO3FET Q6, which is turned on in response to the power supply voltage Vcc, becomes small, making it difficult for current to flow.

This can prevent a malfunction in which the input circuit erroneously outputs a high level supplied from the external terminal A+ as a low level. In other words, as shown in the figure, the noise causes the address signal /M
This makes it possible to prevent malfunctions equivalent to those caused by a change in the value.

〔effect〕

(1) Deterioration of level margin due to noise can be avoided by providing a MOSFET that is constantly turned on in response to the power supply voltage Vcc and the ground potential of the 7 circuits in series with an input MOSFET that receives a signal from an external terminal. It acts to suppress the generation of inverted output caused by As a result, it is possible to substantially prevent deterioration of the input level margin due to noise, resulting in the effect that the operating margin can be improved.

(2) By providing a feedback MOSFET in the input circuit to the address buffer of an internally synchronous semiconductor memory device, the address signal change detection circuit will respond to noise generated during the operation cycle. Since such changes in the address signal do not occur, it is possible to achieve the effect that a stable read operation can be performed.

(3) Since the feedback MOSFET operates by constantly receiving the voltage from the power supply line, it has the advantage of being able to immediately respond to randomly generated noise.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. do not have. For example, the feed bank MOSFET may include only one MOSFET that receives the circuit ground potential V53 or the power supply voltage Vcc. Further, the input circuit is not limited to the 0M03 circuit, and may be configured only with an N-channel MOS FET or a P-channel MO3FET.

Further, the specific circuit configuration of the peripheral circuits constituting the pseudo-static RAM can take various embodiments. Note that an automatic refresh circuit is not particularly required. Furthermore, even in internally synchronous static RAM, if a malfunction equivalent to a change in the address signal due to noise occurs, the address will be switched during operation, resulting in double selection of memory cells. This causes problems such as destruction of stored information. Therefore, by providing the aforementioned slow feed bank MO3FET in the address buffer, the above-mentioned malfunction can be prevented.

[Application field]

In the above explanation, the invention made by the present inventor was mainly explained with respect to an internally synchronous dynamic type RAM, which is the field of application behind the invention, but it is not limited to this, and the invention is not limited to this. It can be widely used in various semiconductor integrated circuit devices that operate in various ways.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing one embodiment of the address buffer, and FIG. 3 shows the operation of the RAM shown in FIG. 1. FIG. 3 is a timing chart showing an example. M-ARY...Memory array, PCI...Precharge circuit, SA...Sense amplifier, R-ADB...Row address buffer, C-5W...Column switch, C-AD
B: Column address buffer, R-DCR: Row address decoder, C-DCR: Column address decoder, PO2: Precharge circuit, MA: Main amplifier, RATD, CATD: Address signal change detection circuit. TG: Timing generation circuit, REF: Automatic refresh circuit, DOB: Data output cover, 7 fur.

Claims (1)

[Claims] 1. MOSFET that receives a signal supplied from an external terminal
and a MOSFET which is provided in series with the MOSFET and is constantly turned on in response to a power supply voltage and/or a ground potential of the circuit. 2. The input MO3FET is a CMO3 circuit consisting of an N-channel MO3FET and a P-channel MO3FET connected in series, and is a MOSFET that is constantly turned on by receiving the power supply voltage and/or the ground potential of the circuit.
is an N-channel MO3FET and/or a P-channel M
The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is an OS FET. 3. The semiconductor integrated circuit device constitutes an internally synchronous semiconductor memory device that detects changes in address signals and forms a series of timing signals for the operation of internal circuits, and the input circuit is connected to its address buffer. A semiconductor integrated circuit device according to claim 1 or 2, characterized in that it constitutes a semiconductor integrated circuit device.