JPS60136089A - Mos memory - Google Patents

Abstract

PURPOSE:To obtain an MOS memory which compensates an assured information storage action by providing both gate and latch functions to an address buffer circuit. CONSTITUTION:The output signal of a delay circuit DL is set at a high level after a rewriting action is over. This rewriting is carried out by receiving the amplification signal of a sense amplifier SA as it is by a memory cell. An input circuit which accepts an address signal Ai is activated. While a feedback circuit of a latch circuit is inactivated. Therefore the noise N if produced to the signal Ai supplied from outside during the above-mentioned series of actions is prevented by said input circuit. At the same time, an address signal ai fetched previously is held.

Description

[Detailed Description of the Invention] (Technical Field) The present invention relates to a memory device composed of MOSFETs (insulated gate field effect transistors). Dynamic RAM that forms timing signals
(Random Access Memory).

[Background technology]

Prior to the present invention, the inventors of the present application developed a pseudo-static RAM that detects changes in address signals and forms various timing signals necessary for the operation of internal circuits. That is, a dynamic type memory cell is used, which is composed of a capacitor that stores information in the form of charge, and an address selection MOSFET, and its peripheral circuit is configured with a 0MO3 (complementary MO3) static type circuit, and the address selection is By detecting signal changes and obtaining necessary timing signals, it can be treated externally in the same way as a static RAM.

In this case, the inventor's research has revealed that the following problem occurs. That is, by detecting changes in the address signal and generating a series of timing signals,
If noise or the like is added to the external address signal while a series of operations such as writing or reading are being performed, the timing generation circuit will respond to this and the selected memory cell will be abandoned. In other words, when the charge accumulated in the memory cell is about to be lost due to the word line selection operation and the sense amplifier amplification operation, in other words, the level of the read information is amplified and rewritten (active restore operation). Before the word line switching is performed. As a result, rewriting is not performed, which may cause a serious problem of information being destroyed.

[Purpose of the invention]

The purpose of this invention is to provide an MO system that guarantees reliable information storage operation.
3 to provide a storage device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

Representative inventions II among the inventions disclosed in this application
l! ! ! ! A brief explanation is as follows.

That is, by providing the address buffer circuit with a gate function and a latch mtm, it is possible to prohibit the capture of address signals from external terminals and to hold the captured address signals from the timing when the operation starts to the end of the cycle. It is something that makes you

(Embodiment) FIG. 1 shows a block diagram of an embodiment of the present invention.

In the figure, each circuit block surrounded by a dotted line is formed on a single semiconductor substrate such as silicon by a known semiconductor integrated circuit manufacturing technique. AO~A14゜WE, C8, RESH and Vcc, Vas are the external terminals, and the terminal Vc
Power is supplied to c and Vss from an appropriate external power supply device (not shown).

The circuit symbol M-ARY is a memory array, which includes a storage capacitor and an address selection MOS F.
Known 1MO5 type memory cells composed of ET are arranged in a matrix.

In this embodiment, although not particularly limited, the memory cells include a pair of complementary data lines arranged in parallel.

2 whose input/output nodes are connected to either one of D
Arranged in an intersection manner.

A data line precharge circuit designated by the circuit symbol PCI is constituted by a MOSFET that receives a precharge pulse φpcr, shorts the complementary data line D, and precharges the circuit to Vcc/2.

The circuit symbol SA indicates a sense amplifier, which is composed of an 0MO3 (complementary MO3) latch circuit in which a power switch MO3FET is provided for the power supply voltage Vcc and the circuit ground potential Vss, although this is not particularly limited. , the pair of input/output nodes are connected to the complementary data line,
It is connected to D.

Timing pulse φpaLφpal and φpa2+φρ
a2 is for controlling the power switch MO8FET. The power switch MO5FET is turned off immediately before precharging. As a result, the complementary data line D maintains the Vcc and Vss levels in a floating state. And the above precharge MO3FET
By turning on, the complementary data line D is short-circuited, and Vc
Precharged to c/2.

The precharging operation of the memory array in this embodiment is to simply short-circuit a pair of complementary data lines (the same applies to a common complementary data line to be described later) to bring the voltage to an intermediate level of about Vcc/2. , the amount of level change is small compared to conventional dynamic RAM, which charges up from 0 volts to the Vcc level.
Even if the gate voltage of the precharge MO3FET is set to a normal logic level (Vcc), it can be turned on in a sufficiently non-saturated state, so the precharge operation can be performed at high speed and with low power consumption.

Then, as mentioned above, set the precharge level to approximately Vcc.
/2, so even when reading the memory cell, the memory cell switch MO3F
Even if a normal logic level (Vcc) is used as the ET gate voltage (word line selection voltage), it can be turned on in a sufficiently unsaturated state, so conventional dynamic RAM
It becomes possible to read out the entire charge of the information storage capacitor without using a bootstrap voltage as in the case of FIG.

Further, since the read reference voltage uses the precharge level of one data line on which no memory cell is selected, there is no need for a dummy cell that forms the read reference voltage as in the conventional dynamic RAM.

Note that the timing signals φpal and φpal are mutually complementary signals, and the timing signals φpa2° and φpal are mutually complementary signals.
pa2 are also mutually complementary signals. FI! In order to simplify the J plane, the timing signal φpa is
Lφpal is collectively expressed as lxl, and the timing signal φ
The combination of pa2+dpa2 is expressed as fho2.

Denoted by circuit symbol C-5W is a column switch that couples a selected complementary data line to a common complementary data line in accordance with a column selection signal.

The circuit symbol R-ADB is a row address buffer which receives external address signals from external terminals A0-88 and outputs internal complementary address signals a0-a8 . a
0 to a8 are formed. In addition, in the following explanation and drawings,
A pair of internal complementary address signals, for example ao and ao, will be expressed as internal complementary address signal aO. therefore,
The internal complementary address signal ao'-a8. a0 to a8 are represented as internal complementary address signals a0 to a8.

The circuit symbol C-ADB is a column address buffer, which receives external address signals from external terminals A9 to A14 and outputs internal complementary address signals a9 to a1.
4. Form a9 to a14. In addition, in accordance with the way of representing the internal complementary address signals described above, in the drawings and the following description, the internal complementary address signals a9 to a14 . a9～a
14 is represented by internal complementary address signals 9 to a14.

The circuit symbol R-DCR is a row address decoder, which receives an internal complementary address signal aQ=a8 via a multiplexer MPX, which will be described later, and outputs M-AR.
A Y word line selection signal is formed. This word line selection signal is synchronized with the word line selection timing signal φX.
-To be communicated to ARY.

The circuit symbol C-DCR is a column address decoder, which receives internal complementary address signals 19 to 14.
In response to this, an M-ARY data line selection signal is formed.

This data line selection signal is transmitted to column switch C-5W in synchronization with data line selection timing signal φy.

The circuit symbol PC2 indicates a precharge circuit for the common complementary data line, and is a MOSFET similar to the above precharge circuit PCI that short-circuits the common complementary data line in response to the precharge pulse φpad, although it is not particularly limited.
It is made up of.

The circuit symbol MA indicates a main amplifier, which has the same circuit configuration as the sense amplifier SA described above. Timing pulses φmal, φ+mjl and φma2+φ
+sa2 is for controlling the power switch MO3FET. Note that this timing signal φma
l and φmal are mutually complementary signals, and timing signals φma2 and (71sa2 are also mutually complementary signals. In the figure, the timing signals φma'Lφ
11a1 is collectively expressed as L salmon 1, and the timing signal φm
a2. LL with 'jma2! It is expressed as L2.

What is indicated by the circuit symbol DOB is a data output cover sofa, which outputs the read data from the main amplifier MA to external terminals D0 to D0 by the read timing pulse φrw.
Each is sent to D7. Note that during writing, this DOB is made inactive (output high impedance) by the read timing pulse φrw.

The circuit symbol DIB is a data input buffer, which transmits write data from external terminals D0 to D7 to a common complementary data line in response to a write timing pulse φr11. Note that during reading, this DIB is made inactive by the write timing pulse φrH.

The various timing signals described above are formed by the following circuit blocks.

Although not particularly limited, the circuit symbol REG is an edge trigger circuit that receives the address signal ao''a8 (or a0 to a8) and detects its rising or falling edge.

Although not particularly limited, the circuit symbol CEG is an edge trigger circuit that receives address signals a9 to a14 (or a9 to 114) and detects their rising or falling edges.

Although the edge trigger circuit REG is not particularly limited,
It is constituted by exclusive OR circuits that receive address signals a0 to a8 and their delayed signals, respectively, and an OR circuit that receives output signals from these exclusive OR circuits.

That is, an exclusive circuit for receiving an address signal and a delayed signal of that address signal is provided for each address signal. In this case, nine exclusive OR circuits are provided, and the output signals of these nine exclusive OR circuits are input to the OR circuit. This edge trigger circuit REG
When any one of the address signals a0 to a8 changes, an edge detection pulse φ synchronized with the change timing is generated.
form r.

The edge trigger circuit CEG has the same configuration as the edge trigger circuit REG. That is, it is comprised of exclusive OR circuits that receive address signals a9 to a14 and their delayed signals, respectively, and an OR circuit that receives output signals from these exclusive OR circuits. This edge trigger circuit CEG is the edge trigger circuit R mentioned above.
Similarly to EG, when any one of the address signals a9 to a14 changes, an edge detection pulse φC is generated in synchronization with the timing of the change.

The circuit symbol TG is a timing generation circuit, which forms the main timing signals etc. shown as the representative above. That is, this timing generation circuit TG
is the edge detection pulse φr.

In addition to φC, it receives a write enable signal WE and a chip selection signal CS supplied from an external terminal to form the above-mentioned series of timing pulses.

The circuit symbol MPX indicates a multiplexer, which controls the address buffer R-AD according to a control signal φref from an automatic refresher circuit REF, which will be described later.
internal complementary address signals a0-a8 formed by f3;
The internal complementary address signals aO to 8 formed by the automatic refresh circuit REF are selectively transferred to the decoder R-
Tell DCH.

The circuit symbol Vbb-G indicates a substrate bias voltage generation circuit.

The circuit symbol REF is an automatic refresh circuit, which includes a fresh address counter, a timer, etc., and receives a refresh signal RES from an external terminal.
It is activated by setting H to low level.

That is, when the refresh signal RESH is set to a low level while the chip selection signal C5 is at a high level, the automatic refresh circuit REF switches the multiplexer MPX by the control signal φref, and transfers the internal address signal from the built-in refresh address counter to the row decoder R-. This is transmitted to the DCH to perform a refresh operation (auto refresh) by selecting one word line. Further, when the refresh signal RESH is kept at a low level, a timer is activated, and the refresh address counter is incremented at regular intervals, and a continuous refresh operation (self-refresh) is performed during this period.

FIG. 2 shows a circuit diagram of a specific embodiment of the address buffer R-ADB. In this embodiment, the following gate function and launch function are added in order to prevent stored information from being destroyed by noise in the address signal supplied from an external terminal.

That is, the signal from the external address signal terminal Ai is p
Channel MO3FETQI and n-channel MO3FE
It is input to a CMOS inverter configured with TQ2. Both MO3FETQI above.

Between Q2, the power supply voltage Vcc, and the circuit ground potential point,
p-channel MO as power switch means, respectively.
A 3FETQ3 and an n-channel MO3FETQ4 are provided. The gates of these MO3FETQ3 and Q4 are
A gate function is added by applying timing signals φ and φ. This timing signal φ is formed by a NAND gate circuit G which receives the operation timing signal φpa (φpal) of the sense amplifier SA and a signal delayed by the delay circuit DL, although it is not particularly limited. Further, the inverted signal φ is formed by the inverter IV2. The delay circuit DL sets the time from the end of the operation of the sense amplifier SA until the end of rewriting (active restore).

As a result, the memory array M-ARY
For complementary data line pair D, the timing signal 7 is set to low level (circuit ground potential) from the time when precharging of D is started, and the timing signal φ is set to high level (power supply voltage V
cc) as both MO3FETQ3. Q4 is turned off to prohibit receiving the address signal At from the external terminal.

The output signal of the input circuit with the above configuration is p-channel MO3
The complementary address signal at is formed through a CMOS inverter composed of a FETQ5 and an n-channel MO3FETQ6. Further, the inverted address signal at is formed by a similar inverter IVI.

Above MO3FETQ5. The output of the inverter composed of Q6 is connected to MO3FETQ7 to QI similar to the input circuit above.
The input is fed back through a circuit made up of O. In other words, in order to hold the address signal when the input circuit is closed, MO3FETQ9 is used as a power switch means.
．． The timing signals φ and φ supplied to the gates of the QIO are used to bring the input circuit and the feedback circuit into a complementary operating state.

Next, the operation of this embodiment circuit will be explained according to the timing diagram of FIG.

When any one of the address signals A0 to An changes, a detection pulse synchronized with each edge is generated by the exclusive OR circuit or the like.

Edge detection pulse φr formed by these logical sums
(φC), the timing signal φpa (φpa
l) becomes low level, the power switch MO3FET provided in the sense amplifier SA is turned off, and the complementary data line pair D is brought into a floating state. Then, when the precharge pulse φpcr becomes high level, the MOSFET that short-circuits the complementary data line D is turned on, so that the complementary data line pair
Precharge D to Vcc/2.

At this time, the timing signal φpa of the sense amplifier SA
The low level of MO3FETQ3. of the input circuit causes the timing signal φ to go high and its inverted timing signal φ to low level. Q4 turns off and stops taking in the address signal Al. Also,
MOSFET, Q9, forming the feedback circuit of the latch circuit.
Since Ql 0 is turned on, the fetched address signal al is held.

After the precharge pulse φρCr becomes low level, the word line selection timing signal φX is generated, and the selected word line WL becomes high level. As a result, the potential of the data line changes slightly in accordance with the charge of the selected memory cell.

Then, the operation timing signal φpa of the sense amplifier SA
(φpa1) becomes high level and the sense amplifier SA
is activated and starts amplifying the minute signal read out to the complementary data line D.

At this time, the delay circuit DL causes the timing signal φ
, φ remains at the above level. Then, after a time period has elapsed when rewriting, which is performed by the memory cell receiving the amplified signal of the sense amplifier SA as it is, is completed, the output signal of the delay circuit DL becomes high level, so that the timing signal φ becomes low level. , the input circuit receiving the address signal Al becomes active, and the feedback circuit of the latch circuit is switched to the non-active state.

As a result, even if noise N occurs in the address signal At supplied from the outside during the above series of operation periods, the input circuit is prohibited from taking in this noise, and the previously taken address signal al is retained. Therefore, the edge trigger circuits REG and CEG continue the series of operations described above without responding to this.

Note that, although not particularly limited, the above-mentioned tying signal φ may be
It may be formed so that it rises in synchronization with the rise of the word line selection timing signal φX and falls in synchronization with the timing signal φX being brought to a high level due to the bootstrap effect. Setting the word line to a high level higher than the power supply voltage as described above is possible because the high level of the data line can be raised without loss of level due to the threshold voltage of the MOSFET for address selection in the memory cell.
This is for writing (full write) to the information storage capacitor (not shown). In this way, the timing signals φ and φ for operating the latch circuit while inhibiting the capture of the external address signal can also be formed using the timing signals generated by the timing generation circuit TG. .

(Effects) (1) After the edge detection pulses φr, φC, etc. are formed and a predetermined operation cycle is started, reception of external address signals is prohibited, and previously captured address signals are held. Since the edge detection circuit does not respond even if noise occurs in the external address signal during this period, it is possible to ensure that the information stored in the selected memory cell is rewritten reliably.In other words, it is possible to ensure reliable memory operation. The effect is that it can be performed.

(2) The effect of (11) above is that the operating margin can be expanded.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, the gate function provided in the address buffer may be realized by a flip-flop circuit, an ordinary logic circuit, or a transmission gate MO3FET. Further, the specific circuit configuration of the peripheral circuit constituting the Wi-like static type RAM can take various embodiments, such as one in which the complementary data line is precharged to the power supply voltage Vcc.

Note that an automatic refresh circuit is not particularly required.

[Application field]

The above explanation will mainly focus on the dynamic type RA, which is the application field that is the background of the invention made by the present inventor.
Although the explanation has been made regarding M, it is not limited to this, and similarly to the above, the operation timing of the internal circuit is formed by detecting the change timing of the address signal, and the MO3 storage device, for example, static type RAM, etc. The same can be said. In this static type RAM, there is a risk that the stored information may be destroyed due to the double selection operation of the word line, so the same effect as described above can be expected.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing one embodiment of the present invention. FIG. 2 is a circuit diagram showing one embodiment of the address buffer, and FIG. 3 is a timing diagram for explaining an example of the operation of the circuit of the embodiment. M-ARY...Memory array, PCI...Precharge circuit, SA...Sense amplifier, R-ADB...Row address buffer, C-5W...Column switch, C-AD
B...Column address buffer, R-DCR...Row address decoder, C-DCR...Column address decoder, PO2...Precharge circuit, MA...Main amplifier, REG, CEG...Edge trigger circuit, TO...Timing Generation circuit, REF... automatic refresh circuit,
DOB...Data output cover sofa, DrB...Data input cover sofa, MPX...Multiplexer, vbb-c...
Substrate bias circuit. Figure 1 Figure 2 Figure 3 bayt ZTz】Z■[ni

Claims (1)

[Claims] 1. A timing control circuit that detects a change in an address signal and forms a timing signal for the operation of an internal circuit; 1. An MO3 storage device comprising: an address buffer circuit that inhibits the capture of an address signal for word line selection and holds the captured address signal until completion of the word line selection. 2. A memory cell for storing information is composed of a capacitor for storing information and a MOSFET for selecting an address, and a peripheral circuit for writing and reading the memory cell is composed of a CMO3 circuit. The MO3 storage device according to claim 1, characterized in that: 3. The address buffer circuit includes a CMOS inverter circuit that receives an address signal supplied from an external terminal;
An input circuit consisting of a power switch MO3FET that receives a timing signal and supplies power to the CMOS inverter circuit, and a launch circuit that performs a holding operation of the address signal taken in when the power switch MOSFET is in the off state. An MO3 storage device according to claim 1 or 2, characterized in that: