JPH01213892A - Dynamic type semiconductor memory device - Google Patents

Abstract

PURPOSE:To cause a value at the time of a normal mode or at the time of a stand-by mode to be small for the output voltage of a substrate voltage generating means in operation at a self-refresh mode by executing a response to the output voltage and control signal of the substrate voltage generating means and controlling the operation of a ring oscillator circuit. CONSTITUTION:The substrate bias voltage generating circuit of a dynamic type semiconductor memory device, which generates a substrate bias voltage with low energy consumption, is constituted as follows. Namely, the substrate bias voltage generating circuit is composed of a substrate bias voltage generating part 31 to include a ring oscillator 311 and to generate the substrate bias voltage, a self-refresh control signal generating circuit 2 to be operated with responding to a condition control signal from an external part, a control part 32 to include a substrate potential detecting circuit 321 and a control circuit 322, and an additional substrate bias voltage generating part 33 to temporarily improve the output of the voltage generating part 31 when refresh is ended. Thus, the voltage of an output VBB which is generated at the time of the self- refresh mode, is controlled in a shallow range of VBBH or VBBL. Then, the energy a consuming current is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic semiconductor memory device, and particularly to a dynamic semiconductor memory device that can generate a substrate bias voltage with low power consumption.

[Background Art] In recent years, personal computers (hereinafter abbreviated as PCs) have become significantly popular. In particular, demand for portable PCs has increased recently. The storage devices used in portable PCs are
A device with low power consumption and capable of battery backup (battery retention) is required.

As such a memory device, a dynamic type semiconductor memory device or a static type semiconductor memory device is usually used. Among these, dynamic semiconductor memory devices are MO
It utilizes the principle of storing information charges in an S capacitor. However, since the accumulated charge is gradually lost due to junction leakage, etc., it is necessary to rewrite the accumulated information at regular intervals. This rewriting operation is called refresh. When a dynamic semiconductor memory device is used in a portable PC, it is necessary to refresh the memory at regular intervals even during battery backup.

On the other hand, in a dynamic semiconductor memory device, normal refresh modes such as 1 τ only refresh and CAS before H 100 refresh are controlled and executed cycle by cycle by an external clock signal. Therefore, using such a normal refresh mode during battery backup requires complicated control, which is not preferable.

Therefore, in order to solve this problem, for example, Yamada Nori rA
auto/5elf 64Kb with built-in Refresh function
It MOS Dynamic RAMJ journal of the Institute of Electronics and Communication Engineers (83/1 v.

1, J66-C, No, 1. pp, 62-69. ), a dynamic semiconductor memory device with a self-refresh mode, which incorporates an address counter and a timer and automatically continues the refresh operation, was devised and put into commercial use. ing.

This self-refresh operation is described in detail in the above-mentioned literature, but will be briefly explained below.

keeping the signal RAS, which controls the standby state and operating state of the dynamic semiconductor memory device, at a high level (standby state);
The refresh control signal REF is set to the timer set time (1
If the row address is kept at a low level for more than 6 μs (time of 6 μs or less), self-refresh mode is started, and the refresh address counter operates every time of 16 μs or less set by the built-in timer, and that row address is selected and refreshed. . As long as REF is kept low, e.g. 64, this self-refresh mode continues, and like normal refresh mode, 128 cycles of refresh are performed every 2ms or less, until all memory cells are refreshed. be done.

FIG. 15 is a circuit diagram showing a substrate bias voltage generation circuit of a dynamic semiconductor memory device having a conventional self-refresh mode.

Referring to FIG. 15, this substrate bias voltage generation circuit 4
1 is a ring oscillator 411 and a ring oscillator 41
Capacitor C for the charge pump that receives the output signal of 1
and N-channel MO3) transistors Q1 and Q2. Note that NB is an internal node, and VaB is the output of this substrate bias voltage generation circuit 41.

FIG. 16 is a waveform diagram for explaining the operation of the substrate bias voltage generation circuit shown in FIG. 15. The operation will be briefly described below with reference to FIGS. 15 and 16.

First, the output signal φ of the ring oscillator 411.

When the rising voltage signal of P is applied to the charge pump capacitor C, the potential of the node NB rises due to capacitive coupling. Then transistor Q turns on, so
The potential of node N is clamped to the threshold voltage of transistor Q. Next, when the falling voltage signal of φOP is applied, the potential of node Na decreases due to capacitive coupling, but this time transistor Q2 is turned on, so the voltage level of output vB decreases, and the voltage level of node N8 decreases. The potential is clamped to a negative potential equal to the threshold voltage of transistor Q2. As such cycles continue several times, the level of the output VB[1 gradually decreases to a predetermined negative potential.

However, in the standby state of a dynamic semiconductor memory device, the current consumption in this substrate bias voltage generation circuit accounts for most of the power consumption, so in order to reduce this, for example, W, L.

Martino et al. “An On-Ch ip B
ack-Bias Generator forM
IE titled O8Dynamic MemoryJ
EE JOURNAL (Solid-3tate
C1rcuits, vol, 5C-15, No. 5. p
p, 820-826. oct.

1980), a method of intermittent operation of a substrate bias voltage generation circuit has been devised.

FIG. 17 is a circuit diagram showing a substrate bias voltage generation circuit that can operate intermittently.

Referring to FIG. 17, compared to FIG. 15, this substrate bias voltage generation circuit further includes a substrate potential detection circuit 442.
and a control circuit 443 for controlling the ring oscillator 441 in response to the detection signal.

In operation, the substrate potential detection circuit 442 constantly monitors the substrate voltage (voltage of the output Vaa), and after this reaches a predetermined level, the control circuit 443 stops the oscillation of the ring oscillator 441, and this part This reduces power consumption. Note that if the substrate potential becomes shallower than a predetermined level for some reason, the ring oscillator 441 is configured to operate again.

[Problems to be Solved by the Invention] Since the conventional dynamic semiconductor memory device is configured as described above, the substrate bias voltage generation circuit is the same both during normal mode operation and self-refresh mode operation. Since this method consumes a large amount of electric power, there is a problem in that it causes unnecessary power consumption, for example, during battery backup.

This invention was made to solve the above-mentioned problems, and by reducing the power consumption of the substrate bias voltage generation path in the self-refresh mode compared to the normal operation mode, unnecessary power consumption can be avoided. It is an object of the present invention to obtain a dynamic semiconductor memory device with reduced .

[Means for Solving the Problems] A dynamic semiconductor memory device according to the present invention includes a substrate voltage generation means having a ring oscillator circuit means, and a control signal generation means for generating a control signal in response to an external state control signal. ring oscillator control means for controlling the ring oscillator circuit means in response to the output voltage and control signal of the substrate voltage generation means; and ring oscillator control means for controlling the ring oscillator circuit means in response to the output voltage of the substrate voltage generation means and the control signal; additional substrate voltage generating means for increasing the substrate voltage.

[Function] In the dynamic semiconductor memory device of the present invention, the ring oscillator control means controls the operation of the ring oscillator circuit means in response to the output voltage and control signal of the substrate voltage generation means, so that the dynamic semiconductor memory device in the self-refresh mode can be operated in a self-refresh mode. The output voltage of the substrate voltage generating means can be made smaller in absolute value than the value during normal mode operation or standby mode, and current consumption in self-refresh mode can be reduced.

Further, the additional substrate voltage generation means detects the end of the self-refresh mode, and temporarily increases the output capability of the substrate voltage generation means at the end of the self-refresh mode.

Thereby, the operation in the next mode can be performed stably and reliably.

Embodiment of the Invention FIG. 2 is a schematic block diagram showing a dynamic semiconductor memory device according to the invention.

Referring to FIG. 2, this dynamic semiconductor memory device includes a substrate bias voltage generation circuit 3 and a self-refresh control signal generator that generates a self-refresh control signal φ in response to a signal externally applied to a terminal 1. circuit 2
including. Self-refresh control signal φ is applied to substrate bias voltage generation circuit 3 and refresh control circuit 91. In the self-refresh operation, the refresh control circuit 91 receives the self-refresh control signal φ
In response to S, the address switching circuit 94 is controlled and the internal address signal generated by the refresh address counter 93 is supplied to the address buffer 95. This internal address signal activates the word line of memory cell array 96 and refreshes the memory cells. The address counter 93 is controlled by a built-in timer 92 through the refresh control circuit 91, which sequentially activates the word lines and refreshes all memory cells.

FIG. 1 is a block diagram showing an embodiment of a substrate bias voltage generating circuit for a dynamic semiconductor memory device according to the present invention.

Referring to FIG. 1, this substrate bias voltage generation circuit is as follows:
A substrate bias voltage generation section 31 that includes a ring oscillator 311 and generates a substrate bias voltage, a self-refresh control signal generation circuit 2 that operates in response to an external state control signal, a substrate potential detection circuit 321, and a control circuit 322. A control section 32 including a substrate bias voltage generation section 3
1 and an additional substrate bias voltage generating section 33 whose output is coupled to the output of 1.

The substrate bias voltage generating section 31 has almost the same configuration as the conventional substrate bias voltage generating circuit 41 explained in FIG. 15. The control section 32 includes a substrate potential detection circuit 321 connected to the self-refresh control signal generation circuit 2 and the output VB[1, and a control circuit 322 connected thereto and controlling the ring oscillator 311. The additional substrate bias voltage generation section 33 includes a self-refresh completion detection circuit 33.
1, a control circuit 332, and a circuit 336 having a ring oscillator 333. The circuit 336 has the same circuit configuration as the substrate bias voltage generating section 31.

3 and 4 are both circuit diagrams showing an example of the self-refresh control signal generation circuit 2. In FIG.

FIG. 3 shows a case where a dedicated control signal T is applied from the outside, and when the external signal T at a low level is applied, the inverter 21 outputs an output signal φ at a high level. Signal T
, is at a high level or in an oven state, the input of the inverter 21 is pulled up by the high resistance R3, so the inverter 21 outputs a low level signal φ.

FIG. 4 shows a case where the external τ1 signal and the CAS signal are used, and the RAS signal is sent to the RS flip-flop 22.
The CAS signal is also input to the reset manual power R of the RS flip-flop 22. One output Q of the RS flip-flop is connected to the input of the comparator 23. Timer 24 is connected to comparison circuit 23.

In operation, in the CAS before RAS refresh state, flip-flop 22 is set and the output CbR
becomes high level. The timer 24 then operates, and after a certain period of time T, when the output CbR is at a high level, the comparison circuit 23
outputs a high level signal φ8. When the CAS signal goes high, the flip-flop 22 is reset;
The output CbR becomes low level, and the signal φ becomes low level.

FIG. 5 is a timing chart for explaining the operation of the substrate bias voltage generation circuit of FIG. 1. The operation of this substrate bias voltage generation circuit will be explained below with reference to FIGS. 1 and 5.

First, the operation when the self-refresh control signal φ is at a high level, that is, in the self-refresh mode, will be described.

It is assumed that this substrate bias voltage generation circuit starts its operation from time 1 (,).
The level of SI11 begins to decrease.

At time t, the output Vl11a reaches a predetermined level V8.
When reaching 8L., the substrate potential detection circuit 321 outputs a low-level detection signal φ0, and the control circuit 322 receives this and outputs a low-level control signal φ at time tea. is output to stop the oscillation of the ring oscillator 311.

After that, the level of the output Vaa decreases to V due to some reason.
When VB8H becomes higher than BaL, the substrate potential detection circuit 321 detects this and outputs a high level detection signal φ0. The ring oscillator 311 receives this detection signal φ. Oscillation is resumed at time t2Q in response to control signal φC generated in response to .

Thus, in the refresh mode, the control section 32 mainly controls the intermittent operation of the ring oscillator 311, but the additional substrate bias voltage generation section 33 operates when the refresh mode ends.

At time tH, the self-refresh mode operation ends, and at the same time, the self-refresh control signal φ changes to low level. Self-refresh completion detection circuit 33
1 outputs a self-refresh end signal φE, which is a one-shot pulse, in response to the signal φ. Control circuit 3
32 is a ring oscillator 33 in response to this signal φE.
3 starts oscillation. At this time, ring oscillator 3
Since ring oscillator 11 also oscillates when the signal φ changes to a low level, both ring oscillators 311 and 333 oscillate during the period from time 1E to time tF. As a result, the output VBa is rapidly brought to a predetermined deep level Va BD (VBa o is a level deeper than v[1 [IL)].

At time tF, the substrate potential detection circuit 321 has a level v
By detecting BaD and outputting a low level detection signal φ0, the control signal φ output from the control circuits 322 and 332
. , and φ. 2 are both at a low level. Therefore, both ring oscillators 311 and 333 stop their oscillation operations.

After that, in other modes, when the level of the output VB[l becomes shallow, the control signal φ. 1 becomes high level, and only the ring oscillator 311 operates in oscillation.

In this way, in the substrate bias voltage generation circuit of FIG.
In the self-refresh mode, the voltage of the output VBl11 can be controlled within a shallow range of va a H to V13 [IL, and the current consumption at that time can be reduced.

FIG. 6 is a circuit diagram showing an example of a ring oscillator circuit used in the present invention.

Referring to FIG. 6, this ring oscillator 311 includes an odd number of inverters l connected in series.

-In, and an AND game (-An) having two inputs and one input of which is connected to the output of an odd number of connected inverters. The other input of the AND gate An is the control signal φ.
c1 is given. The output of the AND gate An and the input of the odd-numbered inverters are connected together. This circuit controls the start and stop of the oscillation of the ring oscillator 311 in response to the control signal φC7.

FIG. 7 is a circuit diagram showing an example of a substrate potential detection circuit used in the present invention, and a graph showing voltage hysteresis at a node in the circuit.

Referring to FIG. 7, this substrate potential detection circuit includes a control section that receives the voltage of the output Vaa of the substrate bias voltage generation circuit and operates in response to a self-refresh control signal φ;
and a hysteresis circuit unit coupled to the control unit to perform a hysteresis operation.

The control section consists of a series connection of a P-channel MOS) transistor Q and an N-channel MOS) transistors Q4 and Q5, and
The parallel connection of channel MOS transistors Q6 and Q7 are connected in series. The gates of transistors Q3 and Q4 are connected to ground Vss. The connection point between transistors Q3 and Q4 constitutes a node N. The connection point between transistors Q4 and Qs constitutes node N2. The connection point between transistors Q5 and Q6 constitutes node N3. One terminal of each of the transistors Q and Q7 is coupled to form a node N4, to which the output VllIB of the substrate bias voltage generation circuit is connected. A self-refresh control signal φ is applied to the gate of transistor Q7.

The hysteresis circuit section consists of P-channel MOS transistors Q8 and Q+o and N-channel MOS transistor Q9.
and Q++, and a P-channel MOS) transistor Q.

2 and an N-channel MOS) transistor QI3. The connection point between transistors Q8 and Q9 is connected to node N. The connection point between transistor Q+o and transistor Q++ constitutes node N3, which is connected to the input of the inverter. From the inverter output,
A detection signal φp is output.

In the following description, in order to simplify the explanation, it is assumed that the threshold voltages of all N-channel transistors 4 to Q are IV. Further, the self-refresh control signal φ is a signal that is at a low level in the normal mode and is at a high level in the self-refresh mode. Furthermore, it is assumed that when the detection signal φ0 is at a high level, the ring oscillator is oscillated, and when the detection signal φ0 is at a low level, the oscillation of the ring oscillator is stopped.

First, the operation in normal mode will be explained. When the output V[l[1 is shallow, for example 0, the threshold voltage of transistors Q and Q6 causes the node N2
is brought to a level above Ov. Therefore, transistor Q4 is turned off. Node N is brought to a high level by transistor Q. Therefore, the detection signal φ
0 is a high level, and the level of output VB[l is the 15th
As explained in the figure, the ring oscillator becomes deeper.

When the output V[IB goes deeper than -3V, node N2 is brought to a level below -IV by the threshold voltages of transistors Q and Q. Therefore, transistor Q,
turns on. In other words, both transistors Q and Q are turned on, but by appropriately selecting the ratio of the conductances of transistors Q and Q, the node N,
can be brought to a low level. At this time, the detection signal φ is at a low level. is output, the oscillation of the ring oscillator is stopped and current consumption is reduced. Thereafter, when the output Vaa becomes shallower than 13V for some reason, the detection signal φ0 becomes high level again and the ring oscillator restarts oscillation.

In the hysteresis circuit section in 22, when the node N, attempts to fall from a high level to a low level in response to a change in the voltage of the output VB[1, the node N.

Since it is brought to a high level by transistor Q8, it takes time for it to go to a low level.

However, if node N, is brought to a high level by transistor (Lo), node N, is quickly brought to a low level through transistor Q9.
When changing from a low level to a high level, the voltage changes with a similar width, so the voltage at the node N1 changes with hysteresis as shown in FIG. Therefore, the output Vaa of the substrate bias voltage generating circuit changes with hysteresis as shown in FIG. 8 with respect to a predetermined level VBas.

FIG. 8 is a graph showing the correspondence between changes in the output voltage of the substrate bias voltage generation circuit and the detection signal φ0.

Next, referring again to FIG. 7, the operation in the self-refresh mode will be described. In this case, since the self-refresh control signal φ is at a high level, transistor Q is turned on, thus bringing nodes N and N4 to the same potential. When the level of the output Vaa of the substrate bias voltage generation circuit becomes deeper than 12V, the ring oscillator stops oscillating. In other words, since the level of the output VB[1 is controlled to be shallower than in normal mode operation,
The amount of charge that needs to be supplied to the ring oscillator is small;
Therefore, power consumption is reduced.

FIG. 9 is a circuit diagram showing an example of a control circuit used in accordance with the present invention. FIG. 9 is the simplest example of the control circuit 322 shown in FIG.
3 is shown.

FIG. 10 is a circuit diagram showing an example of a self-refresh completion detection circuit used in the present invention. This self-refresh completion detection circuit 331 includes a NOR element Nr having two functions, and an inverter 1 that constitutes a delay circuit.
1 to Im (m is an odd number).

FIG. 11 is a timing chart for explaining the operation of the circuit shown in FIG. 10. As shown in FIG. 11, in response to the self-refresh control signal φ, this circuit 331 sends a one-shot pulse having a pulse width corresponding to the delay time Td determined by the delay circuit at the end of the self-refresh mode to the end detection signal. Output as φE.

FIG. 12 is a circuit diagram showing an example of the control circuit 332 used in the present invention. This control circuit 332 includes an RS flip-flop 334 and an inverter 335.

The set terminal S of the flip-flop 334 is connected to receive the self-refresh completion detection signal φ[, and the reset terminal R is connected to receive the detection signal φD inverted by the inverter 335.

In operation, flip-flop 334 receives signal φE which temporarily becomes high level at the end of self-refresh mode, is set, and outputs high level control signal φc2. As a result, as described above, the ring oscillator 333 of the additional substrate bias voltage generating section 33 is activated. Note that at this time, the self-refresh control signal φ has already been applied.

is at a low level, so the substrate potential detection circuit 321
is designed to detect a predetermined deep level in normal mode.

In the above description of the embodiments, an additional substrate bias voltage generation section has been shown as a means for temporarily increasing the bias capability of the substrate bias voltage generation circuit, but the present invention is not limited to this, and for example, as shown in FIG. A means for temporarily increasing the oscillation frequency of a ring oscillator as shown in FIG. 14 (N-channel MOS transistor Q+s), or a means for temporarily increasing the capacitance of a charge pump capacitor as shown in FIG. N channel MO
Similar effects can be obtained by using either of the S transistors Q+7 and Q+a).

[Effects of the Invention] As described above, according to the present invention, there is provided a substrate voltage generation means having a ring oscillator circuit means, and a ring oscillator control means for controlling the ring oscillator circuit means in response to the output voltage and state control signal thereof. and additional substrate voltage generation means that temporarily increases the output capability of the substrate voltage generation means at the end of the self-refresh operation, so that power consumption in the self-refresh mode can be reduced, and power consumption in the self-refresh mode can be reduced. It is possible to obtain a dynamic semiconductor memory device that can stably and reliably perform operations in subsequent modes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a substrate bias voltage generating circuit according to the present invention. FIG. 2 is a schematic block diagram showing a dynamic semiconductor memory device to which the present invention is applied. FIGS. 3 and 4 are a circuit diagram and a block diagram, respectively, showing specific examples of a self-refresh control signal generation circuit used in the present invention. FIG. 5 is a timing chart for explaining the operation of FIG. 1. FIG. 6 is a circuit diagram showing an example of a ring oscillator used in the present invention. 7th
The figure is a circuit diagram showing an example of a substrate potential detection circuit used in the present invention. FIG. 8 is a graph showing voltage fluctuations for explaining the operation of FIG. 7. Figure 9 shows
FIG. 3 is a diagram showing an example of a control circuit 322 used in the present invention. FIG. 10 is a circuit diagram showing an example of a self-refresh completion detection circuit used in the present invention. FIG. 11 is a timing chart for explaining the operation of FIG. 10. FIG. 12 is a diagram showing an example of the Lurie control circuit 332 used in the present invention. FIG. 13 is a circuit diagram showing means for temporarily increasing the bias capability of the substrate bias voltage generating circuit used in another embodiment of the present invention. FIG. 14 is a circuit diagram showing means for temporarily increasing the bias capability of the substrate bias voltage generating circuit used in still another embodiment of the present invention. FIG. 15 is a circuit diagram showing a conventional substrate bias voltage generation circuit. FIG. 16 is a waveform diagram for explaining the operation of FIG. 15. FIG. 17 is a circuit diagram showing another conventional substrate bias voltage generation circuit. In the figure, 1 is an external terminal, 2 is a self-refresh control signal generation circuit, 3 is a substrate bias voltage generation circuit, and 31
31 is a substrate bias voltage generation section, 32 is a ring oscillator control section, 33 is an additional substrate bias voltage generation section, and 311 is a substrate bias voltage generation section;
and 333 are ring oscillators, 321 is a substrate potential detection circuit, 322 and 332 are control circuits, 331 is a self-refresh completion detection circuit, 41 is a conventional substrate bias voltage generation circuit, 411 is a ring oscillator, 442 is a substrate potential detection circuit, 443 is a control circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A dynamic semiconductor memory device having a self-refresh function, comprising a ring oscillator circuit means, a substrate voltage generation means for generating a substrate bias voltage, and a state of the semiconductor memory device from the outside. control signal generating means for receiving a state control signal and generating a control signal for controlling the ring oscillator circuit means; and controlling the ring oscillator circuit means in response to the output voltage of the substrate voltage generating means and the control signal. and additional substrate voltage generation means for detecting the end of a self-refresh operation and temporarily increasing the output capability of the substrate voltage generation means at the end of the self-refresh operation. .