JPH0778992B2 - Dynamic semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device, and more particularly to a dynamic semiconductor memory device capable of generating a substrate bias voltage with low power consumption.

[Prior Art] In recent years, personal computers (hereinafter abbreviated as PCs) have become extremely popular. In particular, recently, the demand for portable PCs is increasing. A storage device used for a portable PC is required to have a low power consumption capable of battery backup.

As such a memory device, a dynamic semiconductor memory device or a static semiconductor memory device is usually used. Of these, the dynamic semiconductor memory device is a MOS
It uses the principle of storing information charges in a capacitor. However, since the accumulated charge is gradually lost due to junction leakage or the like, it is necessary to rewrite the accumulated information at a certain fixed time. This rewriting operation is called refresh. When a dynamic semiconductor memory device is used in a portable PC, it is necessary to refresh at regular intervals even during battery backup.

On the other hand, in the dynamic semiconductor memory device,
Only refresh, ▲ ▼ before ▲ ▼
A normal refresh mode such as refresh is executed by being controlled one cycle by an external clock signal. Therefore, it is not preferable to use such a normal refresh mode at the time of battery backup because complicated control is required.

To solve this problem, for example, Yamada et al. “Au
64Kbit MOS Dynamic RA with built-in to / Self Refresh function
Transactions of the Institute of Electronics and Communication Engineers (83/1 vol.J66-C,
No. 1, pp, 62-69.), A dynamic semiconductor having a self-refresh (self-refresh) mode in which an address counter and a timer are built in and the refresh operation is automatically continued. A storage device has been devised and is commercially available.

This self-refresh operation is described in detail in the above-mentioned document, but will be briefly described below.

The signal ▲ ▼ for controlling the standby state and the operating state of the dynamic semiconductor memory device is kept at a high level (standby state), and the refresh control signal ▲ ▼ is kept at a low level for a timer set time (16 μs or less). Continuing, the self-refresh mode is started, and the refresh address counter operates every 16 μs or less set by the built-in timer, and the row address is selected and refreshed. As long as ▲ ▼ is kept at a low level, for example, in the case of 64K, this self-refresh mode is continued, and like the normal refresh mode, 128 cycles are refreshed every 2 ms or less to refresh all memory cells. To be done.

FIG. 15 is a circuit diagram showing a substrate bias voltage generation circuit of a conventional dynamic semiconductor memory device having a self-refresh (self-refresh) mode.

Referring to FIG. 15, this substrate bias voltage generating circuit 41
Includes a ring oscillator 411, a charge pump capacitor C that receives the output signal of ring oscillator 411, and N-channel MOS transistors Q ₁ and Q ₂ . Incidentally, N _B is an internal node, V _BB shows the output of the substrate bias voltage generating circuit 41.

FIG. 16 is a waveform diagram for explaining the operation of the substrate bias voltage generating circuit shown in FIG. The operation will be briefly described below with reference to FIGS. 15 and 16.

First, when the rising voltage signal of the output signal φ _CP of the ring oscillator 411 is applied to the charge pump capacitor C, the potential of the node N _B rises due to capacitive coupling. Then, the transistor Q ₁ is turned on, so that the potential of the node N _B is clamped to the threshold voltage of the transistor Q ₁ . Then, when the voltage signal of the fall of phi _CP is applied, but decreases the potential at the node N _B by capacitive coupling, turn the transistor Q ₂ is turned on, the voltage level of the output V _BB drops, The potential of node N _B is clamped to a negative potential equal to the threshold voltage of transistor Q ₂ . By repeating such a cycle several times, the level of the output V _BB gradually decreases to a predetermined negative potential.

However, in the standby state of the dynamic semiconductor memory device, the current consumption in the substrate bias voltage generation circuit occupies most of the power consumption, and therefore, in order to reduce this, for example, WM Martino et al.
IEEE JOURNAL (Solid-State Circuits, vol.
As described in SC-15, No. 5, pp. 820-826, oct. 1980), a method of intermittently operating a substrate bias voltage generating circuit has been devised.

FIG. 17 is a circuit diagram showing a substrate bias voltage generating circuit capable of intermittent operation.

Referring to FIG. 17, this substrate bias voltage generating circuit is
Compared to FIG. 15, it further includes a substrate potential detection circuit 442 and a control circuit 443 for controlling ring oscillator 441 in response to the detection signal.

In the operation, the substrate potential detection circuit 442 constantly monitors the substrate voltage (voltage of the output V _BB ), and after this reaches a predetermined level, the control circuit 443 stops the oscillation of the ring oscillator 441, and this portion The power consumption of is reduced. If the substrate potential becomes shallower than the predetermined level for some reason, the ring oscillator 44
1 is configured to work.

[Problems to be Solved by the Invention] Since the conventional dynamic semiconductor memory device is configured as described above, the substrate bias voltage generating circuit is the same in both the normal mode operation and the self refresh mode operation. Since electric power is consumed, there is a problem that unnecessary electric power is consumed, for example, at the time of battery backup.

The present invention has been made to solve the above problems, and by reducing the power consumption of the substrate bias voltage generation circuit in the self-refresh mode to that in the normal operation mode, unnecessary power consumption is reduced. An object is to obtain a reduced dynamic semiconductor memory device.

[Means for Solving the Problem] A dynamic semiconductor memory device according to the present invention is a dynamic semiconductor memory device having a self-refresh function, which has a ring oscillator circuit means for generating a substrate bias voltage. Substrate voltage generating means, a state control signal for controlling the state of the semiconductor memory device from the outside, and a control signal generating means for generating a control signal, and an output voltage of the substrate voltage generating means and a response signal to the control signal. A ring oscillator control means for controlling the ring oscillator circuit means, a detection means for detecting the end of the self refresh operation in response to the control signal, and a self refresh operation end in response to the detection output of the detection means. And occasionally additional substrate voltage generating means for temporarily increasing the output capability of the substrate voltage generating means.

[Operation] In the dynamic semiconductor memory device according to the present invention, the ring oscillator control means controls the operation of the ring oscillator circuit means in response to the output voltage of the substrate voltage generation means and the control signal, so that the operation in the self-refresh mode is performed. The output voltage of the substrate voltage generating means can be made smaller in absolute value than the value in the normal mode operation or the standby mode, and the current consumption in the self-refresh mode can be reduced.

Furthermore, the dynamic semiconductor memory device according to the present invention can detect the end of the self-refresh operation and temporarily increase the output capability of the substrate voltage generating means immediately after the end of the self-refresh operation. As a result, the operation in the mode following the self-refresh mode can be stably and reliably performed immediately after the change.

[Embodiment of the Invention] FIG. 2 is a schematic block diagram showing a dynamic semiconductor memory device according to the present invention.

Referring to FIG. 2, this dynamic semiconductor memory device includes a substrate bias voltage generating circuit 3 and a self-refresh control signal generating circuit for generating self-refresh control signal φ _S in response to a signal externally applied to terminal 1. Circuit 2
Including and Self refresh control signal φ _S is applied to substrate bias voltage generating circuit 3 and refresh control circuit 91. In the self-refresh operation, the refresh control circuit 91 controls the address switching circuit 94 in response to the self-refresh control signal φ _S to supply the address buffer 95 with the internal address signal generated by the refresh address counter 93. This internal address signal activates the word line of the memory cell array 96 to refresh the memory cell. The increment of the address counter 93 is performed by the built-in timer 92 through the refresh control circuit 91, whereby word lines are sequentially activated and all memory cells are refreshed.

FIG. 1 is a block diagram showing an embodiment of a substrate bias voltage generating circuit of a dynamic semiconductor memory device according to the present invention.

Referring to FIG. 1, the substrate bias voltage generating circuit
A substrate bias voltage generation unit 31 including a ring oscillator 311 for generating a substrate bias voltage, a self-refresh control signal generation circuit 2 which operates in response to a state control signal from the outside, a substrate potential detection circuit 321 and a control circuit 322. It includes a control unit 32 that includes it, and an additional substrate bias voltage generation unit 33 whose output is coupled to the output of the substrate bias voltage generation unit 31.

The substrate bias voltage generating unit 31 has almost the same structure as the conventional substrate bias voltage generating circuit 41 described in FIG.
The control unit 32 controls the substrate potential detection circuit 321 connected to the self-refresh control signal generation circuit 2 and the output V _BB, and the control circuit 322 for controlling the ring oscillator 311 connected thereto.
Including and The additional substrate bias voltage generator 33 includes a self-refresh end detection circuit 331, a control circuit 332, and a circuit 336 having a ring oscillator 333. Circuit 336
Has the same circuit configuration as the substrate bias voltage generator 31.

3 and 4 are circuit diagrams each showing an example of the self-refresh control signal generating circuit 2.

FIG. 3 shows a case where a dedicated control signal T _S is given from the outside, and when the low level external signal T _S is given, the inverter
21 outputs a high level output signal φ _S. When the signal T _S becomes the high level or the open state, the input of the inverter 21 is pulled up by the high resistance R _S, so that the inverter 21 outputs the low level signal φ _S.

Fig. 4 shows the ▲ ▼ signal and ▲ ▼ from the outside.
When using the signal, the ▲ ▼ signal is the set input S of the RS flip-flop 22, and the ▲ ▼ signal is the RS signal.
It is input to the reset input R of the flip-flop 22. RS
One output Q of the flip-flop is connected to the input of the comparator 23. The timer 24 is connected to the comparison circuit 23.

In operation, the flip-flop 22 is set and the output is
CbR goes high. The timer 24 operates thereafter, and when the output CbR is at a high level for a certain period of time T, the comparison circuit 23 outputs a high level signal φ _S. Flip-flop 22 is reset when the signal goes high,
The output CbR becomes low level and the signal φ _S becomes low level.

FIG. 5 is a timing chart for explaining the operation of the substrate bias voltage generating circuit of FIG. The operation of the substrate bias voltage generating circuit will be described below with reference to FIGS. 1 and 5.

First, the operation when the self-refresh control signal φ _S is at a high level, that is, in the self-refresh mode will be described.

This substrate bias voltage generation circuit is assumed to start operating at time t ₀ . Output signal φ of ring oscillator 311
Due to the charge pump action of _CP, the level of output V _BB begins to drop. At time t ₁ , when the output V _BB reaches the predetermined level V _BBL , the substrate potential detection circuit 321 outputs a low level detection signal φ _D , and the control circuit 322 receives this and controls the low level at time t _1a . The signal φ _C is output and the oscillation of the ring oscillator 311 is stopped.

After that, the output V _BB level _changes to V _{BBL for} some reason.
When it becomes higher than V _BBH , the substrate potential detection circuit 321 detects it and outputs a high level detection signal φ _D. Ring oscillator 311 receives control signal φ _C generated in response to detection signal φ _D , and restarts oscillation at time t _2a .

In this way, the control unit 32 mainly controls the intermittent operation of the ring oscillator 311 in the refresh mode, but the additional substrate bias voltage generation unit 33 operates at the end of the refresh mode.

At time t _E , the self-refresh mode operation ends, and at the same time, the self-refresh control signal φ _S changes to low level. Self refresh end detection circuit 331
Outputs a self-refresh end signal φ _E which is a one-shot pulse in response to the signal φ _S. Control circuit 332
Causes the ring oscillator 333 to start oscillating in response to the signal φ _E. At this time, the ring oscillator 311 also oscillates when the signal φ _S changes to the low level, so that both ring oscillators 311 and 333 oscillate during the period from time t _E to time t _F. This allows
The output V _BB is rapidly brought to a predetermined deep level V _BBD (V _BBD is deeper than V _BBL ).

At time t _F , the substrate potential detection circuit 321 detects the level V _BBD and outputs the low level detection signal φ _D , so that the control signals φ _C1 and φ _C2 output from the control circuits 322 and 332 are both low level. Becomes Therefore, ring oscillators 311 and 333
Both stop the oscillation operation.

After that, in another mode, when the level of the output V _BB becomes shallow, only the control signal φ _C1 becomes high level, and only the ring oscillator 311 oscillates.

As described above, in the substrate bias voltage generating circuit of FIG.
In self-refresh mode, the voltage of output V _BB is changed to V _BBH
Or V _BBL can be controlled within a shallow range, and the current consumption at that time can be reduced.

FIG. 6 is a circuit diagram showing an example of a circuit of the ring oscillator used in the present invention.

With reference to FIG. 6, the ring oscillator 311 to inverters I ₁ of the even-numbered stages connected in series with I _n, whereas the input connected to the output of the inverter of the even-numbered stages connected has two inputs Including AND gate An. The control signal φ _C1 is applied to the other input of the AND gate An. The output of the AND gate An and the input of the even-stage connected inverter are integrally connected. With this circuit, the ring oscillator 311 controls the start and stop of its oscillation operation in response to the control signal φ _C1 .

FIG. 7 is a circuit diagram showing an example of the substrate potential detection circuit used in the present invention and a graph showing voltage hysteresis at node points in the circuit.

Referring to FIG. 7, the substrate potential detecting circuit receives a voltage of output V _BB of the substrate bias voltage generating circuit and is coupled to the control unit which operates in response to the self-refresh control signal φ _S. And a hysteresis circuit section that performs a hysteresis operation. The control unit includes a P-channel MOS transistor Q ₃ , a N-channel MOS transistor Q ₄ and Q ₅ connected in series and a N-channel MOS transistor Q ₆ and Q ₇ connected in parallel. The gates of transistors Q ₃ and Q ₄ are connected to ground V _SS . The connection point between the transistors Q ₃ and Q ₄ constitutes the node N ₁ . The connection point between the transistors Q ₄ and Q ₅ constitutes the node N ₂ . The connection point between the transistors Q ₅ and Q ₆ constitutes the node N ₃ . One terminal of each of the transistors Q ₆ and Q ₇ is coupled to form a node N _4, to which the output V _BB of the substrate bias voltage generating circuit is connected. Transistor Q
_The self-refresh control signal φ _S is applied to the gate of ₇ .

The hysteresis circuit section is a P-channel MOS transistor Q ₈
And Q ₁₀ and N-channel MOS transistors Q ₉ and Q _11, and a flip-flop circuit, and an inverter formed of P-channel MOS transistor Q ₁₂ and N-channel MOS transistor Q ₁₃ . The connection point between the transistors Q ₈ and Q ₉ is connected to the node N ₁ . Transistor Q ₁₀ and transistor Q
The connection point with ₁₁ constitutes node N ₅ and is connected to the input of the inverter. The detection signal φ _D is output from the output of the inverter.

In the following description, for simplification of explanation, the threshold voltages of the N-channel transistors Q ₄ to Q ₇ are all 1V.
Suppose that Further, the self-refresh control signal φ _S is a signal which is low level in the normal mode and is high level in the self-refresh mode. Furthermore, it is assumed that the ring oscillator oscillates when the detection signal φ _D is at a high level, and the oscillation of the ring oscillator is stopped when the detection signal φ _D is at a low level.

First, the operation in the normal mode will be described. If the output V _BB is shallow, for example 0V, the transistor Q
The threshold voltages of ₅ and Q ₆ bring node N ₂ to a level above 0V. Therefore, the transistor Q ₄ turns off. Node N ₁ is brought high by transistor Q ₃ . Therefore, the detection signal φ _D is at a high level,
The level of the output V _BB becomes deeper by the ring oscillator, as described in FIG.

When the output V _BB goes deeper than −3V, the node N ₂ is brought to a level lower than −1V by the threshold voltage of the transistors Q ₅ and Q ₆ . Therefore, the transistor Q ₄ turns on. That is, both the transistors Q ₃ and Q ₄ are turned on, but the node N ₁ can be brought to a low level by appropriately selecting the ratio of the conductances of the transistors Q ₃ and Q ₄ . At this time, since the low-level detection signal φ _D is output, the oscillation of the ring oscillator is stopped and the current consumption is reduced. After that, the output V _BB is −3 for some reason.
When it becomes shallower than V, the detection signal φ _D becomes high level again, and the oscillation of the ring oscillator is restarted.

Here, in the hysteresis circuit section, the node N ₁ outputs V
_When trying to go from a high level to a low level in response to a change in the voltage of _BB , it takes time for the node N ₁ to go to a low level because it is brought to a high level by the transistor Q ₈ . However, if the node N ₅ is brought to a high level by the transistor Q _10, the node N ₁ is transistor Q ₉
Is rapidly brought to a low level via. Conversely, the node
Similarly, when N ₁ changes from low level to high level, it also changes with a certain width, so that the voltage of the node N ₁ changes with hysteresis as shown in FIG. Therefore, the output V _BB of the substrate bias voltage generating circuit changes with hysteresis as shown in FIG. 8 with respect to a predetermined level V _BBS .

FIG. 8 is a graph showing the correspondence between changes in the output voltage of the substrate bias voltage generating circuit and the detection signal φ _D.

Next, referring to FIG. 7 again, the operation in the self refresh mode will be described. In this case, since the self-refresh control signal φ _S is high level, the transistor Q ₇ is turned on, and therefore the nodes N ₃ and N ₄ are brought to the same potential. The oscillation of the ring oscillator stops when the level of the output V _BB of the substrate bias voltage generator becomes deeper than −2V. That is, since the level of the output V _BB is controlled to be shallower than that in the operation in the normal mode, the amount of charges to be supplied to the ring oscillator may be small, thus reducing the power consumption.

FIG. 9 is a circuit diagram showing an example of the control circuit used by the present invention. FIG. 9 is a simplest example of the control circuit 322 shown in FIG. 1, and a delay buffer 323 is shown.

FIG. 10 is a circuit diagram showing an example of a self-refresh end detection circuit used in the present invention. This self-refresh end detection circuit 331 is a NOR having two inputs.
The element Nr and the inverters I ₁ to I forming the delay circuit
_m (m is an odd number) and.

FIG. 11 is a timing chart for explaining the operation of the circuit of FIG. This circuit, as shown in Figure 11,
In response to the self-refresh control signal φ _S , 331 outputs a one-shot pulse having a pulse width corresponding to the delay time Td determined by the delay circuit as the end detection signal φ _E at the end of the self-refresh mode.

FIG. 12 is a circuit diagram showing an example of the control circuit 332 used in the present invention. The control circuit 332 includes an RS flip-flop 334 and an inverter 335. The set terminal S of the flip-flop 334 is connected to receive the self-refresh end detection signal φ _E , and the reset terminal R is connected to receive the detection signal φ _D inverted by the inverter 335.

In operation, the flip-flop 334 outputs the signal φ that temporarily becomes high level at the end of the self-refresh mode.
Upon receiving _E , it is set and outputs a high level control signal φ _C2 . As a result, the ring oscillator 333 of the additional substrate bias voltage generator 33 is activated as described above.
At this time, the self-refresh control signal φ _S
Is at a low level, the substrate potential detection circuit 321 detects a predetermined deep level in the normal mode.

In the above description of the embodiments, as a means for temporarily increasing the bias capability of the substrate bias voltage generating circuit, an additional substrate bias voltage generating section is provided, but the present invention is not limited to this. For example, FIG. A means for temporarily increasing the oscillation frequency of the ring oscillator as shown in (N-channel MO
S transistor Q ₁₆ ) or means for temporarily increasing the capacitance of the charge pump capacitor as shown in FIG. 14 (capacitor C ₂ and N channel MOS transistor Q
The same effect can be obtained by using either of ₁₇ and Q ₁₈ ).

As described above, according to the present invention, the substrate voltage generation means having the ring oscillator circuit means and the ring oscillator control means for controlling the ring oscillator circuit means in response to the output voltage and the state control signal thereof. And a detection means for detecting the end of the self-refresh operation, and an additional substrate voltage generation means for temporarily increasing the output capability of the substrate voltage generation means at the end of the self-refresh operation. It is possible to obtain a dynamic semiconductor memory device which can reduce the number of charges and can perform its operation in a stable and reliable manner immediately after changing to a mode after the self-refresh mode.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a substrate bias voltage generating circuit according to the present invention. FIG. 2 is a schematic block diagram showing a dynamic semiconductor memory device to which the present invention is applied. FIGS. 3 and 4 are a circuit diagram and a block diagram showing a specific example of the self-refresh control signal generating circuit used in the present invention. FIG. 5 is a timing chart for explaining the operation of FIG. FIG. 6 is a circuit diagram showing an example of a ring oscillator used in the present invention. 7th
FIG. 1 is a circuit diagram showing an example of a substrate potential detecting circuit used in the present invention. FIG. 8 is a graph showing the voltage fluctuation for explaining the operation of FIG. Figure 9 shows
It is a figure which shows an example of the control circuit 322 used in this invention. FIG. 10 is a circuit diagram showing an example of a self-refresh end detection circuit used in the present invention. FIG. 11 is a timing chart for explaining the operation of FIG. FIG. 12 is a diagram showing an example of the control circuit 332 used in the present invention. FIG. 13 is a circuit diagram showing means for temporarily increasing the bias capability of the substrate bias voltage generating circuit used in another embodiment of the present invention. FIG. 14 is a circuit diagram showing means for temporarily increasing the bias capability of the substrate bias voltage generating circuit used in still another embodiment of the present invention. Figure 15 shows
It is a circuit diagram which shows the conventional substrate bias voltage generation circuit.
FIG. 16 is a waveform diagram for explaining the operation of FIG. FIG. 17 is a circuit diagram showing another conventional substrate bias voltage generating circuit. In the figure, 1 is an external terminal, 2 is a self-refresh control signal generator, 3 is a substrate bias voltage generator, 31 is a substrate bias voltage generator, 32 is a ring oscillator controller, 33 is an additional substrate bias voltage generator, 311 and 333 are ring oscillators, 321 is a substrate potential detection circuit, 322 and 332 are control circuits, 331 is a self-refresh end detection circuit, 41
Is a conventional substrate bias voltage generation circuit, 411 is a ring oscillator, 442 is a substrate potential detection circuit, and 443 is a control circuit. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A dynamic semiconductor memory device having a self-refresh function, comprising ring oscillator circuit means, a substrate voltage generating means for generating a substrate bias voltage, and a state of the semiconductor memory device from the outside. Control signal generating means for receiving a state control signal for controlling and generating a control signal, and for controlling the ring oscillator circuit means in response to the output voltage of the substrate voltage generating means and the control signal. Ring oscillator control means, detection means for detecting the end of the self-refresh operation in response to the control signal, and substrate voltage generation means for temporarily ending the self-refresh operation in response to the detection output of the detection means. And a substrate voltage generating means for enhancing the output capability of the dynamic semiconductor memory device.