JPH01235095A - Dynamic semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the size of a dynamic semiconductor memory by using a substrate bias voltage generating circuit which performs intermittent actions via an oscillation means both as a voltage holding means for a timer means which produces a timing signal for refresh and a word line driving signal generating means. CONSTITUTION:A timer means 3 and a voltage holding means 21 can always work based on the output of a ring oscillator 2. At the same time, the output of a substrate bias voltage generating means 1 is detected and ON/OFF switching control is applied to the means 1 via the oscillator 2 based on the output voltage of the means 1. In other words, an intermittent action state can be set by a switching control means 5 so that the means 1 is actuated only when required. Thus the oscillator 2 itself is always working together with reduction of power consumption. As a result, the oscillator 2 can serve as the means 21 and the means 3. Then it is possible to use the oscillator 2 both as the means 21, the means 1 and the means 3 respectively. Thus the size of a dynamic semiconductor memory can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a dynamic semiconductor memory device, which has a built-in address counter and a timer, is capable of self-refresh mode operation, and is capable of controlling the output of a word line drive signal generation circuit. The present invention relates to a dynamic semiconductor memory device having a voltage holding circuit that holds the voltage higher than a power supply voltage and a substrate bias voltage generating circuit that holds the potential of a semiconductor substrate constant.

[Prior Art] In recent years, personal computers have become extremely popular, and in particular,
Recently, demand for portable personal computers has increased. The storage device used in such a portable personal computer needs to be low power consumption and capable of battery backup (battery retention). As such a memory device, a dynamic type semiconductor memory device or a static type semiconductor memory device is usually used. Among these, dynamic semiconductor memory devices have the advantage of having simple memory cell configurations and being suitable for high integration. However, on the other hand, since the principle of storing information charges in a capacitor provided on a semiconductor substrate is used, the accumulated charges are gradually lost due to junction leakage, etc.
Therefore, a so-called refresh operation is required to rewrite the stored information at regular intervals. Furthermore, even during the battery backup described above, refreshment must be performed at regular intervals. In a dynamic semiconductor memory device, such refresh is usually performed by a RAS-only refresh, a CAS-before-RAS refresh, or other similar refresh operations, but all of these refresh operations are controlled one cycle at a time by an external clock. Because it is a method to
Rewriting to all memory cells requires complicated control, which is undesirable from the viewpoint of power consumption, especially during the battery backup.

So, for example, "Yamada Noh" Auto/5elf R
64Kbit MOS dynamic RAM with built-in refresh function “IEICE Journal °83/1 vol.
, J66-C, No. 1. pI).

62-69J, a dynamic semiconductor memory device having a self-refresh mode in which an address counter and a timer circuit are built in and automatically continues refreshing has been devised and put into commercial use. Although this self-refresh operation is described in detail in the above-mentioned literature, it will be briefly explained below based on FIG. 2.

FIG. 2 is a block diagram showing a die-tic type semiconductor memory device including a one-pin refresh circuit 50 with a self-refresh function. As shown in FIG. 2, the additional circuitry necessary to provide a refresh function to the position pins is the refresh control 52. Refresh atsre counter 54. A multiplexer 56 and a timer circuit 3 which is an example of timer means. Then, a signal RAS that distinguishes between a standby state and an operating state of the dynamic semiconductor memory device is kept at a high level (hereinafter referred to as "H level") (standby state), and a refresh control signal is externally applied to the refresh control 52. R
When EF goes from H level to low level (hereinafter referred to as "L level"), self-refresh is started, and first, the refresh add counter 54 performs one cycle on the specified address memory cell as in the auto-refresh operation. A refresh operation is performed. That is, the refresh address signal from the refresh address counter 54 is input to the address buffer 60 via the multiplexer 56, and then to the row decoder 62.
Then, the memory cell 58 corresponding to the refresh address is refreshed via the column decoder 64.

When this one cycle of refresh operation is completed, the timer circuit 3 provided in the dynamic semiconductor memory device starts operating, and the refresh control signal is sent over the time (approximately 16 μs) set in the timer circuit 3 in advance. When REF is held at L, the refresh address counter 54 is incremented by 1 bit and the memory cell corresponding to the refresh address is refreshed. After this, the timer circuit 3 starts operating again,
In the same manner as above, the memory cell 58 corresponding to the refresh address further incremented by one bit is refreshed. This series of operations continues as long as the refresh control signal REF is held at L, and as in the normal refresh mode (in the case of 64)
128 cycles of refresh are performed every ms, and all memory cells are refreshed.

On the other hand, in the word line drive signal generation circuit 7, which is an example of the word line drive signal generation means of the dynamic semiconductor memory device, as shown in, for example, Japanese Unexamined Patent Publication No. 59-38996, In order to write data completely, a voltage holding circuit 21 is added, which is an example of voltage holding means for holding the voltage output from the word line drive signal generating circuit 7 higher than the power supply voltage during the access period. This voltage holding circuit 21 receives a repetitive signal generated by a ring oscillator 10, which is an example of an oscillating means, and boosts the word line drive signal for each signal and holds it at a predetermined voltage value. Note that 8 in the figure is a conventionally well-known boost signal generation circuit. Then, the word line drive signal maintained higher than the power supply voltage is sent to the row decoder 6.
2, and data can be written to the memory cell 58.

In addition, numeral 1 in the figure is a substrate bias voltage generation circuit which is an example of a substrate bias voltage generation means, and it generates a potential applied to the semiconductor substrate, that is, a substrate bias voltage, in order to keep the potential of the semiconductor substrate constant and prevent malfunction. It operates in response to a predetermined pulse from the ring oscillator 2. The output pulse from the ring oscillator 2 is also given to the timer circuit 3, and the timer circuit 3 is configured to operate.

FIG. 3 is a diagram showing a conventional circuit including a ring oscillator, a substrate bias voltage generation circuit, and a timer circuit.

In the figure, 1 is a substrate bias voltage generation circuit;
2 is a ring oscillator that creates a pulse waveform whose output level changes alternately between power supply potential VCC and ground potential GND. Based on the output from the ring oscillator 2, the substrate bias voltage generation circuit 1 is configured to output a substrate bias voltage. Further, the substrate bias voltage generation circuit 1 includes an N-channel transistor Q
+, Q2, and a capacitor C, and a capacitor C and an N-channel transistor Q1 are inserted in series in this order between the input side and the output side of this circuit l. The gate of this N-channel transistor Q is connected to the output side. Also, the node N between the capacitor C and the N-channel transistor 705 is connected to the potential GN.
An N-channel transistor Q2 is inserted between the node N and the gate of the N-channel transistor Q2.
1 is connected. Further, the timer circuit 3 is connected to the output side of the ring oscillator 2, and is configured to output a timing signal for self-refresh every preset time (approximately 16 μS) in the timer circuit 3 based on the output signal of the ring oscillator 2. It is configured.

The operation of this substrate bias voltage generation circuit 1 is as follows. First, the output of ring oscillator 2 is at power supply potential v0
° (step 1), the voltage at node N tries to rise to the power supply potential VCC level due to capacitive coupling by capacitor C, but when the voltage at node N rises to the threshold voltage vT2 of N-channel transistor Q2, N
The channel transistor Q2 becomes conductive and further voltage rise is suppressed, so that the node N becomes the voltage v
It is kept at T2. Next, when the output of the ring oscillator 2 becomes the ground potential GND (step 2), the voltage at the node N becomes the voltage (VT2) due to the capacitive coupling of the capacitor C.
-Vl: C), but when the voltage at node N1 becomes smaller than the voltage (Vt VT + ) at which the threshold voltage VTI of N-channel transistor Q is detected from the voltage VT at terminal T, N-channel transistor Q becomes conductive. state, the voltage at node N does not become much lower.

When step 1 and step 2 are each performed once, the voltage at node N and the voltage vT decrease. Note that the degree is determined by the ratio of the load capacitance of the capacitance C and the voltage VT. Furthermore, when step 1 and step 2 are repeated several times, the voltage at node N1 becomes the voltage (VT 2 - V c (
) and the voltage vT2, and the voltage V is the voltage (
It becomes a constant voltage of VT2-VC(+VTl).

For example, VCc = 5V, VT + "Vt 2-I
V, VT-3V is obtained and applied to the semiconductor substrate (not shown).

By the way, when the semiconductor memory device is in a standby state (control signal RAS
The power consumption in this substrate bias voltage generation circuit 1 occupies most of the power consumption when the voltage is at H level). Therefore, in order to reduce this, for example, rW, L, Mar
tino et at.

, “An On-Chip Back-Bia
sGenerator for MOS Dyn
amic Memory' IEEE J, 5o
lid-3tate C1rcuits, vol.

5G-15, No, 5. pp, 820-826゜oct.
, 1980J, a method of intermittent operation of the substrate bias voltage generating circuit 1 has been devised.

FIG. 4 is a diagram showing an embodiment of the invention. In this figure, the difference from FIG. 3 is that the substrate potential detection circuit 4 detects the output voltage of the substrate bias voltage generation circuit 1.
and a control circuit 5 that controls the operation of the ring oscillator 2 based on the output signal of the substrate potential detection circuit 4. As shown in the figure, the substrate potential is constantly monitored by the substrate potential detection circuit 4, and after the substrate potential reaches a predetermined level, the control circuit 5 stops the oscillation of the ring oscillator 2 and generates a substrate bias voltage. The operation of circuit 1 is also stopped. Further, if the substrate potential becomes higher than a predetermined level for some reason, the ring oscillator 2 is operated again via the control circuit 5. In this way, the substrate bias voltage generation circuit 1 operates intermittently based on the substrate potential,
Efforts are being made to reduce power consumption.

Next, the operation of the word line drive signal generation circuit 7 shown in FIG. 2 will be explained using the circuit diagram shown in FIG.

In FIG. 5, 7 is a word line drive signal generation circuit for generating a word line drive signal φ1; 8 is a boost signal generation circuit for generating a boost signal φP for boosting the word line drive signal φ; 9 is a supply terminal for the repetitive signal φ generated by the ring oscillator 10. Further, 11 is a transistor whose one main electrode is connected to the supply terminal 9, the other main electrode is connected to the node N2, and the gate electrode is connected to the output terminal 13 of the boosted signal φP, 14 is the node N2 and the node N,
16 is a charging transistor connected between the power supply terminal 17 and node N3 and has its gate electrode connected to the output terminal 13 of the boosted signal φP; 18 has its drain and gate electrodes connected to the word A rectifying transistor 20 is connected to the output terminal 19 of the line drive signal generation circuit 7, and a clamping transistor 20 has its drain and gate electrode connected to the output terminal 19 of the word line drive signal φ1, and its source connected to the power supply terminal 17. .

FIG. 6 is a signal waveform diagram of each part for explaining the operation of the circuit shown in FIG. 5. At time t, when the transistor 11 is turned on by the rear pressure signal P, the repetition signal φC
When V changes from L to H, the threshold voltage of transistor 11 is subtracted from the change, V-V, M is the boosting capacitance f
It is transmitted to the node N3 through f114, and the node N3
The level of increases, the rectifying transistor 18 turns on, current flows from the node N toward the output terminal 19, and the voltage level of the output terminal 19 increases. Repetitive signal φ. changes from H to L, the rectifying transistor 18 becomes O.
Since it becomes an FF, no current flows from the output terminal 19 to the node N. Although the voltage level of node N3 decreases, it is charged to V-V through charging transistor 16. The above signal φ.

If a series of operations are repeated, including the coupling action of the boosting capacitor 14, charging the node N via the charging transistor 16, and charging the output terminal 19 via the rectifying transistor 18, the voltage at the output terminal 19 will no longer drop.

[Problems to be Solved by the Invention] A conventional semiconductor memory device having a substrate bias voltage generation circuit 1 that operates intermittently is configured as described above, and the ring oscillator 2 is operated intermittently in accordance with the substrate potential.

Therefore, in the configuration shown in FIG. 4, if a self-refresh method incorporating the timer circuit 3 shown in FIG. 3 is adopted, the ring oscillator 2 shown in FIG. It cannot be used as timer circuit 3 as it is, and as a result,
A ring oscillator that constantly oscillates for the timer circuit 3 is newly required, which poses a problem in that the size of the storage device increases. In addition, in the conventional dynamic semiconductor memory device, as shown in FIG. 2, the voltage holding circuit 21 for holding the output of the word line drive signal generating circuit 7 higher than the power supply voltage also has its own ring. Since the oscillator 10 was used, there was a drawback that the size of the semiconductor memory device became larger.

In view of the above-mentioned circumstances, the present invention provides three components: a substrate bias voltage generation circuit that performs intermittent operation using one oscillation means, a timer means for creating a timing signal for self-refresh, and a voltage holding means for the word line drive signal generation means. The object of the present invention is to obtain a small-sized semiconductor memory device that can operate multiple devices at the same time.

[Means for Solving the Problems] A dynamic semiconductor memory device according to the present invention includes a word line drive signal generating means for supplying a word line drive signal to a word line connected to a memory cell, and a word line drive signal generating means for supplying a word line drive signal to a word line connected to a memory cell; oscillation means for deriving the voltage, voltage holding means for holding the output of the word line drive signal generation means higher than a power supply voltage based on the output from the oscillation means, and voltage holding means for holding the output of the word line drive signal generation means higher than the power supply voltage based on the output from the oscillation means; substrate bias voltage generation means for generating a substrate bias voltage for holding the potential constant; and timer means for outputting a timing signal for self-refresh at regular intervals based on the output from the oscillation means; The present invention is characterized in that it includes a switching control means for detecting the output voltage of the substrate bias voltage generation means and controlling conduction or disconnection of the oscillation means to the substrate bias voltage generation means based on the detected voltage.

[Action] The timer means and the voltage holding means can always operate based on the output of the oscillation means, and the output of the substrate bias voltage generation means is detected, and the substrate bias voltage generation from the oscillation means is performed based on the output voltage. Switching control of conduction and cutoff to the means is performed.

In other words, the function of the switching control means enables intermittent operation in which the substrate bias voltage generation means is operated only when necessary, reducing power consumption, while the oscillation means itself is always operating. , the oscillation means can be used both as the voltage holding means and the timer means.

[Embodiment of the Invention] FIG. 1 is a diagram showing an embodiment of the present invention. In the description of this embodiment, the description of parts that overlap with the description of the prior art will be omitted.

1, the difference from the conventional example shown in FIG. 4 is that a ring oscillator 2 and a timer circuit 3 for self-refresh mode are connected, and a switch circuit whose opening/closing is controlled by a control circuit 5. 6 and inverter II
+I2 is connected in series and inserted between the ring oscillator 2 and the capacitor C, and furthermore, the output pulse of the ring oscillator 2 is also applied to the voltage holding circuit 21 shown in FIG. The ring oscillator 2 is connected to the substrate bias voltage generation circuit 1 and the timer circuit 3.
Furthermore, the voltage holding circuit 21 is shared by all three. The inverter I, 12 is a capacitor C.
It is an inverter with relatively high driving capacity for driving the ring oscillator 2 in Fig. 3 or 4.
The size corresponds to the final stage inverter (not shown) in the middle.

Next, the operation will be explained. The operating principle of the substrate bias voltage generation circuit 1 is the same as that of the conventional example shown in FIG. 3 or 4, but in the conventional example shown in FIG. After the ring oscillator 2 reaches the level of The electrical connection between the output of 2 and capacitor C is disconnected. Moreover, when the substrate potential becomes higher than a predetermined level, the switch circuit 6 becomes conductive again via the control circuit 5, and the output side of the ring oscillator 2 and the input side of the inverter (2) are electrically connected, and the substrate bias is applied. The operation of the voltage generating circuit 1 is restarted.

This substrate potential detection circuit 4. A switching control means for detecting the output voltage of the substrate bias voltage generation means by a control circuit 5 and a switch circuit 6, and controlling conduction or disconnection of the oscillation means to the substrate bias voltage generation means based on the detected voltage. is configured.

On the other hand, based on the output of the ring oscillator 2, the timer circuit 3 outputs a timing signal for performing the above-described self-refresh operation at preset intervals (approximately 16 μs).

As described above, one ring oscillator 2 is used to control the outputs of the substrate bias voltage generation circuit 1 that performs intermittent operation, the timer circuit 3 that outputs a timing signal for self-refresh, and the word line drive signal generation circuit 7 from the power supply voltage. Since the three voltage holding circuits 21 that hold the voltage at a high level can operate simultaneously, a small-sized semiconductor memory device can be obtained.

[Effects of the Invention] The present invention having the above-mentioned configuration enables the switching control means to operate the substrate bias voltage generation means intermittently to reduce power consumption, and the oscillation means is connected to the voltage holding means and the substrate bias voltage. By using both the generating means and the timer means, the size can be reduced, and it has become possible to provide a dynamic semiconductor memory device that is small and consumes little power.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a dynamic semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional dynamic semiconductor memory device, and FIG. 3 is a main part of a conventional dynamic semiconductor memory device. FIG. 4 is a circuit diagram showing main parts of another conventional dynamic semiconductor memory device, FIG. 5 is a circuit diagram showing other main parts of a conventional dynamic semiconductor memory device, and FIG. 5 is a signal waveform diagram for explaining the operation of the circuit of FIG. 5. FIG. In the drawing, 7 is a word line drive signal generation circuit which is an example of word line drive signal generation means, 1 is a substrate bias voltage generation circuit which is an example of substrate bias voltage generation means, and 21 is a voltage holding circuit which is an example of voltage holding means. 2 is a ring oscillator which is an example of oscillation means; 3 is a timer circuit which is an example of timer means; 4 is a substrate potential detection circuit; 5 is a control circuit;
6 is a switch circuit.

Claims (1)

[Scope of Claims] Word line drive signal generation means for supplying a word line drive signal to a word line connected to a memory cell, oscillation means for deriving an output at a predetermined frequency, and a method based on the output from the oscillation means. voltage holding means for holding the output of the word line drive signal generating means higher than the power supply voltage; and generating a substrate bias voltage for holding the potential of the semiconductor substrate constant based on the output from the oscillation means. timer means for outputting a timing signal for self-refresh at regular intervals based on the output from the oscillation means; detecting the output voltage of the substrate bias voltage generation means and applying the voltage to the output voltage; and switching control means for switching and controlling conduction and cutoff from the oscillation means to the substrate bias voltage generation means based on the switching control means.