JPH07296581A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce current consumption in a data hold period by selecting and switching either one side between first, second source voltages in response to a level of a refresh entry signal and supplying it to an internal circuit. CONSTITUTION:In a regular operation period, the refresh entry signal SR supplied from a timing circuit 11 is L level, and a transistor Q1 of a switch circuit 5 is turned on, and the Q3 is turned off, and the circuit 5 selects the source voltage VC to output it. Then, in the data hold period, the signal SR becomes H level, and the Q1 is turned off, and the Q3 is turned on, and the circuit 5 selects the source voltage VD to output it. Thus, the voltage VD lower than the voltage VC in the regular operation period is supplied to the internal circuit 1 as an internal voltage V1 in the data hold period, and power consumption is reduced in self refresh operation in the data hold period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device such as a dynamic random access memory (DRAM) that requires a refresh operation.

[0002]

2. Description of the Related Art In addition to a static (S) RAM which has been conventionally used for a so-called battery backup memory using a built-in battery of a personal computer or the like, a storage capacity is large and a cost per bit and a mounting area are increased due to the development of high integration. DRAMs that can reduce the size are being used. Therefore, there is a demand for a DRAM that is not accessed while holding data, that is, consumes less current during a data holding period.

As is well known, a DRAM is composed of two elements, a charge storage capacitive element and a charge input / output control MOSFET. The stored information is represented by the electric charge accumulated in the capacitive element, and the accumulated electric charge is attenuated with time due to the leak current of the MOSFET, the recombination in the semiconductor substrate, and the like. Therefore, a refresh operation is required to update the information by reading and rewriting the stored information at regular intervals.

For this refresh, a refresh control circuit including a timer is built in, and when the memory is kept in a standby state for a certain time or longer, the refresh operation is automatically performed at regular intervals or in the state of a specific external control signal. A DRAM having a self-refresh function is widely used.

Referring to FIG. 3 which is a block diagram showing a conventional first semiconductor memory device, which is a DRAM having a general self-refresh function, the conventional semiconductor memory device includes a memory cell array, a write / read circuit, and the like. An internal circuit 1 including a circuit and supplied with a power supply voltage VC which is the same as the operating voltage VI and which performs a predetermined memory operation.
, Refresh entry signal SR and counter signal SC
And a counter circuit 3 for outputting a counter signal SC under the control of the refresh entry signal SR.

The internal circuit 1 has a timing circuit 11 for controlling the operation timing of the memory.

FIG. 3 and FIG. 4 showing an operation time chart.
The operation of the first semiconductor memory device in the related art will be described with reference to FIG. 1, and when a specific external control signal such as a row address strobe (RAS) signal holds a constant state for a set time or longer, the timing circuit 11 of the internal circuit 1 Refresh entry signal S for controlling the start of self-refresh operation
R is generated and supplied to the counter 3 and the refresh control circuit 2, respectively. The counter 3 generates a counter signal SC having a cycle T in response to the supply of the signal SR and supplies it to the refresh control circuit 2. In response to the supply of these signals SC and SR, the refresh control circuit 2 generates a refresh control signal RC every cycle T and supplies it to the internal circuit 2. The internal circuit 2 performs a refresh operation every cycle T in response to the supply of the refresh control signal RC.

As described above, in the conventional first semiconductor memory device, the power supply voltage supplied to the internal circuit is constant regardless of the normal operation period and the data holding period. Although almost no current flows in the data holding state of the memory cell, the operating current of the DRAM at the time of reading and writing is almost proportional to the power supply voltage in both the normal operation and the self refresh operation in the data holding period. First
The operating current of the DRAM is almost constant during both the normal operation period and the self-refresh period. The current consumption during the data holding period depends on the operating current, the self refresh cycle, and the duty cycle determined by the read / write operation time during the refresh operation.

Taking a general 16M DRAM as an example, assuming that the operating current is 50 mA during the normal operation, the self-refresh cycle T is 20 μs in the data holding period, and the read / write operation time is 200 ns, the duty corresponding to the refresh operation in the data holding period is set. Since the cycle is 1%, the current consumption at this time is 0.5 mA.

One of the methods for reducing the current consumption in the data holding period is to increase the self refresh period as much as possible in order to reduce the duty cycle. However, if the above cycle is extended without any measures, the detection margin for reading the held data is lowered due to the attenuation of the charge due to the above-described leakage current of the MOSFET and recombination in the semiconductor substrate.

The conventional second semiconductor memory device described in Japanese Patent Laid-Open No. 2-29989, which reduces power consumption by extending the cell fresh cycle while ensuring the above detection margin, has a pair of memory cells. First to apply a first voltage for normal operation to precharge the bit line
Voltage source, a second voltage source for applying a second voltage for refresh operation closer to the ground potential than the first voltage, and the second voltage to the bit line pair in response to a refresh entry signal. And a control circuit for switching to apply, and by supplying the second voltage to the bit line pair in a specific refresh mode, the charge corresponding to the first voltage applied to the memory cell during normal operation is This is to increase the detection margin of read data.

[0012]

In the above-described first conventional semiconductor memory device, since the read / write operation current is the same in the self refresh operation period in the normal operation period and the data retention period, the data retention period is consumed. It has the drawback of a large amount of current.

The second conventional semiconductor memory device is intended to reduce the above current consumption by reducing the duty cycle corresponding to the refresh operation by extending the refresh cycle. There is a drawback that extension of the refresh cycle is limited due to the restriction due to.

An object of the present invention is to solve these drawbacks and to provide a semiconductor memory device which further reduces the current consumption in the data holding period.

[0015]

A semiconductor memory device of the present invention includes an internal circuit having a memory cell array and a peripheral circuit including a write / read circuit for performing a predetermined memory operation, and a refresh entry signal for instructing a refresh operation. A counter circuit which outputs a counter signal in response to the supply of the refresh signal and the refresh entry signal and the counter signal, and the refresh is automatically performed when the memory cell array is kept in a standby state for a predetermined time. In a semiconductor memory device having a self-refresh function that operates, a step-down circuit that steps down a first power supply voltage by a predetermined voltage to generate a second power supply voltage, and a level of the refresh entry signal that has been supplied. In response to selecting one of the first power supply voltage and the second power supply voltage, It is configured to include a switching circuit for supplying the part circuit.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Next, referring to FIG. 1, which is a block diagram in which components common to those of FIG. 3 are designated by common reference characters / numerals, the embodiment of this invention shown in FIG. The semiconductor memory device of FIG. 1 includes an internal circuit 1 including a timing circuit 11 which is the same as the conventional one, a refresh control circuit 2, and a counter circuit 3.
In addition to, the step-down circuit 4 for stepping down the power supply voltage VC to generate the voltage VD, and the voltage VI supplied to the internal circuit 1 in response to the supply of the refresh entry signal SR are the power supply voltage V
And a switching circuit 5 for switching from C to voltage VD.

The step-down circuit 4 includes resistors R1 and R2 for dividing the power supply voltage VC and an operational amplifier A1 connected to a voltage follower, and is a voltage VD = (VC- which is obtained by stepping down the power supply voltage VC by a predetermined drop voltage ΔV. ΔV) is generated. Here, the voltage drop ΔV is given by VC × R1 / (R1 + R2).

The switching circuit 5 is a CMO including P-channel type and N-channel type transistors P1 and N1, respectively.
S-type transfer gate G1 and transistor P2
A transfer gate G2 formed of N2 and an inverter I1 that inverts the refresh entry signal SR to generate an inverted signal ISR are provided. Signal SR is transistor P
The signal ISR is supplied to the gates of the transistors P1 and N2, and the signal ISR is supplied to the gates of the transistors P2 and N1.

Next, the operation of this embodiment will be described with reference to FIG. 1 and FIG. 2 showing an operation time chart.
First, during the normal operation period, the refresh entry signal SR supplied from the timing circuit 11 is at the L level, the transfer gate G1 of the switching circuit 5 is turned on, and the transfer gate G2 is turned off. The power supply voltage VC is selected and output. Therefore, the operating voltage VI supplied to the internal circuit 1 is the power supply voltage VC. Next, in the data holding period, when the refresh entry signal SR becomes H level, the transfer gate G2 becomes conductive and the transfer gate G1 is cut off, so that the switching circuit 5 selects and outputs the voltage VD. Therefore, the operating voltage VI supplied to the internal circuit 1 is the voltage VD.

At the same time, in response to the control of the refresh entry signal SR, the counter circuit 3 and the refresh control circuit 2 operate in the same manner as in the conventional case, generate the refresh control signal RC and supply it to the internal circuit 1, and the internal circuit 1 Refreshes every cycle T.

As described above, in the semiconductor memory device of the present embodiment, the voltage VD lower than the power supply voltage VC in the normal operation period by the voltage drop ΔV is supplied to the internal circuit 1 as the internal voltage VI during the data holding period. Therefore, in the self-refresh operation during the data holding period, the current consumption of the internal circuit 1 is VD / VC = (VC-ΔV) / V as compared with the normal operation period.
It is reduced by the ratio of C.

As an example, the voltage drop ΔV is the power supply voltage VC.
10% of the above, it is possible to reduce the current consumption by about 10%, that is, the power consumption by about 20%, as compared with the case where the same operation voltage as the normal operation period is used during the data holding period.

In the 16M DRAM example similar to the conventional one, the current consumption during the data holding period is reduced to 0.55 mA in the conventional example, to 0.45 mA in this embodiment.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-mentioned embodiments and various modifications can be made. For example, the voltage drop is not limited to 10% and can be set to any value within the range in which the internal circuit 1 can operate. Also,
The configurations of the step-down circuit and the switching circuit are not limited to those shown in the present embodiment, and it goes without saying that any modification that achieves the same function can be performed.

Further, it is needless to say that a configuration for further reducing the current consumption by combining with a refresh period extension technique such as the second conventional technique can be applied without departing from the gist of the present invention. .

[0026]

As described above, the semiconductor memory device of the present invention includes the step-down circuit for stepping down the external power supply voltage to generate the second power supply voltage, and the external power supply voltage in response to the level of the refresh entry signal. By including either of the second power supply voltage and the second power supply voltage and supplying the switching circuit to the internal circuit, the current consumption during the data holding period can be reduced regardless of the restriction by the charge holding characteristic of the memory cell. There is an effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a time chart showing an example of the operation of the semiconductor memory device of this embodiment.

FIG. 3 is a block diagram showing a first conventional semiconductor memory device.

FIG. 4 is a time chart showing an example of operation in the semiconductor memory device of FIG.

[Explanation of symbols]

 1 Internal Circuit 2 Refresh Control Circuit 3 Counter Circuit 4 Step-Down Circuit 5 Switching Circuit 11 Timing Circuit A1 Operational Amplifier G1, G2 Transfer Gate I1 Inverter N1, N2, P1, P2 Transistor

Claims (4)

[Claims] 1. An internal circuit having a memory cell array and a peripheral circuit including a write / read circuit and performing a predetermined storage operation,
A counter circuit that outputs a counter signal in response to the supply of a refresh entry signal for instructing a refresh operation, and a standby state for the memory cell array that is supplied with the refresh entry signal and the counter signal and exceeds a predetermined time In a semiconductor memory device having a self-refresh function that automatically performs the refresh operation when the power is supplied, a step-down circuit that steps down the first power supply voltage by a predetermined voltage to generate a second power supply voltage, and receives a supply. And a switching circuit that selects one of the first power supply voltage and the second power supply voltage and supplies the selected internal power supply voltage to the internal circuit in response to the level of the refresh entry signal. Storage device. 2. The step-down circuit includes first and second resistors, one end of which is connected to the first power supply voltage and is connected in series, and divides the first power supply voltage to correspond to the second power supply voltage. And a voltage follower connection operational amplifier that current-amplifies the second voltage and outputs the second power supply voltage. Semiconductor memory device. 3. An inverter in which the switching circuit inverts the refresh entry signal to generate an inversion signal, and first and second conductive elements, respectively, which are supplied with the refresh entry signal and the inversion signal in their respective gates. CMOS type first transfer gates composed of first and second transistor types, and third gates of the first and second conductivity types respectively supplied with the inversion signal and the refresh entry signal. 2. The semiconductor memory device according to claim 1, further comprising: a second transfer gate including a fourth transistor. 4. The internal circuit generates a timing signal for controlling the operation of the internal circuit and generates the refresh entry signal in response to the continuation of a predetermined level state of a predetermined external control signal for the time period. 2. The semiconductor memory device according to claim 1, further comprising a timing circuit for