JPH02312095A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce power consumption by reducing a voltage supplied to an oscillator in a substrate bias voltage generating circuit in self-refresh mode. CONSTITUTION:In the self-refresh mode, a self-refresh mode detection signal phis is at an H level, a p type MOS transistor (TR) P1 does not supply a source voltage Vcc to a ring oscillator 411A-1, and an n type MOS TR N1 turns off instead. The oscillator 411A-1 is supplied with a voltage which is the threshold value of the TR N1 lower. When voltages applied to respective inverters I1 - IN drop, a delay time becomes longer and the oscillation period of the oscilla tor 411A-1 becomes long. Consequently, the number of times of charge pump operation per unit time of a substrate voltage generating circuit 41 decreases and the power consumption is reducible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic semiconductor memory device with a built-in refresh function, and particularly to a structure for further reducing power consumption thereof.

[Conventional technology]

In recent years, personal computers have become extremely popular and are used in various fields. Among such personal computers, demand for portable personal computers has particularly increased recently. The storage devices used in these portable personal computers are required to have low power consumption and are capable of battery retention (battery backup).
A dynamic semiconductor memory device (DRAM) or a static semiconductor memory Wt (SRAM) is used.

Among these, DRAM utilizes the principle of storing information charges in a MOS capacitor (a capacitor that uses a metal layer as one electrode, a semiconductor region as the other electrode, and an insulating film between them as a dielectric). However, in such a MOS capacitor, the stored charge is gradually lost due to leakage at one junction formed between the semiconductor region that is the other electrode and the semiconductor substrate, so the stored information is not stored at regular intervals. Needs to be rewritten. Such a rewrite operation is called a refresh operation. When a DRAM is used as a storage device in a portable personal computer, it is necessary to refresh the memory at regular intervals even during battery backup.

Typical refresh modes for DRAM include πN3 only refresh and m-before-m refresh. π
The W3-only refresh is a refresh mode in which a refresh row address (refresh address) is externally applied, and the row address strobe signal τ1 is lowered to put the DRAM in a selected state. In this 7X million refresh, column address strobe signal m is at the "H" level.

The τW3 before Wτ3 refresh mode is a mode in which the signal CX3 is first set to L level before the signal πK is set to the L level, and a refresh instruction signal is given, and refresh is automatically performed according to the state of this signal. In these normal refresh modes, the signal π”
Refreshing is executed cycle by cycle by external clock signals such as 8, 117 and 3. Therefore, it is not preferable to use such a normal refresh mode during battery backup because it requires complicated control.

Therefore, in order to easily refresh the battery even during battery backup, for example, Yamada et al.
The paper “Auto/5el” published on pages 69 to 69
f 64Kbit MOS with built-in refresh function
As explained in "Dynamic RAM," DRAM has a built-in address counter that generates refresh addresses and a timer circuit that provides refresh timing for each row, and has a self-refresh mode that automatically performs refresh operations. It has been devised and put into practical use.

Although this self-refresh operation is explained in detail in the above-mentioned literature, it will be briefly explained below with reference to the drawings.

Figure 3 shows a conventional 64 with self-refresh mode.
FIG. 2 is a block diagram showing an example of the configuration of a DRAM. In the configuration of FIG. 3, only the portions related to the refresh operation are shown.

In Figure 3, the DRAM has 256 (=2”) rows,
A memory array 97 comprising 256 (=2”) columns of memory cells arranged in a matrix, and an address switching circuit 95.
An address buffer 96 receives an address signal from the memory array 96, temporarily holds it, and generates an internal address signal, and the address buffer 96 selects a corresponding row from the memory array 97 in response to the internal row address signal. 9 row decoders.

A 7-bit internal address signal RAO-RA6 from address buffer 96 is applied to row decoder 98. Although not shown in the figure, memory array 97 has 128 rows and 25 rows, respectively.
It is divided into two blocks of 6 columns, and one word line, ie, two word lines, from each block is simultaneously selected by 7-bit lower address signals RAO-RAS. Most significant address signal R from address buffer 96
A7 is used as an address signal for block selection.

The address switching circuit 95 receives externally applied row address signals AO to A7 and refresh addresses QO to Q6 generated from the refresh address counter 94, and selects one of them as an address under the control of the refresh control circuit 92. It is transmitted to buffer 96. Address signals AO to A7 applied from the outside are provided by time-division multiplexing of a row address signal and a column address signal.

In order to specify the self-refresh operation, the DRAM also includes a self-refresh mode detection circuit 91 that receives a signal Tπ-d applied through the input terminal 1 and detects whether or not the self-refresh mode is instructed; It also includes a refresh control circuit 92 that generates signals for controlling the operations of an address switching circuit 95, a refresh address counter 94, and a timer 93 in response to a self-refresh mode detection signal φ from a refresh mode detection circuit 91.

Address switching circuit 95 selects refresh addresses QO to Q6 from refresh address counter 94 in response to a refresh instruction signal from refresh control circuit 92.
is given to the address buffer 96.

Timer 93 outputs refresh request signal φe at predetermined intervals in response to refresh instruction signal φa from refresh control circuit 92.

Refresh address counter 94 has its count value incremented in response to refresh request signal φ7 from timer 93, and provides refresh addresses QO-Q6 corresponding to the count value to address switching circuit 95.

Next, its operation will be briefly explained. The self-refresh mode is activated by keeping the signal πτ applied to the input terminal 2 at the "H11 level" (standby state) and lowering the external refresh signal πT applied to the input terminal 1 to the "L" level. Detection circuit 911 detects that refresh is instructed, and outputs refresh instruction signal φ.

In response to this refresh instruction signal φ3, address switching circuit 95 transfers refresh addresses QO to Q6 from refresh address counter 94 to address buffer 9.
Give to 6. The address buffer 96 generates internal refresh addresses RAO-RA6 from the applied refresh addresses QO-Q6, and supplies them to the row decoder 98. The 0-row decoder 98 decodes this 7-bit refresh address QO-Q6 (RAO-RAS). Then, one row out of 128 rows in each block of memory array 97 is selected. Subsequently, a circuit (not shown) refreshes the data in the memory cells connected to the selected row.

Next, this external refresh signal π′F! : If the signal continues to be held at the "L" level for a predetermined set time (maximum 16 μs) or more, the self-refresh mode detection circuit 91 detects the designation of the self-refresh mode. In response to the detection of this self-refresh mode designation, refresh control circuit 92 raises signal φ7 and starts timer 93. In response to this activation signal φ1, the timer outputs a refresh request signal φ1 and applies it to the refresh control circuit 92 when a predetermined set time (maximum 16 μs) has elapsed. Refresh control circuit 92 increments the count value of refresh address counter 94 in response to this refresh request signal φ. In response, refresh address counter 94 provides address switching circuit 95 with a refresh address QO-Q6 that is different from the refresh address output in the previous refresh cycle.

Similarly to the previous refresh operation, one row corresponding to this refresh address QO-Q6 is selected in memory cell 97, and data in the selected memory cell is refreshed in this selected one row. The refresh request signal φ from the timer 93 is repeatedly generated at a predetermined period as long as the external refresh signal π is at the "L" level and the signal m is at the "H" level. Therefore, 128 word lines in each block in the memory array 97 are sequentially selected in this self-refresh mode, and the data of the memory cells connected to the selected word lines are refreshed. case,
Memory array 9 every 16 μs × 128 to about 2 m s
All 7 memory cells will be refreshed.

Therefore, if the DRAM is set in the self-refresh mode in advance, refresh will be automatically performed as described above even during battery backup when the main power is turned off.

Normally, in the RAM as described above, this DRAM
A substrate bias voltage generation circuit is provided to reduce parasitic capacitance between the circuit elements constituting the DRAM and the semiconductor substrate on which the DRAM is formed, and to ensure high-speed and stable operation of the DRAM. ! In general, in DRAM, reduction of the junction capacitance between the semiconductor substrate and the impurity region, stabilization of the threshold voltage of the MOS transistor formed on the surface of the semiconductor substrate, signal wiring layer on the field insulating film, etc. When the semiconductor substrate is of P type, the semiconductor substrate is biased to a negative potential ■□ for the purpose of suppressing the generation of a parasitic MOS transistor consisting of an impurity region formed on the surface of the semiconductor substrate. .

Figure 4 shows a conventional DR with self-refresh mode.
FIG. 3 is a diagram showing an example of an AM substrate bias voltage generation circuit. In FIG. 4, the substrate bias voltage generation circuit 41 includes a ring oscillator 411 that outputs an oscillation signal φCP of a predetermined frequency, a charge pump capacitor C that receives the oscillation signal from the ring oscillator 411, and a node N8 and a ground potential. an n-channel MO provided between the two and clamping the potential of node N3 to its threshold voltage level Vt+;
S) An n-channel MOS transistor Q2 provided between the transistor Q1, the node N, and the output terminal 412, and clamping the node Nl to a potential determined by the difference between its threshold voltage v0 and the semiconductor substrate potential. It has the following.

FIG. 5 is a signal waveform diagram for explaining the operation of the substrate bias voltage generation circuit shown in FIG. 4. Hereinafter, the operation of the substrate bias voltage generation circuit will be briefly explained with reference to FIGS. 4 and 5.

Oscillation signal φeP from ring oscillator 411 is “H”
When the level rises, the potential of node N becomes capacitor C.
Due to the capacitive coupling, the power supply potential VCC level attempts to rise to the "H" level. At this time, in response to the rise in the potential of the node N, the MOS transistor Ql becomes conductive, and the potential of the node N becomes the MOS transistor Ql.
is clamped to the threshold voltage level vy+. on the other hand,
MOS transistor Q2 is in a non-conductive state.

Next, when the oscillation signal φCF falls to the "L" level, the potential of the node N also decreases due to the capacitive coupling of the capacitor C. In response to the potential drop of this node N, M
OS) transistor Q1 is turned off, MOS) transistor Q2 is turned on, and positive charges flow from the semiconductor substrate to node N. The potential of this node Ns is the semiconductor substrate potential ■. When the value becomes equal to the difference between the threshold voltage vyz of the transistor Q2 and the MOS transistor Q2, the MOS transistor Q2 becomes non-conductive and the movement of charge stops. 4
This one oscillation signal φ6. Due to the rise and fall of
The potential of the semiconductor substrate decreases a little; as such cycles continue several times, the voltage of the semiconductor substrate gradually decreases to a predetermined negative potential. Now, set the operating power supply voltage to V
CC, the bias voltage V□ of this semiconductor substrate is ideally Va, +V7□-vcc, and usually -3
The value is about V.

FIG. 6 is a diagram showing an example of the ring oscillator 411 in the substrate bias generation circuit 41 of FIG. 4. In FIG. 6, a ring oscillator 411 is composed of odd-numbered stages of inverters 11 to IN, and outputs an oscillation signal φC2 by inputting the output of the final stage inverter IN to the first stage inverter 1. Inverters 11-IN in this circuit are directly supplied with a power supply voltage and operate exactly the same in both normal mode and self-refresh mode, so that an oscillation signal φC2 having a constant period is always output.

FIG. 7 is a diagram showing an example of the configuration of timer 93 shown in FIG. 3. In FIG. 93-1, a buffer circuit 93-2 that performs waveform shaping of the oscillation signal from the ring oscillator 93-1, and a pulse signal from the buffer circuit 93-2, and outputs a refresh request signal φ1 at every predetermined count value. and a counter circuit 93-3 for output.

The ring oscillator 93-1 includes six stages of cascade-connected inverters INI to INS, and a NAND gate N that receives the output of the inverter IN6 at one input and receives the activation signal φ7 from the refresh control circuit 92 at the other input.
1. The NAND gate N1 output is given to the buffer circuit 93-2, and the first stage inverter I
It is fed back to the input section of NI.

Buffer circuit 93-2 includes four stages of cascade-connected inverters IN7 to IN10. This buffer circuit 93-2
The roundness of the waveform of the oscillation signal output from the ring oscillator 93-1 is corrected, the oscillation signal φ□ is output from the inverter lNl0, and the output of the inverter rN10 is inverted by the inverter INII to output an inverted output signal T1. These mutually complementary oscillation signals φrlTT are sent to the counter circuit 93.
−3 is given. Counter circuit 93-3 includes four stages of binary counters BCI to BC4 connected in cascade. Each of the binary counters BCI to BC4 divides the frequency of the signal applied to its input portions I and T into half the frequency and outputs the divided frequency.

Next, the operation will be explained. First, when the activation signal φ7 from the ring oscillator control circuit 92 is at the 'L' level and the self-refresh mode is not specified, the NAND gate N1 is at a certain 'H' level.
Ring oscillator 93-1 does not perform oscillation operation.

Next, the signal φ3 becomes “H” level for a predetermined time or longer, self-refresh mode is detected, and the activation signal φ7 becomes “H” level.
When the voltage level rises, the NAND gate (Nl) operates as an inverter. Therefore, the inverters INI to IN6 and the NAND gate N1 become equivalent to seven stages of inverters, and the ring oscillator 93-1 starts oscillating. The oscillation signal from ring oscillator 93-1 is applied to buffer circuit 93-2, where the waveform is shaped.

These waveform-shaped oscillation signals φ, which are complementary to each other.

T7 is applied to counter circuit 93-3.

In other words, the binary counter BCI receives the oscillation signal φ
, is applied twice, an output signal O1 that rises to the "H" level is derived. Therefore, when the signal φ7 has a period of 1 μs, the output O1 of the binary counter BCI has a duty of 50
A signal with a period of 2 μs is output. Similarly, 2
An output signal 02 with a duty cycle of 4 μs is derived from the binary counter BC2, and an output signal o3 of the duty cycle 50 with a cycle of 8 μs is derived from the binary counter BC3.

As a result, the binary counter BC4 outputs the refresh request signal φS with a duty of 50. A signal with a period of 16 μs is output. When this refresh request signal φ becomes H'' level, a refresh operation is performed.

Note that a reset signal RESET is applied to each of the binary counters BC1 to BC4, so that the count output can be reset to a predetermined value as necessary.

[Problem to be solved by the invention]

A conventional dynamic semiconductor memory device with built-in refresh is configured as described above, and the oscillator in the substrate bias voltage generation circuit oscillates a signal at the same period in both the normal mode and the internal refresh mode. Therefore, in either mode, the number of charge bombings per unit time remains the same, and the power consumption by the substrate bias circuit remains the same.

However, in internal refresh mode,
Since operations other than the refresh operation, such as data writing/reading and column selection operations, are not performed, the substrate leakage current flowing into the semiconductor substrate is smaller than in normal mode, and the amount of leakage can be predicted. It is something. Therefore, although it is necessary to reduce power consumption as much as possible, especially in internal refresh mode during battery backup, the substrate bias voltage generation circuit consumes the same amount of power as in normal operation mode, so unnecessary power consumption is avoided. There was a problem that it was causing.

In addition, while normal memory cells have a refresh time of 1 second or more at room temperature, the standard refresh time in internal refresh mode is set to a considerably short time (for example, 4MDRAM has a refresh time of 16m5).
), this causes the problem that the number of refresh cycles per unit time becomes unnecessarily large, and that an excessive amount of power is consumed even in an internal refresh mode in which power consumption needs to be reduced.

This invention was made to solve the above-mentioned problems. ■ The first object of the invention is to reduce the amount of power consumed by the substrate bias voltage generation circuit during internal refresh mode. It is an object of the present invention to provide a dynamic semiconductor memory device with a built-in refresh function, which is capable of reducing the amount of power consumed by a refresh operation in an internal refresh mode. The purpose is to provide equipment.

[Means to solve the problem]

A semiconductor memory device according to the present invention is a semiconductor memory device having a function of automatically refreshing memory cell data in response to an external refresh instruction signal; means for generating an internal refresh instruction signal, means for refreshing the memory cell data, and a signal that is periodically generated at predetermined intervals while the internal refresh instruction signal is in an active state and activates the refresh means. means for biasing the semiconductor substrate to a predetermined potential by charge bombing using an oscillator whose oscillation period can be adjusted by supply voltage or supply current; supply voltage or supply to the oscillator during the internal refresh; Means for reducing current is provided on the same semiconductor substrate.

Further, a semiconductor memory device according to a second invention is a semiconductor memory device having a function of automatically refreshing memory cell data in response to an external refresh instruction signal, wherein the semiconductor memory device has a function of automatically refreshing memory cell data in response to an external refresh instruction signal. The internal refresh instruction signal is in an active state using means for generating an internal refresh instruction signal in response to the internal refresh instruction signal, means for refreshing the memory cell data, and an oscillator whose oscillation period can be adjusted by a supply voltage or a supply current. Means for generating a signal for activating the refresh means at regular intervals, and means for reducing the voltage or current supplied to the oscillator are provided on the same semiconductor substrate.

[Effect]

In the semiconductor memory device according to the first aspect of the invention, the means for reducing the supply voltage or supply current to the charge pump oscillator within the substrate bias during internal refreshing reduces the period of the pulse signal generated by the oscillator during internal refreshing. This reduces the unnecessary number of charge bombing operations and reduces power consumption by the substrate bias generation circuit during internal refresh.

Furthermore, in the semiconductor memory device according to the second aspect of the invention, the means for reducing the supply voltage or supply current to the oscillator in the internal refresh activation signal generating means reduces the period of the signal generated by the oscillator during internal refresh. This reduces the number of refresh operations more than necessary during internal refresh, and reduces power consumption due to refresh operations during internal refresh.

〔Example〕

In particular, a device including a ring oscillator as a charge pump oscillator and capable of stepping down the voltage supplied to the ring oscillator in the self-refresh mode is connected to several stages of inverters 11 to I.
A ring oscillator 411A-1 composed of N, and an n-type MO that supplies a voltage obtained by stepping down the power supply voltage Vcc to the ring oscillator 411A-1 in the self-refresh mode.
S transistor N1 and power supply voltage vcc in normal mode
p-type MOS that supplies ring oscillator 411A-1 with
) Inverters IWI and pW! for making the amplitude of the oscillation signal output from the transistor P1 and the ring oscillator 411A-1 equal to the power supply voltage Vcc! ! MO3) transistor P2.

Next, the operation of this circuit will be explained. In the normal mode, the self-refresh mode detection signal φ3 is at L level, and at this time, the p-type MO3) transistor P1, which receives this signal φS at its gate electrode, is turned on. On the other hand n
Type MO3) transistor N1 is turned off. Therefore, the power supply voltage vce applied to the source electrode of the transistor P1 is supplied to the ring oscillator 411A-1.

On the other hand, in the self-refresh mode, the self-refresh mode detection signal φ is at H level, and the p-type M
O3) The transistor P1 no longer supplies the power supply voltage vcc to the ring oscillator 411A-1, and instead supplies the n-type MO
3) The transistor N1 is turned off. Therefore, the ring oscillator 411A-1 is an n-type MO3) transistor N1.
The voltage will be supplied by This transistor N1 has a power supply voltage VeC at its gate bridge and source electrode.
The ring oscillator 411A-1 is supplied with a voltage VccV(N1) which is lower by the threshold value V(N1) of the transistor N1.

The oscillation period of the ring oscillator 411A-1 is determined by the delay time of each inverter 11 to IN, and when the voltage supplied to each inverter 11 to IN decreases, the time required to charge and discharge the input and output of each inverter If-IN decreases. become longer. For this reason, the delay time of each inverter 11 to IN becomes large, and as a result, the oscillation cycle of ring oscillator 411A-1 becomes long. And this ring oscillator 41
The signal output from 1A-1 is changed in amplitude to the power supply voltage by inverter IWI and p-type MO3) transistor P2. It is raised to.

Therefore, in the self-refresh mode, the oscillation cycle of the charge pump oscillation signal φCP output by the pulse generation circuit 411A is longer than in the normal mode. Therefore, the number of charge pump operations per unit time in the substrate voltage generation circuit 41 (FIG. 4) is reduced, and the power consumed by the charge pump operation is reduced.

As described above, the power consumed by the substrate bias voltage generation circuit 41 in the self-refresh mode is reduced compared to the normal mode. Therefore, DRAM with a built-in refresh function suitable for battery backup can be used for
can be provided.

In the above explanation, it was stated that the oscillation period of the charge pump pulse generation circuit could be adjusted only by the threshold value Vtb (Nl) of the n-type MO3) transistor N1.
It goes without saying that the oscillation period can also be adjusted by changing the ratio to the conductance of the p-type MOS transistor in IN. For example, if the conductance of the transistor N1 is small, the current supplied to the ring oscillator 411A-1 will be small, and the time required for charging and discharging at the input and output of each inverter 11 to IN will become longer, and the delay caused by each inverter will become longer. 411A-
The period of the oscillation signal from 1 becomes longer.

The oscillation period from ring oscillator 411A-1 can also be lengthened by using an external power source (for example, a battery) that provides a lower voltage.

In addition, since the supply voltage is lower than vcc, the output waveform of the ring oscillator 411A-1 is rounded, and the 411A-
Inverter IAI, IA2 between 1 and inverter IWI
By inserting the ring oscillator 411A-1
It includes a ring oscillator as a timer oscillator that shapes the output waveform of the inverter IWI and reliably reduces the through current caused by the inverter IWI, and an even number of stages of inverters INI to INN that step down the voltage supplied to the ring oscillator, and the output of the inverter INH. and refresh instruction signal φ7) NAI, and these inverters INI
~INN and NAND game) n-type M that steps down the supply voltage to the ring oscillator 93A-11 composed of NAI
O3) Transistor N1 and ring oscillator 93A-1
Inverter IWI and p-type MOS) transistor P2 to make the amplitude of the oscillation signal output from the power supply voltage ■cc
It is composed of

The operation of this circuit will be explained below. The n-type MOS transistor Nil has its gate electrode and source electrode connected to the power supply voltage V.
(c, and the voltage V is lower than the power supply voltage V, C by the threshold value Vth (N 41 ) of the transistor Nil
cc Vth (N 11 ) is supplied to the timer ring oscillator 93A-11. In normal mode, refresh instruction signal φa is at L level, and NAN
The output signal of the D gate NA1 remains at a constant H level, and the ring oscillator 93A-11 does not perform oscillation. On the other hand, in the self-refresh mode, the refresh instruction signal φd is at an H level, and at this time the N
AND gate NAI operates as an inverter.

Therefore, the ring oscillator 93A-11 is connected to the inverter I.
Together with NI to INN, it includes an odd number of stages of inverters and performs oscillation operation, and then the ring oscillator 93
The signal output from A-11 is connected to inverter IWI and p
Type MO3) Its amplitude depends on the pH of the transistor and the power supply voltage V.
The pulse signal φ raised to CC is output.

The oscillation period of the ring oscillator 93A-11 depends on the delay time of each inverter INI-INN and NAND gate NA1.
Since the voltage supplied to the ND gate NAI is set to a voltage ■, c-vth (Nil) lower than the power supply voltage vee,
The time required to charge and discharge the input and output of each inverter (1)-IN and NAND gate NA1 becomes longer. Therefore, the period of the oscillation signal output by the ring oscillator 93A-11 becomes longer than when using the same number of stages of ring oscillators in the conventional circuit (FIG. 6).

In addition, in order to lengthen the period of the ring oscillator using the conventional technique, it is only necessary to increase the number of stages of the ring oscillator or increase the number of each transistor type MO3) transistor Nil used in the ring oscillator. It is possible to generate long-period pulses by reducing the area occupied by the pulse generating circuit 93A-1.

In this way, the period of the ring oscillator 93A-11 can be adjusted by Vtk (Nil) of the transistor Nil,
For example, it is possible to double the period of a ring oscillator with the same number of stages in a conventional circuit. As a result, the final timer signal φ also has a double period, and the number of refresh operations per unit time is halved.

As a result, power consumption due to self-refreshing will be halved.

Therefore, the power consumed by the ring oscillator 93-1- of the conventional circuit is reduced, and a DRAM with a built-in refresh function suitable for battery backup can be provided.

In the above description, the period of the timer pulse generation circuit 93A-1 is determined by the threshold voltage V(N) of the n-type MO3) transistor N1.
Although the explanation has been made on the assumption that the adjustment can be made only by 1), it goes without saying that adjustment can also be made by changing the conductance ratio of each MO3) transistor in the ring oscillator 93A-11. For example, if the conductance of the transistor Nil is small, the current supplied to the ring oscillator 93A-11 becomes small, and each inverter INI to INN
The time required to charge and discharge the input and output of the NAND gate NAI becomes longer, and the delay caused by each inverter becomes longer.
The oscillation cycle from ring oscillator 93A-11 becomes longer.

An external power supply may be used as shown in A, and this also allows the oscillation period of the ring oscillator 93A-11 to be changed to 93A-11.
By inserting the inverters IAI and IA2 between the ring oscillator 93A-11 and the inverter IWI, it is possible to shape the output waveform from the ring oscillator 93A-11 and reliably reduce the through current caused by the inverter IWI.

〔Effect of the invention〕

■ As described above, according to the first invention, the number of charge bombings per unit time can be reduced by reducing the supply voltage or supply current to the oscillator in the substrate bias voltage generation circuit during the built-in refresh mode. As a result, the power consumed within the substrate bias voltage generation circuit in the internal refresh mode is reduced, and a dynamic semiconductor memory device with a built-in refresh function that consumes low power can be obtained.

■ Also, according to the second invention, by reducing the voltage or current supplied to the oscillator of the internal refresh activation signal generating means, the number of refresh operations per unit time in the internal refresh mode can be reduced. As a result, it is possible to reduce the power consumption due to the refresh operation in the internal refresh mode, and it is possible to obtain a dynamic semiconductor memory device with a built-in refresh function that consumes low power.

7 is a diagram showing a circuit that corresponds to the ring oscillator 93-1 in the self-refresh timer 93 shown in FIG. 7, which charges the ring oscillator 411 in the substrate bias voltage generation circuit 41 shown in FIG. 4. .

FIG. 3 is a diagram schematically showing the configuration of the main parts of a conventional semiconductor memory device.

FIG. 4 is a diagram showing an example of the configuration of the substrate bias voltage generation circuit used in FIG. 3.

FIG. 5 is a signal waveform diagram showing the operation of the substrate bias voltage generation circuit shown in FIG. 4.

FIG. 6 shows the conventional substrate bias voltage generation circuit 41 of FIG.
4 is a diagram illustrating a configuration example of a ring oscillator 411 in FIG.

FIG. 7 is a signal waveform diagram showing the operation of the timer 93 shown in FIG. 3 on the component side.

In the figure, 91 is a self-refresh mode detection circuit, 92 is a refresh control circuit, 93 is a refresh request signal generation timer, 94 is a refresh address counter, 95 is an address switching circuit, 96 is an address buffer, 97 is a memory array, and 98 is a Row decoder, 411A
is a pulse generation circuit, 411A-1 is a ring oscillator,
93A-1 is a pulse generation circuit, and 93A-11 is a ring oscillator.

Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) A semiconductor memory device having a function of automatically refreshing memory cell data in response to an external refresh instruction signal, which generates an internal refresh instruction signal in response to the external refresh instruction signal. means for refreshing the memory cell data in response to the internal refresh instruction signal; and means for refreshing the memory cell data in response to the internal refresh instruction signal; means for generating an activation signal; means for biasing the semiconductor substrate to a predetermined potential by charge pumping using an oscillator whose oscillation period can be adjusted by supply voltage or supply current; 1. A semiconductor memory device comprising: means for reducing a supply voltage or a supply current, each of said means being formed on the same semiconductor substrate. (2) A semiconductor memory device having a function of automatically refreshing memory cell data in response to an external refresh instruction signal, which generates an internal refresh instruction signal in response to the external refresh instruction signal. means for refreshing the memory cell data in response to the internal refresh instruction signal; and an oscillator whose oscillation period can be adjusted by a supply voltage or current, the internal refresh instruction signal is in an active state. means for generating a signal for activating the refresher means at regular intervals during the period of time, and means for reducing the supply voltage or supply current to the oscillator, each of the means being formed on the same semiconductor substrate. A semiconductor memory device characterized by: