JPS63147845U - - Google Patents
Info
- Publication number
- JPS63147845U JPS63147845U JP4021487U JP4021487U JPS63147845U JP S63147845 U JPS63147845 U JP S63147845U JP 4021487 U JP4021487 U JP 4021487U JP 4021487 U JP4021487 U JP 4021487U JP S63147845 U JPS63147845 U JP S63147845U
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- buried layer
- type formed
- epitaxial layer
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000002955 isolation Methods 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000009795 derivation Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Description
第1図及び第2図は夫々本考案を説明するため
の平面図及びAA線断面図、第3図及び第4図は
従来例を説明するための平面図及びBB線断面図
である。
21は半導体基板、26はコレクタ埋込層、2
7はエミツタ領域、28はコレクタ導出領域、3
2はエミツタ電極である。
1 and 2 are a plan view and a sectional view taken along the line AA, respectively, for explaining the present invention, and FIGS. 3 and 4 are a plan view and a sectional view taken along the line BB, respectively, for explaining a conventional example. 21 is a semiconductor substrate, 26 is a collector buried layer, 2
7 is an emitter region, 28 is a collector derivation region, 3
2 is an emitter electrode.
Claims (1)
エピタキシヤル層と、前記基板表面に埋込んで形
成した逆導電型の埋込層と、この埋込層に重畳し
て前記基板表面から上方向へ形成した一導電型の
コレクタ埋込層と、前記埋込層を取囲むように前
記エピタキシヤル層を貫通した一導電型の分離領
域と、前記コレクタ埋込層に対応する前記エピタ
キシヤル層の表面に形成した逆導電型のベースコ
ンタクト領域と、該ベースコンタクト領域を取り
囲むようにしてリング状に形成した一導電型のエ
ミツタ領域と、このエミツタ領域を囲むようにし
て前記エピタキシヤル層表面から前記コレクタ埋
込層まで達する一導電型のコレクタ導出領域とを
具備することを特徴とする縦型PNPトランジス
タ。 an epitaxial layer of an opposite conductivity type formed on a semiconductor substrate of one conductivity type; a buried layer of an opposite conductivity type formed embedded in the surface of the substrate; a collector buried layer of one conductivity type formed in a direction, an isolation region of one conductivity type penetrating the epitaxial layer so as to surround the buried layer, and the epitaxial layer corresponding to the collector buried layer; a base contact region of opposite conductivity type formed on the surface of the epitaxial layer; an emitter region of one conductivity type formed in a ring shape surrounding the base contact region; A vertical PNP transistor comprising a collector lead-out region of one conductivity type that reaches a buried layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4021487U JPS63147845U (en) | 1987-03-19 | 1987-03-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4021487U JPS63147845U (en) | 1987-03-19 | 1987-03-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63147845U true JPS63147845U (en) | 1988-09-29 |
Family
ID=30854102
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4021487U Pending JPS63147845U (en) | 1987-03-19 | 1987-03-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63147845U (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5544701A (en) * | 1978-09-25 | 1980-03-29 | Hitachi Ltd | Manufacturing transistor |
JPS5619663A (en) * | 1979-07-25 | 1981-02-24 | Nec Home Electronics Ltd | Semiconductor device |
-
1987
- 1987-03-19 JP JP4021487U patent/JPS63147845U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5544701A (en) * | 1978-09-25 | 1980-03-29 | Hitachi Ltd | Manufacturing transistor |
JPS5619663A (en) * | 1979-07-25 | 1981-02-24 | Nec Home Electronics Ltd | Semiconductor device |
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