JPS63147739U - - Google Patents
Info
- Publication number
- JPS63147739U JPS63147739U JP3777387U JP3777387U JPS63147739U JP S63147739 U JPS63147739 U JP S63147739U JP 3777387 U JP3777387 U JP 3777387U JP 3777387 U JP3777387 U JP 3777387U JP S63147739 U JPS63147739 U JP S63147739U
- Authority
- JP
- Japan
- Prior art keywords
- digital signal
- under test
- circuit under
- output
- analog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Measurement Of Resistance Or Impedance (AREA)
- Tests Of Electronic Circuits (AREA)
Description
第１図は本考案の一実施例構成図、第２図は本
考案の他の実施例構成図である。
図中、１，１ａ，１ｂはアナログ―デイジタル
変換器、２は出力端子、３は被試験回路、４は入
力端子、５はデイジタル信号解析器、６はデータ
処理部、７はパネル、８は制御部、９はデイスプ
レイ、１０はクロツク発生器である。
FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of another embodiment of the present invention. In the figure, 1, 1a, 1b are analog-digital converters, 2 is an output terminal, 3 is a circuit under test, 4 is an input terminal, 5 is a digital signal analyzer, 6 is a data processing section, 7 is a panel, and 8 is a 9 is a display, and 10 is a clock generator.
Claims (1)
変換するアナログ―デイジタル変換器１と、 該アナログ―デイジタル変換器１からのデイジ
タル信号を出力する出力端子２と、 該出力端子２から出力されたデイジタル信号を
被試験回路３が受領し、該被試験回路３より出力
されるデイジタル信号を受領する入力端子４と、 該入力端子４より受領した被試験回路３からの
デイジタル信号と、該アナログ―デイジタル変換
器１からのデイジタル信号とを受領し、これらの
各信号について、解析を施すデイジタル信号解析
器５と、 該デイジタル信号解析器５より出力されるこれ
らの解析データに基づいて、被試験回路３につい
ての所望のデータ処理を行うデータ処理部６ とを備え、被試験回路３の入出力特性を評価する
ことを特徴とする信号比較装置。[Claims for Utility Model Registration] An analog-digital converter 1 that receives an analog input signal and converts it into a digital signal, an output terminal 2 that outputs the digital signal from the analog-digital converter 1, and the output terminal A circuit under test 3 receives the digital signal output from the circuit under test 2, and an input terminal 4 receives the digital signal output from the circuit under test 3, and a digital signal from the circuit under test 3 received from the input terminal 4. and a digital signal analyzer 5 that receives and analyzes the digital signals from the analog-to-digital converter 1, and analyzes each of these signals based on the analysis data output from the digital signal analyzer 5. and a data processing section 6 for performing desired data processing on the circuit under test 3, and for evaluating input/output characteristics of the circuit under test 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3777387U JPS63147739U (en) | 1987-03-14 | 1987-03-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3777387U JPS63147739U (en) | 1987-03-14 | 1987-03-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63147739U true JPS63147739U (en) | 1988-09-29 |
Family
ID=30849400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3777387U Pending JPS63147739U (en) | 1987-03-14 | 1987-03-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63147739U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5056836A (en) * | 1973-09-17 | 1975-05-17 |
-
1987
- 1987-03-14 JP JP3777387U patent/JPS63147739U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5056836A (en) * | 1973-09-17 | 1975-05-17 |
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