JPS63146477U - - Google Patents
Info
- Publication number
- JPS63146477U JPS63146477U JP3886387U JP3886387U JPS63146477U JP S63146477 U JPS63146477 U JP S63146477U JP 3886387 U JP3886387 U JP 3886387U JP 3886387 U JP3886387 U JP 3886387U JP S63146477 U JPS63146477 U JP S63146477U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- gate
- fet switch
- gate bias
- secondary winding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004804 winding Methods 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Dc-Dc Converters (AREA)
Description
図は本考案の一実施例に係るスイツチング電源
とその短絡保護回路との回路図である。
１……コンバータトランス、５……コンバータ
トランスの二次側巻線、９……ＦＥＴスイツチ、
１０ａ，１０ｂ……出力端子、１４……ゲートバ
イアス抵抗、１５……サイリスタ。
The figure is a circuit diagram of a switching power supply and its short-circuit protection circuit according to an embodiment of the present invention. 1...Converter transformer, 5...Secondary winding of converter transformer, 9...FET switch,
10a, 10b...output terminal, 14...gate bias resistor, 15...thyristor.
Claims (1)
スの二次側巻線の一方の端部と一方の出力端子と
の間の第１電源ラインにソース・ドレインを接続
された電界効果トランジスタＦＥＴスイツチと、
前記ＦＥＴスイツチのゲートにゲートバイアス電
圧を印加する手段とを具備してなるスイツチング
電源に備えられ、 前記二次側巻線の他方の端部と他方の出力端子
との間の第２電源ラインに挿入されたゲートバイ
アス抵抗と、前記ＦＥＴスイツチのゲートと前記
二次側巻線の他方の端部との間にアノード・カソ
ードを接続されるとともに、カソード・ゲートを
前記ゲートバイアス抵抗に並列に接続されたサイ
リスタとを含み、第２電源ラインに流れる過電流
に従つて前記ゲートバイアス抵抗の両端間に発生
する電圧により前記サイリスタをオンにして前記
ＦＥＴスイツチをオフにすることを特徴とするス
イツチング電源の短絡保護回路。[Claims for Utility Model Registration] A converter transformer, and a field effect transistor whose source and drain are connected to a first power supply line between one end of the secondary winding of the converter transformer and one output terminal. FET switch and
a switching power supply comprising means for applying a gate bias voltage to the gate of the FET switch, and a second power supply line between the other end of the secondary winding and the other output terminal. An anode/cathode is connected between the inserted gate bias resistor, the gate of the FET switch, and the other end of the secondary winding, and the cathode gate is connected in parallel to the gate bias resistor. thyristor, the switching power supply is characterized in that the thyristor is turned on and the FET switch is turned off by a voltage generated across the gate bias resistor according to an overcurrent flowing in a second power supply line. short circuit protection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3886387U JPS63146477U (en) | 1987-03-16 | 1987-03-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3886387U JPS63146477U (en) | 1987-03-16 | 1987-03-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63146477U true JPS63146477U (en) | 1988-09-27 |
Family
ID=30851509
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3886387U Pending JPS63146477U (en) | 1987-03-16 | 1987-03-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63146477U (en) |
-
1987
- 1987-03-16 JP JP3886387U patent/JPS63146477U/ja active Pending
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