JPS63146439A - Forming method for electrode of semiconductor device - Google Patents
Forming method for electrode of semiconductor deviceInfo
- Publication number
- JPS63146439A JPS63146439A JP29253386A JP29253386A JPS63146439A JP S63146439 A JPS63146439 A JP S63146439A JP 29253386 A JP29253386 A JP 29253386A JP 29253386 A JP29253386 A JP 29253386A JP S63146439 A JPS63146439 A JP S63146439A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- contact
- rounded
- corners
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000011229 interlayer Substances 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 4
- 229910045601 alloy Inorganic materials 0.000 abstract description 2
- 239000000956 alloy Substances 0.000 abstract description 2
- 229910021332 silicide Inorganic materials 0.000 abstract description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 3
- 229910052782 aluminium Inorganic materials 0.000 abstract 3
- 238000001020 plasma etching Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は半導体装置の形成方法に関する。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a method for forming a semiconductor device.
(従晶術)
半導体装置の微細化に伴ってコンタクトサイズは減少し
、しかしながら、層間膜の厚、さはさほど減少しないた
めにコンタクトホールの横方向長さに対する縦方向の長
さの比(アスペクト比)は大きくなってくる。そこで単
に真直ぐな穴を形成し、そこに配線用材料たとえばIJ
f: depoするとコンタクトの底面や側面のM被
覆度がひく<、良好な;ンタクトがとれない。館1図は
それを改善するために従来行われていた方法を示したも
のである。先ずレジスト11のコンタクト部分をぬき(
a)、等方性プラズマエツチングを用いて810212
゛−の上面一部のみをエツチングしQ))、その後異方
性エツチング(RIE)により下地AA!13や81ま
でエツチングすることによりロが開けたコンタクトを形
成している((C)〜(e))、Lかしこの方法を用い
た場合、例えばP −CVD S ioz膜のように等
方性プラズマエツチングのエツチングレートが顕しく低
いものについてはコンタクドロを広げることができない
。(Merocrystalline technique) As semiconductor devices become smaller, the contact size decreases, but the thickness and size of interlayer films do not decrease significantly, so the ratio of the vertical length to the horizontal length of the contact hole (aspect ratio) becomes larger. Therefore, simply make a straight hole and fill it with a wiring material such as IJ.
f: When deposited, the M coverage on the bottom and side surfaces of the contact is low <, good; contact cannot be maintained. Figure 1 shows the conventional method used to improve this. First, remove the contact part of resist 11 (
a), 810212 using isotropic plasma etching
Etching only a part of the upper surface of Q)), then anisotropic etching (RIE) to make the base AA! By etching up to 13 and 81, a contact with an open side is formed ((C) to (e)). If the etching rate of plasma etching is significantly low, it is not possible to expand the contact depth.
(発明が解決しようとする問題点)
この発明は上述した従来の半導体装置形成方法の欠点を
改良したものでコンタクドロの丸めを簡単なプロセスで
しかも等方性プラズマエツチングを使えない膜にも実現
することを目的とする。(Problems to be Solved by the Invention) This invention improves the above-mentioned drawbacks of the conventional semiconductor device forming method, and enables rounding of contact holes through a simple process, even on films for which isotropic plasma etching cannot be used. The purpose is to
(問題点を解決するための手段)
上記の問題点を解決するために本発明は、レジストにコ
ンタクト開口用の穴を形成した後に熱処理を加えること
によりレジストの角を丸め、その後にエッチメックRI
Eを行うことによりコンタクト口の丸め部を形成するこ
とを特徴とする。(Means for Solving the Problems) In order to solve the above problems, the present invention provides a method of rounding the corners of the resist by applying heat treatment after forming holes for contact openings in the resist, and then performing etchmection RI.
A feature is that a rounded portion of the contact opening is formed by performing E.
(作 用)
比較的低い温度(百数十℃)で短時間の熱処理を行うこ
とでレジストの角は簡単に丸められる。(Function) The corners of the resist can be easily rounded by performing heat treatment for a short time at a relatively low temperature (more than 100 degrees Celsius).
ゆえにレジストと層間膜とのRIEエツチング選択比を
充分低くとれればそのレジストの形状をそのまま層間膜
に転写できることになる。特に本発明ではレジストの丸
め全利用しているため簡単な熱処理でその形状をコント
ロールすることができ、また等方性プラズマエッチでは
ほとんどエツチングされない様な層間膜についてもコン
タクドロの拡大を行うことができる。またレジストはエ
ッチバックRIEにより完全に除去してしまうためレジ
スト除去のプロセスを特に必要とせず工程の簡略化にも
なる。Therefore, if the RIE etching selectivity between the resist and the interlayer film can be made sufficiently low, the shape of the resist can be directly transferred to the interlayer film. In particular, in the present invention, since the resist is fully rounded, its shape can be controlled by simple heat treatment, and the contact depth can be expanded even for interlayer films that are hardly etched by isotropic plasma etching. . Further, since the resist is completely removed by etchback RIE, no special process for removing the resist is required, which simplifies the process.
(実施例) 次に本発明を1実施例につき図面を参照し。(Example) Next, reference will be made to the drawings for an embodiment of the present invention.
詳述する。第2図(a)〜(e)は本発明による半導体
装置の形成方法を概略説明するための断面図である。Explain in detail. FIGS. 2(a) to 2(e) are cross-sectional views for schematically explaining a method for forming a semiconductor device according to the present invention.
レジスト21をコンタクト形成用にパターニングした後
(a)、熱処理(100〜200°0程度)を施こすこ
とによりその角を丸めるう)、そのレジストを用いてエ
ッチメックRIEにより層間膜例えばシリコン酸化膜2
2を下地例えばA123までエツチングすることにより
その角の丸まったレジスト形状をシリコン酸化膜に転写
し、コンタクドロを丸める( (c) 、 (d) )
。その後、配線材料例えばAlをdep。After patterning the resist 21 for contact formation (a), the corners are rounded by heat treatment (approximately 100 to 200°0), and the resist is used to form an interlayer film, such as a silicon oxide film, by etch-mec RIE. 2
By etching 2 to the base material, for example, A123, the resist shape with rounded corners is transferred to the silicon oxide film, and the contact area is rounded ((c), (d))
. After that, a wiring material such as Al is deposited.
し、バターニングして電極を形成する(e)。下地とし
てはMの他Sib シリサイドその他合金なども考えら
れる。and patterning to form an electrode (e). In addition to M, Sib silicide and other alloys may be used as the base.
本発明によれば等方性グラズマエッチングでほとんどエ
ツチングされないような層間膜についてもコンタクドロ
の丸めを簡単なプロセスで行い、良好な電極を形成する
ことができる。According to the present invention, even for an interlayer film that is hardly etched by isotropic glazma etching, the contact hole can be rounded by a simple process and a good electrode can be formed.
第1図は従来の電極形成方法の概略図、!2図は本発明
における電極形成方法を示す説明図である。
11・・・レジスト
12・・・シリコン酸化膜
13・・・下地A1
14・・・上層Al
21・・・レジストFigure 1 is a schematic diagram of the conventional electrode formation method. FIG. 2 is an explanatory diagram showing the electrode forming method in the present invention. 11...Resist 12...Silicon oxide film 13...Base A1 14...Upper layer Al 21...Resist
Claims (1)
を形成したレジストを熱処理によりリフローさせ、その
角を丸めた後、エッチバックRIEを用いてコンタクト
開口用層間膜にレジスト形状を転写し、それによりコン
タクト丸めを行うことを特徴とする半導体装置の電極形
成方法。When forming electrodes of a semiconductor device, a resist with holes for contact holes is reflowed by heat treatment, its corners are rounded, and then the shape of the resist is transferred to an interlayer film for contact openings using etchback RIE. A method for forming an electrode of a semiconductor device, characterized in that contact rounding is thereby performed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29253386A JPS63146439A (en) | 1986-12-10 | 1986-12-10 | Forming method for electrode of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29253386A JPS63146439A (en) | 1986-12-10 | 1986-12-10 | Forming method for electrode of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63146439A true JPS63146439A (en) | 1988-06-18 |
Family
ID=17783027
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP29253386A Pending JPS63146439A (en) | 1986-12-10 | 1986-12-10 | Forming method for electrode of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63146439A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005294534A (en) * | 2004-03-31 | 2005-10-20 | Sharp Corp | Through electrode structure, semiconductor substrate lamination module and through electrode forming method |
US7955984B2 (en) * | 2006-12-28 | 2011-06-07 | Fujitsu Limited | High speed high power nitride semiconductor device |
-
1986
- 1986-12-10 JP JP29253386A patent/JPS63146439A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005294534A (en) * | 2004-03-31 | 2005-10-20 | Sharp Corp | Through electrode structure, semiconductor substrate lamination module and through electrode forming method |
US7955984B2 (en) * | 2006-12-28 | 2011-06-07 | Fujitsu Limited | High speed high power nitride semiconductor device |
US8519441B2 (en) | 2006-12-28 | 2013-08-27 | Fujitsu Limited | High speed high power nitride semiconductor device |
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