JPS6314488A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPS6314488A JPS6314488A JP15852686A JP15852686A JPS6314488A JP S6314488 A JPS6314488 A JP S6314488A JP 15852686 A JP15852686 A JP 15852686A JP 15852686 A JP15852686 A JP 15852686A JP S6314488 A JPS6314488 A JP S6314488A
- Authority
- JP
- Japan
- Prior art keywords
- solution
- substrate
- growth
- growing
- crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000013078 crystal Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000007790 solid phase Substances 0.000 claims abstract description 7
- 238000009826 distribution Methods 0.000 claims description 5
- 230000007547 defect Effects 0.000 abstract description 10
- 230000006866 deterioration Effects 0.000 abstract description 3
- 239000000155 melt Substances 0.000 abstract 1
- 238000005253 cladding Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体素子の製造方法に関し、さらに詳し
くは1段差を有する構造上に半導体埋込み層を結晶成長
させる半導体素子の製造方法において、結晶成長時に成
長面の界面付近に形成される欠陥を低減させるための改
良された製造方法に係るものである。Detailed Description of the Invention [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more specifically, in a method for manufacturing a semiconductor device in which a buried semiconductor layer is grown as a crystal on a structure having a one-step difference. The present invention relates to an improved manufacturing method for reducing defects formed near the interface of the growth surface during growth.
従来例によるのこの種の埋込み構造を有する半導体素子
の一例として、こへでは、アプライド・フィジックス・
レター(Applied Physics Lette
r)マo1.廷(In4) 337−339に示されて
いる埋込み型レーザダイオード(BH−LD)の概要構
成を第3図に示す。As an example of a conventional semiconductor device having this type of embedded structure, here we will introduce the Applied Physics
Applied Physics Letter
r) Mao1. FIG. 3 shows a schematic configuration of a buried laser diode (BH-LD) shown in In4 337-339.
すなわち、この第3図従来例構成において、符号lはn
”−1np基板、2はn−IMPクラッド層、3はp−
INFNチクド層、4はrnGaAsP活性層、5はp
+−InGaAsP=+ 7タクト層、6はn−1nP
埋込み層、7はp−InP埋込み層であり、また14は
p−InP埋込み層7と各層界面との間に生じている損
傷部分である。That is, in the conventional configuration shown in FIG. 3, the symbol l is n.
”-1np substrate, 2 is n-IMP cladding layer, 3 is p-
INFN layer, 4 rnGaAsP active layer, 5 p
+-InGaAsP=+ 7 tact layers, 6 is n-1nP
The buried layer 7 is a p-InP buried layer, and 14 is a damaged portion occurring between the p-InP buried layer 7 and each layer interface.
しかして、この従来例構成の場合、n”−1np基板1
とP” InGaAsPコンタクト層5間に、順方向電
圧を印加することにより、 InGaAsP活性層4内
にキャリアが注入され、?+−INPクラッド層2と、
p−IMPクラッド層3との屈折率差および禁止帯幅差
により電子、正孔がInGaAsP活性層4内に閉じ込
められ、かつn−1nP埋込み層8. p−TnP埋込
み層7により横方向にも閉じ込められて、この電子、正
孔が輻射再結合され、同第3図の垂直方向に光が伝搬す
るような共振器をへきかいなどで形成しておけば、ある
電流値を越えたところでレーザ発振を生ずることになる
。However, in the case of this conventional configuration, the n''-1np substrate 1
By applying a forward voltage between the P'' and InGaAsP contact layers 5, carriers are injected into the InGaAsP active layer 4, and the ?+-INP cladding layer 2 and
Electrons and holes are confined within the InGaAsP active layer 4 due to the difference in refractive index and band gap with the p-IMP cladding layer 3, and the n-1nP buried layer 8. A resonator should be formed in a cleavage or the like so that the p-TnP buried layer 7 confines the electrons and holes in the lateral direction, and the electrons and holes are radiatively recombined and the light propagates in the vertical direction as shown in FIG. For example, laser oscillation will occur when the current exceeds a certain value.
こ−で、この種の半導体レーザ素子の場合にあって、n
−1nP埋込み層6. p−1nP埋込み層7は、段差
を形成した基板の表面上に結晶成長されるために、成長
開始前の高温放置により表面が損傷されて、特にp−I
nP埋込み層7と各層界面の損傷部分14での結晶欠陥
が素子特性に悪影響をおよぼすことから、埋込み成長前
の基板表面保護に充分な注意が必要である。In the case of this type of semiconductor laser device, n
-1nP buried layer 6. Since the p-1nP buried layer 7 is crystal-grown on the surface of the substrate with steps formed, the surface is damaged by being left at a high temperature before the start of growth, and the p-1nP buried layer 7 is particularly susceptible to p-I
Since crystal defects in the nP buried layer 7 and damaged portions 14 at the interfaces of each layer adversely affect device characteristics, sufficient care must be taken to protect the substrate surface before buried growth.
このように、従来例での半導体レーザ素子にあっては、
埋込み成長をなす際に1段差を形成した基板の表面が、
成長開始前の高温放置によって損傷されるために、基板
の段差部分と埋込み層との界面付近に結晶欠陥などを生
じ、この結晶欠陥によって素子特性が劣化すると云う不
利があり、また、これを避けるために、従来1例えば、
結晶成長直前に非飽和溶液を基板に接触させて、その表
面を溶解させる手段があるが、この場合1表面溶解量の
制御が困難であると共に、溶解後、その溶液の一部が基
板表面に残留されて埋込み層成長溶液に混入し、埋込み
層の組成を制御できなくなるなどの問題点があった。In this way, in the conventional semiconductor laser device,
The surface of the substrate with one step formed during buried growth is
Since the crystal is damaged by being left at a high temperature before the growth starts, crystal defects occur near the interface between the step part of the substrate and the buried layer, which has the disadvantage of deteriorating the device characteristics, and this should be avoided. For example, conventionally,
There is a method of bringing an unsaturated solution into contact with the substrate immediately before crystal growth to dissolve the surface, but in this case, it is difficult to control the amount dissolved per surface, and after dissolution, a part of the solution may reach the substrate surface. There were problems such as remaining particles mixed into the buried layer growth solution, making it impossible to control the composition of the buried layer.
この発明は、従来のこのような問題点を解消するために
なされたものであり、その目的とするところは、半導体
埋込み層成長前の高温放置による基板表面の損傷を除去
して、埋込み層と各層界面との間に結晶欠陥を生じない
ようにすると共に、埋込み層自体の組成制御についても
、充分に再現性よく行ない得るようにした。この種の半
導体素子の製造方法を提供することである。This invention was made in order to solve these conventional problems, and its purpose is to eliminate damage to the substrate surface caused by leaving it at high temperatures before growing a semiconductor buried layer. In addition to preventing crystal defects from occurring between the interfaces of each layer, the composition of the buried layer itself can be controlled with sufficient reproducibility. It is an object of the present invention to provide a method for manufacturing this type of semiconductor device.
前記目的を達成するために、この発明に係る半導体素子
の製造方法は、段差構造上への半導体結晶成長用溶液と
して、溶液内に固相が存在する溶液を用い、溶液内の温
度分布が被成長基板と接触する部分で最も高温となる条
件で結晶成長を行なうようにしたものである。In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention uses a solution in which a solid phase exists as a solution for growing semiconductor crystals on a step structure, and the temperature distribution in the solution is Crystal growth is performed under conditions where the temperature is highest at the part that contacts the growth substrate.
従って、この発明方法の場合、半導体結晶成長用溶液は
、成長開始後にあって、一旦、被成長基板面を極く薄く
溶解するため、成長開始前の高温放置で生じた基板面の
損傷部分が除去された後に結晶成長される1、こ、と1
になり、これによって埋込み層界面での結晶欠陥発生を
防上できる。Therefore, in the case of the method of this invention, the semiconductor crystal growth solution is applied after the growth starts, and once the surface of the substrate to be grown is extremely thinly dissolved, the damaged parts of the substrate surface caused by being left at high temperatures before the start of growth are removed. 1, this, and 1 that are grown as crystals after being removed
This makes it possible to prevent crystal defects from occurring at the buried layer interface.
以下、この発明に係る半導体素子の製造方法の一実施例
につき、第1図および第2図を参照して詳細に説明する
。Hereinafter, one embodiment of the method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to FIGS. 1 and 2.
第1図はこの実施例方法を適用した埋込み型レーザダイ
オードの概要構成を模式的に示す断面図であり、第2図
は同上方法での成長炉における成長用ポートの概要構成
とその成長状態とを示す横断面図である。Fig. 1 is a cross-sectional view schematically showing the general structure of a buried laser diode to which this embodiment method is applied, and Fig. 2 shows the general structure of a growth port in a growth reactor according to the above method and its growth state. FIG.
第1図実施例構造において、前記第3図従来例構造と同
一符号は同一または均等部分を示しており、また第2図
において、符号8は炉心管、3はこの炉心管8内に装入
される被成長基板11のホルダーとしてのスライドポー
ト、10はこのスライドポート8上の溶液ホルダー、1
2はこの溶液ホルダー10に保持された半導体結晶成長
用溶液、13は同溶液12中の固相である。In the structure of the embodiment shown in FIG. 1, the same reference numerals as in the conventional structure shown in FIG. 3 indicate the same or equivalent parts, and in FIG. A slide port 10 serves as a holder for a substrate 11 to be grown, and 10 is a solution holder on this slide port 8;
2 is a semiconductor crystal growth solution held in this solution holder 10, and 13 is a solid phase in the solution 12.
そして、結晶成長に際しては、前記第2図に見られる通
り、炉心管8内での下部管壁側に被成長基板11.炉中
心側に成長用溶液12が、それぞれに存在するような配
置構成にすることで、溶液ホルダー10に保持された成
長用溶液12内での温度分布を、被成長基板11面に接
触する部分で最も高温になるようにでき、従って、この
成長条件では、成長開始後に、結晶成長用溶液12が、
一旦、被成長基板11面を極く薄い範囲で溶解した後に
、目的とする結晶成長がなされるため、成長開始前の高
温放置によって生じた基板11面の損傷部分14が自動
的に、除去されることになり、これによって埋込み層界
面での結晶欠陥発生を未然に防止でき、結果的に素子特
性の劣化を回避し得るのである。During crystal growth, as shown in FIG. 2, a growth target substrate 11. By arranging the growth solution 12 so that it exists on the center side of the furnace, the temperature distribution within the growth solution 12 held in the solution holder 10 can be adjusted to the part that contacts the surface of the growth substrate 11. Therefore, under these growth conditions, after the start of growth, the crystal growth solution 12 reaches the highest temperature.
Once the surface of the substrate 11 to be grown is melted in an extremely thin area, the desired crystal growth is performed, so that the damaged portion 14 on the surface of the substrate 11 caused by being left at high temperatures before the start of growth is automatically removed. Therefore, it is possible to prevent crystal defects from occurring at the buried layer interface, and as a result, deterioration of device characteristics can be avoided.
ご覧で、前記した成長用溶液!2の温度分布を被成長基
板11面に接触する部分で最も高温になるようにするた
めには、前記構成の番;辷かに、炉心管8と被成長基板
11との間にあって、別のヒーターなどを配することに
よっても実現でき、さらに半導体結晶成長用溶液12中
の固相13は、予め結晶成長用溶液12の過飽和度が2
0℃を越えるような溶液を用いるか、あるいは結晶成長
用溶液12の成分を含む化合物結晶を充分多量に加えて
おくことで実現できるのである。Look at the growth solution mentioned above! In order to make the temperature distribution of 2 so that the temperature is highest at the part that contacts the surface of the growth substrate 11, it is necessary to use the above structure; This can also be achieved by arranging a heater or the like. Furthermore, the solid phase 13 in the semiconductor crystal growth solution 12 is prepared in advance so that the supersaturation degree of the crystal growth solution 12 is 2.
This can be achieved by using a solution whose temperature exceeds 0°C or by adding a sufficiently large amount of compound crystals containing the components of the crystal growth solution 12.
なお、前記実施例方法では、 n”−1np基板上に半
導体埋込み層を結晶成長させる素子構成の場合について
述べたが、p”−1np基板上に結晶成長させる場合に
ついても同様に適用でき、また、前記実施例方法におい
ては、InGaAsP活性層5系の半導体材料の場合に
ついて述べたが、その他の半導体材料についても同様で
あり、さらに、前記実施例方法においては、段差を有す
る構造上に半導体埋込み層を結晶成長させる半導体レー
ザ素子の場合について述べたが、その他の埋込み構造を
有するレーザ素子、 LED素子、受光素子、電子デ
バイスなどに対しても、全く同様に適用できることは勿
論である。In addition, in the above-mentioned example method, the case of the device configuration in which the semiconductor buried layer is grown as a crystal on the n''-1np substrate is described, but it can be similarly applied to the case where the crystal is grown on the p''-1np substrate. In the method of the embodiment, the case of InGaAsP active layer 5-based semiconductor material was described, but the same applies to other semiconductor materials. Although the case of a semiconductor laser device in which crystal layers are grown has been described, it goes without saying that the present invention can be similarly applied to other laser devices having a buried structure, LED devices, light receiving devices, electronic devices, etc.
以上詳述したように、この発明方法によるときは、半導
体素子の段差を有する構造上に半導体埋込み層を結晶成
長させる場合、段差構造上への結晶成長用溶液として、
溶液内に固相が存在する溶液を用い、溶液内の温度分布
が被成長基板と接触する部分で最も高温となる条件で結
晶成長を行なうようにしたから、このように設定された
成長条件では、成長開始後にあって、まず、結晶成長用
溶液が、一旦、被成長基板面を極く薄い範囲で溶解した
後、続いて、目的とする半導体結晶成長がなされるため
に、成長開始前の高温放置によって生じた基板面の損傷
部分が自動的に除去され、これによって埋込み層界面で
の結晶欠陥の発生を未然に防出でき、結果的には素子特
性の劣化を回避し得るのであり、また、結晶成長直前に
非飽和溶液で基板表面を溶解させる手段とは異なって、
埋込み層の組成を容易に制御でき、このために埋込み層
自体を、充分に再現性よく結晶成長できるなどの優れた
特長を有するものである。As described in detail above, when using the method of the present invention, when crystal-growing a semiconductor buried layer on a structure having steps of a semiconductor element, as a solution for crystal growth on the step structure,
We used a solution in which a solid phase exists, and the crystal growth was performed under conditions where the temperature distribution in the solution was the highest at the part in contact with the growth substrate, so under the growth conditions set in this way, After the start of growth, the crystal growth solution first dissolves the surface of the substrate to be grown in a very thin area, and then the target semiconductor crystal grows. Damaged parts of the substrate surface caused by high-temperature storage are automatically removed, thereby preventing the occurrence of crystal defects at the buried layer interface, and as a result, deterioration of device characteristics can be avoided. Also, unlike the method of dissolving the substrate surface with an unsaturated solution immediately before crystal growth,
It has excellent features such as the ability to easily control the composition of the buried layer and, therefore, the ability to grow crystals of the buried layer itself with sufficient reproducibility.
第1図はこの発明に係る半導体素子の製造方法の一実施
例を適用した埋込み型レーザダイオードの概要構成を模
式的に示す断面図、第2図は同上方法での成長炉におけ
る成長用ポートの概要構成とその成長状態とを示す横断
面図であり、また第3図は従来例による埋込み型レーザ
ダイオードの概要構成を模式的に示す断面図である。
1・・・・n”−Inp基板、2・・・・n−INPN
チクド層、3・・・・p−IMPクラッド層、4・・・
・InGaAsP活性層5 ” ・・P+−InGaA
sP=+ 7タクト層、8−・・−n−1nP埋込み層
、?・・・・p−1nP埋込み層、8・・・・炉心管、
3・・・・スライドポート、10・・・・溶液ホルダー
、11・・・・被成長基板、12・・・・半導体結晶成
長用溶液、13・・・・半導体結晶成長用溶液中の固相
。
代理人 大 岩 増 雄
+3.キ嬶体昂晶へ長日落命中の固凋
第3図
手続補正書(自発)
昭和 6¥ 11月19日
2、発明の名称
半導体素子の製造方法
3、補正をする者
代表者志岐守哉
4、代理人
5、補正の対象
(1) 明細書の発明の詳細な説明の欄6、補正の内
容
(1)明細書2頁7行、13行のrn”−TnpJを「
n+−InPJ と補正する。
(2)同書2頁7行、16行のr n−INPJをrn
−1nPJ と補正する。
(3)同書2頁8行、16行のr p−INPJをrp
−1nPJ と補正する。
(4)同書7頁10行のrn”−1npJをrn”−1
nPJと補正する。
(5)同書7頁12行のr p”−TnpJをrp”−
InPJと補正する。
(8)同書9頁11行のrn’−1npJをrn”−I
nlJと補正する。
(7)同書9頁11行のr n−INPJをrn−1n
PJと補正する。
(8)同書9頁12行のr p−INPJをr p−1
nPJと補正する。
(9)図面の第1図、第3図を別紙のとおり補正する。
以上
第3図FIG. 1 is a cross-sectional view schematically showing the general structure of a buried laser diode to which an embodiment of the semiconductor device manufacturing method according to the present invention is applied, and FIG. FIG. 3 is a cross-sectional view schematically showing the general structure and its growth state, and FIG. 3 is a cross-sectional view schematically showing the general structure of a conventional buried laser diode. 1...n"-Inp board, 2...n-INPN
Chikudo layer, 3...p-IMP cladding layer, 4...
・InGaAsP active layer 5'' ・・P+-InGaA
sP=+ 7 tact layers, 8-...-n-1nP buried layers, ? ... p-1nP buried layer, 8 ... reactor core tube,
3...Slide port, 10...Solution holder, 11...Growth substrate, 12...Semiconductor crystal growth solution, 13...Solid phase in the semiconductor crystal growth solution . Agent Masuo Oiwa +3. Written amendment to the procedure for Figure 3, which has been in decline for a long time (voluntary), Showa 6 yen, November 19, 2, Title of the invention: Method for manufacturing semiconductor devices 3, Representative of the person making the amendment: Moriya Shiki 4 , Agent 5, Subject of amendment (1) Column 6 of detailed explanation of the invention in the specification, Contents of amendment (1) Change rn”-TnpJ on page 2, line 7 and line 13 of the specification to “
Correct as n+-InPJ. (2) r n-INPJ on page 2, lines 7 and 16 of the same book as rn
Correct it to -1nPJ. (3) r p-INPJ on page 2, lines 8 and 16 of the same book.
Correct it to -1nPJ. (4) rn”-1 npJ on page 7, line 10 of the same book
Correct with nPJ. (5) r p”-TnpJ in the same book, page 7, line 12, rp”-
Correct with InPJ. (8) rn'-1npJ on page 9, line 11 of the same book as rn''-I
Correct with nlJ. (7) r n-INPJ on page 9, line 11 of the same book as rn-1n
Correct with PJ. (8) r p-INPJ on page 9, line 12 of the same book as r p-1
Correct with nPJ. (9) Figures 1 and 3 of the drawings will be corrected as shown in the attached sheet. Figure 3 above
Claims (1)
層を結晶成長させる場合、段差構造上への結晶成長用溶
液として、溶液内に固相が存在する溶液を用い、溶液内
の温度分布が被成長基板と接触する部分で最も高温とな
る条件で結晶成長を行なうことを特徴とする半導体素子
の製造方法。(1) When crystal-growing a semiconductor buried layer on a structure with steps of a semiconductor element, a solution in which a solid phase exists is used as the solution for crystal growth on the step structure, and the temperature distribution in the solution is controlled. A method for manufacturing a semiconductor device, characterized in that crystal growth is performed under conditions such that the highest temperature is reached at the part that contacts the growth target substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15852686A JPS6314488A (en) | 1986-07-04 | 1986-07-04 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15852686A JPS6314488A (en) | 1986-07-04 | 1986-07-04 | Manufacture of semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6314488A true JPS6314488A (en) | 1988-01-21 |
Family
ID=15673659
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15852686A Pending JPS6314488A (en) | 1986-07-04 | 1986-07-04 | Manufacture of semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6314488A (en) |
-
1986
- 1986-07-04 JP JP15852686A patent/JPS6314488A/en active Pending
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