JPS5827238B2 - Single crystal manufacturing method - Google Patents
Single crystal manufacturing methodInfo
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- JPS5827238B2 JPS5827238B2 JP55182369A JP18236980A JPS5827238B2 JP S5827238 B2 JPS5827238 B2 JP S5827238B2 JP 55182369 A JP55182369 A JP 55182369A JP 18236980 A JP18236980 A JP 18236980A JP S5827238 B2 JPS5827238 B2 JP S5827238B2
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Description
【発明の詳細な説明】
本発明は単結晶の製造方法、詳しくは単結晶成長中に電
流をパルス的に加えることによって結晶欠陥のない高品
質単結晶を得る結晶成長法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for producing a single crystal, and more particularly to a crystal growth method for obtaining a high-quality single crystal free of crystal defects by applying current in pulses during the growth of the single crystal.
従来、半導体のSiやQaAsに代表される単結晶を電
気、電子装置に応用するためには、単結晶基板上に同種
あるいは異種の結晶を成長させるエビクキシャル成長法
が工業的に用いられている。Conventionally, in order to apply single crystals such as semiconductors Si and QaAs to electrical and electronic devices, an evixaxial growth method in which crystals of the same type or different types are grown on a single crystal substrate has been used industrially.
これらの成長法によって結晶欠陥、特に転位の発生を抑
制することが高晶質結晶を得るための要点である。The key to obtaining highly crystalline crystals is to suppress the occurrence of crystal defects, particularly dislocations, by these growth methods.
エビクキシャル成長法においては、基板と結晶格子定数
の異る結晶を成長させる場合に、格子のミスフィツトに
よる転位が発生し、結晶品質を劣化させるという問題が
ある。In the evixaxial growth method, when growing a crystal having a different crystal lattice constant from that of a substrate, there is a problem in that dislocations occur due to lattice misfit and deteriorate the crystal quality.
これに対しては、例えば、格子定数がゆるやかに変化す
るような組成の結晶をまず成長させ、その後所定の組成
の結晶を成長させるという、いわゆるバッファ層をつく
る手法、また、格子定数の少しづつ異る結晶を層状に成
長させる手法等が報告されている。To deal with this, for example, there are methods to create a so-called buffer layer, in which a crystal with a composition whose lattice constant gradually changes is first grown, and then a crystal with a predetermined composition is grown, and a method in which the lattice constant changes gradually. A method of growing different crystals in layers has been reported.
このようなエビクキシャル成長法では、バッファ層をつ
くるため格子定数を精密に制御する必要があり、例えば
スライドボート法による液相成長法ではバッファ層を構
成するために、余分の融液溜を設け、成長を行わねばな
らないという欠点がある。In such eviaxial growth methods, it is necessary to precisely control the lattice constant in order to create a buffer layer. For example, in liquid phase growth using a slide boat method, an extra melt reservoir is provided to create a buffer layer. The disadvantage is that it requires growth.
またバッファ層の厚さを成長中に精密に制御することは
必ずしも容易でないと言う困難もあった。Another problem is that it is not always easy to precisely control the thickness of the buffer layer during growth.
本発明はこのような欠点を除去すること、詳しくは結晶
欠陥のない良好な単結晶を安価に作業性良く融液等より
製造する方法を提供せんとするものである。The present invention aims to eliminate these drawbacks, and more specifically, to provide a method for producing a good single crystal without crystal defects from a melt or the like at low cost and with good workability.
したがって、本発明による単結晶の製造方法は、格子定
数の異なる種結晶あるいは基板結晶を用いて単結晶を製
造するに際し、前記単結晶の製造原料である融液あるい
は多結晶と種結晶あるいは基板結晶間に、一時的に前記
融液あるいは多結晶側より前記種結晶あるいは基板結晶
側に電流を流して結晶転位及び結晶欠陥の伝播を断つこ
とを特徴とするものである。Therefore, in the method for producing a single crystal according to the present invention, when producing a single crystal using seed crystals or substrate crystals having different lattice constants, the melt or polycrystal, which is the raw material for producing the single crystal, and the seed crystal or substrate crystal are used. During this period, a current is temporarily passed from the melt or polycrystal side to the seed crystal or substrate crystal side to interrupt the propagation of crystal dislocations and crystal defects.
本発明によれば、単結晶を成長させるに際し、格子のミ
スフィツトによる転位などの結晶欠陥を逆電流を流すこ
とにより防止することができ、良好な単結晶を得ること
が可能となる。According to the present invention, when growing a single crystal, crystal defects such as dislocations due to lattice misfit can be prevented by flowing a reverse current, making it possible to obtain a good single crystal.
本発明を更に詳しく説明する。The present invention will be explained in more detail.
本発明においては、融液あるいは多結晶より単結晶を成
長させるに際し、一時的に前記融液あるいは多結晶から
前記種結晶あるいは基板結晶に電流を流すものである。In the present invention, when growing a single crystal from a melt or polycrystal, a current is temporarily passed from the melt or polycrystal to the seed crystal or substrate crystal.
単結晶を製造する方法の典型的方法としては、(1)融
液と種結晶とを接触させて、種結晶を回転上昇させなが
ら単結晶を製造する、いわゆるチョクラルスキー法、
(2)基板結晶上の融液の温度を除々に低下させ過飽和
状態とし、前記基板上に単結晶を成長せしめる方法(た
とえばスライドボード法)、(3)種結晶に成長した多
結晶をリング状発熱体で加熱し、単結晶とする方法(た
とえば浮遊帯溶融法)、
(4)基板結晶と融液間に結晶基板側(陽極)より電流
を流しく以下、順極性と言う)、結晶を成長せしめる方
法(たとえばエレクトロマイグレーション法)、などが
あるが、本発明による方法は、このいずれの方法におい
ても用いることができる。Typical methods for manufacturing single crystals include (1) the so-called Czochralski method, in which a melt and a seed crystal are brought into contact and a single crystal is manufactured while rotating and raising the seed crystal; (2) a substrate method; A method of gradually lowering the temperature of the melt on the crystal to a supersaturated state and growing a single crystal on the substrate (for example, slide board method); (3) heating the polycrystal grown on the seed crystal with a ring-shaped heating element; (4) A method of forming a single crystal (for example, the floating zone melting method), (4) a method of flowing a current between the substrate crystal and the melt from the crystal substrate side (anode) (hereinafter referred to as "forward polarity"), a method of growing the crystal ( For example, electromigration method), etc., and the method according to the present invention can be used in any of these methods.
前述の(1) 、 (2) 、 (3)の方法で単結晶
を製造する場合、種結晶あるいは基板結晶を陰極とし、
融液あるいは多結晶を陽極として、一時約に電流を流が
す。When producing a single crystal using the methods (1), (2), and (3) above, the seed crystal or substrate crystal is used as a cathode,
Using the melt or polycrystal as an anode, a current is temporarily passed through it.
エレクトロマイグレーション法の場合、順極性に流して
いた電流を一時的に逆に流す(逆極性に流す)ことによ
り行なうことができ、また、一時的に電流を停止し、瞬
間的に逆極性が生ずることを利用して、逆電流を流すよ
うにしてもよい。In the case of the electromigration method, it can be carried out by temporarily reversing the current that was flowing in the forward polarity (flowing it in the opposite polarity), or by temporarily stopping the current and causing the reverse polarity to occur momentarily. Taking advantage of this fact, a reverse current may be caused to flow.
電流を流す時期は任意に定めうる。The timing at which the current is applied can be arbitrarily determined.
次に本発明の実施例について説明する。Next, examples of the present invention will be described.
実施例
第1図は本発明による方法を用いたGa AsGa A
e As系液相エピクキシャル成長の際に用いる成長装
置の一例の断面図であり、図中、1はグラファイトボー
ト、2はグラファイトスライダ、3は窒化ホロンの絶縁
板、4はグラファイトスライダ保持具、5,6はステン
レス製電極端子、であり、それぞれグラファイトボート
1とグラファイトスライダー2に固着されている。Example FIG. 1 shows Ga AsGa A using the method according to the present invention.
e It is a sectional view of an example of a growth apparatus used in As-based liquid phase epitaxial growth, and in the figure, 1 is a graphite boat, 2 is a graphite slider, 3 is an insulating plate of holon nitride, 4 is a graphite slider holder, 5 , 6 are stainless steel electrode terminals, which are fixed to the graphite boat 1 and graphite slider 2, respectively.
7はGaAeAs Qa飽和融液、8はGaAs基板
、9はGaAs裏面の電極端子、10はソース結晶であ
る。7 is a GaAeAs Qa saturated melt, 8 is a GaAs substrate, 9 is an electrode terminal on the back surface of GaAs, and 10 is a source crystal.
この装置によって結晶成長を行う手法は一般的なスライ
ドボート法によるもめとほぼ同じである。The method of crystal growth using this device is almost the same as the general slide boat method.
すなわち、先ずスライダー2を移動させ、グラファイト
ボート1の融液溜にあるGa AIJ As −Ga融
液7をソース結晶(通常はノンドープ結晶)10上にお
き所定の温度(通常750〜900′c)で平衡させる
。That is, first, the slider 2 is moved, and the Ga AIJ As -Ga melt 7 in the melt reservoir of the graphite boat 1 is placed on the source crystal (usually a non-doped crystal) 10 at a predetermined temperature (usually 750 to 900'C). Equilibrate with
平衡に達した後、融液7をGaAs基板8上に移動させ
結晶成長を開始する。After reaching equilibrium, the melt 7 is moved onto the GaAs substrate 8 to start crystal growth.
結晶成長はボート1全体の温度を徐々に下げ、融液7中
に過飽和状態を起こさせて成長させる方法が一般的であ
るが、前述のようにステンレスを極5,6から電流(ス
ライダー2側を■、ボート1側を○)を流す、いわゆる
エレクトロマイグレイジョン(たとえばり、 Jast
zebski 、 Y、 1.mamura。The general method for crystal growth is to gradually lower the temperature of the entire boat 1 to create a supersaturation state in the melt 7, but as mentioned above, the stainless steel is heated with electric current (on the slider 2 side) from the poles 5 and 6. So-called electromigration (for example, Just
zebski, Y, 1. Mamura.
and H,C,Gatos 、 J、 Electr
ocnem Soc。and H, C, Gatos, J, Electr.
ocnem Soc.
125、(1978)i140.)による成長によって
も可能である(従来のこれらの成長では、Ga As基
板8上にGa Ae Asの単結晶が成長するが、Ga
AI As中のAI量が0.25以上になるとGaA
sとの格子定数の差が0.1%以上となり、ミスフィツ
ト転位が発生することが判っている)。125, (1978) i140. ) (In these conventional growth methods, a single crystal of GaAeAs is grown on the GaAs substrate 8, but
AI When the amount of AI in As becomes 0.25 or more, GaA
It is known that misfit dislocations occur when the difference in lattice constant from s is 0.1% or more).
このような装置を用い、エレクトマイクレージョン法で
GaO,6A6o、4 Asの単結晶を製造した。Using such an apparatus, single crystals of GaO, 6A6o, and 4As were produced by the electromicresion method.
800℃において、電流を10A/Hで順極性で流した
場合(融液e1基板■)成長速度が03μm/7iπと
なった。When a current of 10 A/H was passed with forward polarity at 800° C. (melt e1 substrate ■), the growth rate was 03 μm/7iπ.
成長開始に先立って、電流を逆極性すなわち融液■、基
板eとすることにより、基板8表面を融解し、Ga A
6 As −Ga融液7と基板8とのぬれ性をよくした
後、順極性にして成長を開始し、約10分成長させる。Prior to the start of growth, the surface of the substrate 8 is melted by applying a current of opposite polarity, that is, the melt (2) and the substrate (e), and the Ga A
6 After improving the wettability between the As--Ga melt 7 and the substrate 8, the growth is started with forward polarity and allowed to grow for about 10 minutes.
この初期成長は基板8中に含まれている不純物が融液7
中に拡散し、融液7を汚すのを防ぐ効果があるが、ミス
フィツト転位が発生する。This initial growth is caused by impurities contained in the substrate 8 in the melt 7.
This has the effect of preventing the particles from diffusing into the melt and contaminating the melt 7, but misfit dislocations occur.
次に電流を一旦切り約1秒無通電状態にした後、再びI
OA/7で電流を流すとミスフィツト転位の少い単結晶
層を成長させることができた。Next, turn off the current and leave it in a non-energized state for about 1 second, then turn on again.
When a current was applied at OA/7, a single crystal layer with few misfit dislocations could be grown.
この現象が生じる理由は必ずしも明らかでないが、次の
ように考えることができる。Although the reason why this phenomenon occurs is not necessarily clear, it can be considered as follows.
GaAs基板8にGa Ae Asが戊長し始めると、
ミスフィツト転位が発生し、その転位の中でも基板8面
に垂直あるいは垂直に近い角度で発生したものは、結晶
成長が進行しても途中で消えることなく伝播してゆくと
考えられる。When GaAe As begins to elongate on the GaAs substrate 8,
Misfit dislocations are generated, and among these dislocations, those generated at angles perpendicular or close to perpendicular to the 8 surfaces of the substrate are considered to propagate without disappearing midway through the progress of crystal growth.
ところが、成長途中で電流を切ると瞬間的に成長が停止
するばかりでなく、電気的スイッチングの一般的性質と
して第2図で示すような逆極性の部分Aが現れるものと
考えられ、この瞬間、結晶成長端面は再融解が起るもの
と推測される。However, if the current is cut off during the growth, not only will the growth stop instantaneously, but it is thought that, as a general property of electrical switching, a portion A of opposite polarity as shown in Figure 2 will appear, and at this moment, It is assumed that remelting occurs at the crystal growth end face.
従って、それまで伝播してきた転位は、この再融解で断
切られることになり、再び成長させても、もはや基板8
から伝播してきた転位は無いため無転位の結晶層を得る
ことができると推定される。Therefore, the dislocations that have propagated up to that point will be cut off by this remelting, and even if they grow again, they will no longer be able to reach the substrate 8.
It is presumed that a dislocation-free crystal layer can be obtained since there are no dislocations propagated from the crystal.
第3図にこの実施例によって得た結晶断面の2000倍
顕微鏡写真(1,1crrLが10μmに相当:を示す
。FIG. 3 shows a 2000x micrograph (1.1 crrL corresponds to 10 μm) of a cross section of the crystal obtained in this example.
この第3図中、中央部帯状部にはミスフィツト転位と思
われるエッチピット(黒点)が多数存在するのが見られ
る、その指状部上方には良好なGao、6Alo、4A
s単結晶が成長じているのがわかる(ちなみに指状部下
方はGa As基板)。In Fig. 3, it can be seen that there are many etch pits (black dots) that are thought to be misfit dislocations in the central band, and above the fingers there are good Gao, 6Alo, 4A
It can be seen that the s single crystal is growing (by the way, the lower part of the finger is a GaAs substrate).
電流を一時停止した所は帯状部と良好な単結晶の境界で
あり、電流の一時停止により、ミスフィツト転位のない
良好な単結晶が成長しているのが理解される。It can be seen that the place where the current is temporarily stopped is the boundary between the band and a good single crystal, and that a good single crystal without misfit dislocations is grown by the temporary stop of the current.
上記実施例と同様に、第4図に示す通電プログラムによ
り、Ga As基板上にGao、6 A60.4 As
単結晶を成長させた、この実施例によって得た結晶断面
の2000倍顕微鏡写真を第5図として示す。Similarly to the above embodiment, GaO, 6 A60.4 As
FIG. 5 shows a 2000x microscopic photograph of a crystal cross section obtained in this example in which a single crystal was grown.
この第5図中、写真下方1/3の部分に見える黒線が成
長開始時(したがって、その下方はGaAs基板)であ
り、そのすぐ上方にある白色部上端が逆極性パルス電流
の印加された時(即ち、黒線と白色部上端で囲まれた部
分が帯状部)である。In this Figure 5, the black line visible in the lower 1/3 of the photo is the time when growth started (therefore, below it is the GaAs substrate), and the upper end of the white part immediately above it is where the reverse polarity pulse current was applied. (that is, the area surrounded by the black line and the upper end of the white part is the band-shaped part).
この第5図よりも明かなように逆極性パルス電流が印加
された後は良好な単結晶が成長していることがわかる。As is clearer from FIG. 5, it can be seen that a good single crystal grows after the reverse polarity pulse current is applied.
以上説明したように、結晶成長途中に、結晶の成長面が
瞬間的に融解するような電気的パルスを加えると、それ
まで結晶中を伝播してきた転位が断ち切られるのである
から、単一パルスあるいは複数個のパルスを加えること
によってそれ以後無転位あるいは無欠陥の単結晶を成長
させることができる。As explained above, if an electric pulse that instantaneously melts the growing surface of the crystal is applied during crystal growth, the dislocations that have been propagating in the crystal up to that point will be cut off. By applying a plurality of pulses, a dislocation-free or defect-free single crystal can be grown thereafter.
この効果をダブルへテロ構造のレーザダイオード°の製
作に応用できる。This effect can be applied to the fabrication of double heterostructure laser diodes.
これまでGa As基板上には長波長発振をするGa
I n As系の層は格子定数が大きすぎて欠陥が多い
ため、GaAsより格子定数の大きなInPを使う必要
があった。Up until now, Ga As substrates have been used with Ga
Since the In As-based layer has a too large lattice constant and many defects, it was necessary to use InP, which has a larger lattice constant than GaAs.
しかしInPは高価で品質のよいものが得られない。However, InP is expensive and cannot be obtained with good quality.
そこでGa As基板上でGa I n As Pを高
欠陥で成長させても、本発明による方法でエピタキシャ
ル成長直径にパルス電流を通じ転位あるいは、転位に類
する結晶欠陥をなくすことができるのでInP基板を用
いる必要がない。Therefore, even if GaInAsP is grown with high defects on a GaAs substrate, the method of the present invention can eliminate dislocations or crystal defects similar to dislocations by applying a pulsed current to the epitaxial growth diameter, so there is no need to use an InP substrate. There is no.
またFETにおける基板と活性層の周の境界領域に対し
ても、本発明を適応することによって欠陥のない活性層
を得ることができる。Furthermore, by applying the present invention to the peripheral boundary region between the substrate and the active layer in an FET, a defect-free active layer can be obtained.
第1図は本発明の方法を実施するための装置の側断面図
、第2図は実施例における電気極性の変化を模式的に示
すグラフ、第3図は実施例の結晶断面顕微鏡写真、第4
図は他の実施例における電流印加プログラム、第5図は
前記実施例において成長させた結晶の断面顕微鏡写真で
ある。
1・・・グラファイトボード、2・・・グラファイトス
ライダ、3・・・窒化ボロン絶縁板、4・・・グラファ
イトスライダ保持具、5,6・・・ステンレス電極端子
、7− Ga Ae As −Ga融液、8 ”・Ga
As基板、9・・・電極端子、10・・・ソース結晶
。FIG. 1 is a side cross-sectional view of an apparatus for carrying out the method of the present invention, FIG. 2 is a graph schematically showing changes in electric polarity in Examples, and FIG. 3 is a microscopic photograph of a crystal cross section of Examples. 4
The figure shows a current application program in another example, and FIG. 5 is a cross-sectional micrograph of a crystal grown in the above example. DESCRIPTION OF SYMBOLS 1... Graphite board, 2... Graphite slider, 3... Boron nitride insulating board, 4... Graphite slider holder, 5, 6... Stainless steel electrode terminal, 7- Ga Ae As -Ga fusion Liquid, 8”・Ga
As substrate, 9...electrode terminal, 10...source crystal.
Claims (1)
単結晶を製造するに際し、前記単結晶の原料である融液
あるいは多結晶と前記種結晶あるいは基板結晶間に、一
時的に前記融液あるいは多結晶側よりパルス的電流を流
して結晶転位及び結晶欠陥の伝播を断つ工程を含むこと
を特徴とする単結晶の製造方法。1. When producing a single crystal using seed crystals or substrate crystals with different lattice constants, the melt or polycrystal is temporarily placed between the melt or polycrystal, which is the raw material for the single crystal, and the seed crystal or substrate crystal. A method for producing a single crystal, comprising the step of passing a pulsed current from the crystal side to cut off the propagation of crystal dislocations and crystal defects.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55182369A JPS5827238B2 (en) | 1980-12-23 | 1980-12-23 | Single crystal manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55182369A JPS5827238B2 (en) | 1980-12-23 | 1980-12-23 | Single crystal manufacturing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57106593A JPS57106593A (en) | 1982-07-02 |
JPS5827238B2 true JPS5827238B2 (en) | 1983-06-08 |
Family
ID=16117100
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP55182369A Expired JPS5827238B2 (en) | 1980-12-23 | 1980-12-23 | Single crystal manufacturing method |
Country Status (1)
Country | Link |
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JP (1) | JPS5827238B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH022330U (en) * | 1988-06-17 | 1990-01-09 | ||
JPH0349863B2 (en) * | 1985-07-26 | 1991-07-30 | Kanebo Ltd |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60102722A (en) * | 1983-11-09 | 1985-06-06 | Matsushita Electric Ind Co Ltd | Manufacture of single crystal ferrite |
JPH0930889A (en) * | 1995-07-18 | 1997-02-04 | Komatsu Electron Metals Co Ltd | Pull device for semiconductor single crystal |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4934790A (en) * | 1972-08-01 | 1974-03-30 |
-
1980
- 1980-12-23 JP JP55182369A patent/JPS5827238B2/en not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4934790A (en) * | 1972-08-01 | 1974-03-30 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0349863B2 (en) * | 1985-07-26 | 1991-07-30 | Kanebo Ltd | |
JPH022330U (en) * | 1988-06-17 | 1990-01-09 |
Also Published As
Publication number | Publication date |
---|---|
JPS57106593A (en) | 1982-07-02 |
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