JPS59129420A - Manufacture of compound semiconductor - Google Patents

Manufacture of compound semiconductor

Info

Publication number
JPS59129420A
JPS59129420A JP451283A JP451283A JPS59129420A JP S59129420 A JPS59129420 A JP S59129420A JP 451283 A JP451283 A JP 451283A JP 451283 A JP451283 A JP 451283A JP S59129420 A JPS59129420 A JP S59129420A
Authority
JP
Japan
Prior art keywords
inp
layer
gaas
solution
compound semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP451283A
Other languages
Japanese (ja)
Inventor
Shigeru Nagao
長尾　茂
Kazuhiro Sawa
沢　和弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP451283A priority Critical patent/JPS59129420A/en
Publication of JPS59129420A publication Critical patent/JPS59129420A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02392—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02461—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Weting (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)

Abstract

PURPOSE:To prevent the decrease of crystallinity due to the thermal decomposition of InP by a method wherein, after forming a multilayer film of a fixed thickness, the InP of the surface is protected with GaAs of dissociation pressure lower than that of the element, and the GaAs is selectively etched. CONSTITUTION:An N-InP 6, an InGaAsP 7 and a P-InP 8 are superposed on an N-InP substrate 1 by a liquid phase epitaxial method, and successively the GaAs 10 of a dissociation pressure lower than that of the InP is epitaxially formed. Next, when the layer 10 is selectively etched, the departure of crystal atoms from the surface of the InP epitaxial layer 8 is prevented, accordingly a substrate excellent in crystallinity without the generation of thermal pits can be obtained. The layer 10 is etched by dipping in HNO3 at 60 deg.C, but the InP 8 is hardly etched at this time.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は化合物半導体の製造方法、とくに、■−Ｖ族化
合物半導体結晶の液相エピタキシャル族２　　　〕゛ 多層の最終成長層の表面保護方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a compound semiconductor, and more particularly, to a method for protecting the surface of a liquid phase epitaxial group 2 multilayer final growth layer of a 1-V group compound semiconductor crystal.

従来例の構成とその問題点 光通信技術に使用される受発光素子材料として、近年、
たとえば、ＩｎＰを基板に用いたＩｎＧａＡｓＰ混晶が
長波長帯領域で有望視されてきている。Conventional configurations and their problems In recent years, as light-receiving and emitting element materials used in optical communication technology,
For example, InGaAsP mixed crystal using InP as a substrate is viewed as promising in the long wavelength band region.

通常、これらのデバイスを製作するだめの結晶製作技術
として、気相法と液相法とがあるが、比較的簡便な製造
装置で、再現性のある高品質の結晶が得られるため、液
相法が一般によく用いられる０ 液相法では、多層の薄膜を順次エピタキシャル成長する
ため、横型のボートが使用され、スライド法により、ダ
ブルへテロ構造を形成する方法が採用されている。Normally, the primary crystal manufacturing techniques for manufacturing these devices are the gas phase method and the liquid phase method, but the liquid phase method is the most reliable method because it allows reproducible, high-quality crystals to be obtained using relatively simple manufacturing equipment. In the commonly used liquid phase method, a horizontal boat is used to sequentially epitaxially grow multilayer thin films, and a sliding method is used to form a double heterostructure.

第１図（ａ）は、この方法の概略を示している。FIG. 1(a) shows an outline of this method.

成長ポート内に、ｎ型ＩｎＰ基板１と溶媒であるＩｎ、
および、ＩｎＰ、ＩｎＡｓ、ＧａＡｓ多結晶を入れ、飽
和溶液になるまで昇温する。溶液２は、高純度Ｉｎ溶液
であり、昇温時にＩｎＰ基板１の表面に生じたガスエッ
チ層をメルトバックするた３１・−ジ めのものである。In the growth port, an n-type InP substrate 1 and a solvent In,
Then, InP, InAs, and GaAs polycrystals are added, and the temperature is raised until a saturated solution is obtained. Solution 2 is a high-purity In solution, and is a 31-dimension solution for melting back the gas etched layer formed on the surface of the InP substrate 1 when the temperature is increased.

溶液３は、Ｔｏを添加したｎ型用ＩｎＰ溶液、溶液４は
、不純物を含まないＩｎＧａＡｓＰ溶液、溶液５はＺｎ
を添加したＰ型用ＩｎＰ溶液であり、ボートをスライド
することによって、これらの溶液の移動を行ない、各エ
ピタキシャル領域の形成を行なう。Solution 3 is an n-type InP solution added with To, solution 4 is an InGaAsP solution containing no impurities, and solution 5 is a Zn-type InP solution.
This is a P-type InP solution to which is added, and these solutions are moved by sliding a boat to form each epitaxial region.

上記の方法により得られた半導体基板の断面図を第１図
（ｂ）に示す。基板１上に、Ｎ型ＩｎＰ層６゜ＩｎＧａ
ＡｓＰ層７．Ｐ型ＩｎＰ層８の各層を順次エピタキシャ
ル成長させたものである。A cross-sectional view of the semiconductor substrate obtained by the above method is shown in FIG. 1(b). On the substrate 1, an N-type InP layer 6°InGa
AsP layer7. Each layer of the P-type InP layer 8 is epitaxially grown in sequence.

以上のようにして、結晶成長が終了するわけであるが、
以下のようなエピタキシャル成長上の問題点を有してい
る。As described above, crystal growth ends,
It has the following problems in epitaxial growth.

溶液５を取り去った後、エピタキシャル層の最上部には
、Ｐ型−ＩｎＰ層８が露出している。After removing the solution 5, a P-type-InP layer 8 is exposed on top of the epitaxial layer.

一方、通常、液相法の成長停止温度は、約６０ｏ℃付近
であり、露出しだＰ型−ＩｎＰ層８は比較的高い解離圧
を持つため、室温まで冷却する間に、表面層からＰ原子
の逃逸が起こり、結晶欠陥の一種であるサーマルビット
　（ｔｈｅｒｍａｌ　　ｐｉｔ）が多数発生ずる。この
ようなサーマルビットが多数発生した半導体基板を用い
て、素子を作成した場合には、表面リーク電流等が多く
なり、また、ＬＥＤを製作した場合結晶性の悪化による
発光効率低下が招来し、デバイスとしての特性が著しく
損なわれる場合がある。On the other hand, normally, the growth stop temperature in the liquid phase method is around 60°C, and the exposed P-type-InP layer 8 has a relatively high dissociation pressure, so during cooling to room temperature, P is removed from the surface layer. Atom escape occurs, and a large number of thermal pits, which are a type of crystal defect, are generated. If a device is made using a semiconductor substrate with many such thermal bits, surface leakage current, etc. will increase, and if an LED is made, the luminous efficiency will decrease due to deterioration of crystallinity. The characteristics of the device may be significantly impaired.

このため、これを防ぐため、最終のＰ型−ＩｎＰ層８を
成長した溶液を結晶成長終了後、基板表面から取り去ら
ずに、室温付近捷で冷却し結晶成長終了後、室ｆＭ、　
ｔでの間に成長した層をエツチングにより取り去る方法
がある。Therefore, in order to prevent this, the solution in which the final P-type-InP layer 8 was grown is cooled in a vacuum near room temperature after the crystal growth is completed without being removed from the substrate surface.
There is a method of removing the layer grown during t by etching.

しかし、この方法を用いるためには、極めて正確にＩｎ
Ｐ層８のエツチング量をコントロールすることが要求さ
れ、このコントロールが難題である。However, in order to use this method, the In
It is required to control the amount of etching of the P layer 8, and this control is a difficult problem.

発明の目的 本発明は、上述したような方法の問題点を取り除くこと
を目的としており、所定の厚さの多層膜を形成した後、
表面のＩｎＰ層を保護する目的で、成長終了後に、Ｉｎ
Ｐ層よりも解離圧の低いｔ−Ｖ族化合物半導体層を形成
し、この後、前述した最上部層を選択的にエツチングす
ることによって、サーマルビットの発生を防止し、結晶
性の低下を防ぐところにある。Purpose of the Invention The present invention aims to eliminate the problems of the above-mentioned methods, and after forming a multilayer film of a predetermined thickness,
In order to protect the InP layer on the surface, after the growth is completed, InP is
By forming a t-V group compound semiconductor layer having a lower dissociation pressure than the P layer, and then selectively etching the above-mentioned uppermost layer, the generation of thermal bits is prevented and the deterioration of crystallinity is prevented. There it is.

発明の構成 本発明は、要約するに、Ｉｌｉ　−Ｖ族化合物半導体基
板上にインジウムを溶媒に用いて液相法によりエピタキ
シャル層を成長後、前記エピタキシャル層を被って、同
層よりも解離圧の低い川−■族化合物成長層を形成する
第１工程と、前記解離圧の低いＩＩＩ　−Ｖ族化合物成
長層をエツチング除去する第２工程をそなえた化合物半
導体装置の製造方法であり、これにより、所望のエピタ
キシャル層の表面が解離圧の低い■−Ｖ族化合物成長層
で被われ、エピタキシャル層表面からの結晶原子逸脱の
現象を防止することができるとともに、前記の解離圧の
低い■−■族化合物成長層を、同層のみを選択的にエツ
チング除去することにより、完全なエピタキシャル層が
得られるのである。Components of the Invention To summarize, the present invention consists of growing an epitaxial layer on an Ili-V group compound semiconductor substrate by a liquid phase method using indium as a solvent, and then growing the epitaxial layer over the epitaxial layer to have a dissociation pressure higher than that of the same layer. A method for manufacturing a compound semiconductor device, comprising a first step of forming a grown layer of a group III-V compound having a low dissociation pressure, and a second step of etching away the grown layer of a group III-V compound having a low dissociation pressure. The surface of the desired epitaxial layer is covered with a growth layer of the ■-V group compound having a low dissociation pressure, and it is possible to prevent the phenomenon of crystal atoms deviating from the surface of the epitaxial layer. By selectively etching away only the compound growth layer, a complete epitaxial layer can be obtained.

実施例の説明 以下に具体的な実施例について述べる。ここでは、最上
部の保護膜としてＧａＡｓを用いた場合について記す。Description of Examples Specific examples will be described below. Here, a case will be described in which GaAs is used as the uppermost protective film.

ｎ型１ｎＰ基板１として、Ｓドープ（キャリア濃度４　
Ｘ　１０１８ｆｆｉ−）　　の（１ｏｏ、）を用いた。The n-type 1nP substrate 1 is S-doped (carrier concentration 4
(1oo,) of X 1018ffi-) was used.

第２図（ａ）に示すような成長ボートを用い、高純度Ｈ
２ガス中で６７５℃　まで昇温した。この温度で、１時
間保持した後、冷却速度０．５℃／ｍｉｎで冷却を開始
した。温度６５０″Ｃにて、高純度Ｉｎ溶液２をｎ型Ｉ
ｎＰ基板１と１０秒間接触し、続いて溶液３を接触させ
、Ｔｅ　ドープ（１×１０１８砿−５）のｎ型ＩｎＰ層
６を約１０μｍ成長させた。６３５°Ｃで、さらに溶液
を移動して、不純物を含まないＩｎ、−ｘＧａｘＡｓｌ
、　Ｐ、層（Ｘ＝０．３０．　ｙ＝ｏ、　６５）を形成
した。成長膜厚は約１μｍである。最後に温度６３１°
Ｃで溶液５と基板１を接触しＺｎ　ドープ（１ｘ　１０
’　８ｃｍ　３）のＰ型ＩｎＰ層８を６１０”Ｃまで成
長した。成長層厚は約１０μｍである。Using a growth boat as shown in Figure 2(a), high-purity H
The temperature was raised to 675°C in two gases. After maintaining this temperature for 1 hour, cooling was started at a cooling rate of 0.5° C./min. At a temperature of 650″C, high purity In solution 2 was converted into n-type I
It was brought into contact with the nP substrate 1 for 10 seconds, and then brought into contact with the solution 3 to grow a Te doped (1×10 18 K-5) n-type InP layer 6 to a thickness of about 10 μm. At 635 °C, the solution was further moved to obtain impurity-free In, -xGaxAsl.
, P, layer (X=0.30.y=o, 65) was formed. The thickness of the grown film is approximately 1 μm. Finally the temperature is 631°
Contact solution 5 and substrate 1 with C doped with Zn (1x 10
A P-type InP layer 8 of 8 cm 3) was grown to 610''C. The thickness of the grown layer was about 10 μm.

以上のようにして、ダブルへテロ構造をＩｎＰ基板１上
に形成した後、ＧａＡＳ溶液９をエピタキシャル成長層
の基板に接触させ、ＧａＡｓのエピタキシャル層１０を
Ｐ型ＩｎＰ領域８の」二部に１〜５μｍ形成し、溶液９
を取り去り室温まで冷却した。After forming the double heterostructure on the InP substrate 1 as described above, the GaAS solution 9 is brought into contact with the substrate of the epitaxial growth layer, and the GaAs epitaxial layer 10 is formed on the second part of the P-type InP region 8. 5μm formed, solution 9
was removed and cooled to room temperature.

ＩｎＰの格子定数は、α、、ｐ＝５．Ｂ６９Ａ、ＧａＡ
ｓの格子定数は、α６ａＡｓ−６，６５３＾　であり、
格子不整は約３．７％　であったが、平担な接合面を得
ることができた。The lattice constant of InP is α, p=5. B69A, GaA
The lattice constant of s is α6aAs-6,653^,
Although the lattice misalignment was approximately 3.7%, a flat joint surface could be obtained.

以上の操作により得られた半導体結晶断面を第２図（ｂ
）に示す。The cross section of the semiconductor crystal obtained by the above operations is shown in Figure 2 (b
).

次に、上記の半導体結晶を６０　”ＣのＨＮ　０３　　
溶液内に浸すことによって、最上部のＧａＡｓエピタキ
シャル層１０の選択エツチングを行なった。この時、Ｐ
型ＩｎＰ層８は、はとんどエツチングされず、熱分解に
起因すると思われるサーマルピットの発生も極端に少な
かった。ここで、もちろん、保護膜の材質としては、表
面のＰ型ＩｎＰ層８と選択エツチング性を有するものを
選ばなければならないことは明らかである。Next, the above semiconductor crystal was heated to 60”C HN 03
Selective etching of the top GaAs epitaxial layer 10 was performed by immersion in a solution. At this time, P
The type InP layer 8 was hardly etched, and there were extremely few thermal pits that were thought to be caused by thermal decomposition. Here, it is obvious that the material of the protective film must be selected to have selective etching properties with respect to the P-type InP layer 8 on the surface.

このような、選択エツチングを施こすことにより、必要
な厚さのＩｎＰ領域を再現性よく得ることができ、前述
した方法のようにＩｎＰ層のエツチングを精密にコント
ロールする必要が全くない。By performing such selective etching, an InP region of the required thickness can be obtained with good reproducibility, and there is no need to precisely control the etching of the InP layer as in the method described above.

発明の効果 以上述べてきたことから明らかなように、本発明によれ
は、たとえばＩｎＰを用いたダブルへテロ構造において
、最終成長層であるＰ型ＩｎＰ層の上部に、ＩｎＰより
も解離圧の低いＧａＡｓ領域を保護膜として形成し、こ
の後、ＧａＡｓ領域を選択的に除去することによって、
ＩｎＰエピタキシャル成長層の熱分解により生じるサー
マルピットの発生を抑え、結晶性の秀れた半導体基板を
得ることが可能である。Effects of the Invention As is clear from the above description, the present invention has the advantage that, for example, in a double heterostructure using InP, a layer with a dissociation pressure higher than that of InP is added to the top of the P-type InP layer, which is the final growth layer. By forming a low GaAs region as a protective film and then selectively removing the GaAs region,
It is possible to suppress the generation of thermal pits caused by thermal decomposition of the InP epitaxial growth layer and obtain a semiconductor substrate with excellent crystallinity.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）は、従来の液相成長法の概略を示す図、第
１図（１））は、同図（ａ）により得られた半導体結晶
の断面を示す図、第２図（ａ）は、本発明法の液相成長
法の概略を示す図、第２図（ｂ）は、同図（ａ）により
得られた基板断面を示す図である。 ９１−ジ １　　ｎ型ＩｎＰ基板、２　　　ｐｕｒｅＩｎ　溶液、
３　　ｎ型ＩｎＰ溶液、４−＝−ＩｎＧａＡｓＰ溶液、
５　　Ｐ型ＩｎＰ溶液、６−−　Ｔ　ｅ　　ドープｎ型
ＩｎＰエピタキシャル層、７−ｎｏｎ（１０ｐ６　Ｉｎ
ＧａＡｓＰエピタキシャル層、８−−　Ｚｎ　　ドープ
Ｐ型ＩｎＰエピタキシャル層、９−−ＧａＡｓ溶液、１
゜ｅａｒｓエピタキシャル領域。 代理人の氏名　弁理士　中　尾　敏　男　はが１名第１
図 （（１−］ （７・）FIG. 1(a) is a diagram showing an outline of the conventional liquid phase growth method, FIG. 1(1)) is a diagram showing a cross section of the semiconductor crystal obtained by FIG. 1(a), and FIG. 2(a) is a diagram schematically showing the liquid phase growth method of the present invention, and FIG. 2(b) is a diagram showing a cross section of the substrate obtained in FIG. 2(a). 91-Di 1 n-type InP substrate, 2 pureIn solution,
3 n-type InP solution, 4-=-InGaAsP solution,
5 P-type InP solution, 6--Te doped n-type InP epitaxial layer, 7-non (10p6 InP
GaAsP epitaxial layer, 8--Zn doped P-type InP epitaxial layer, 9--GaAs solution, 1
゜ears epitaxial region. Name of agent: Patent attorney Toshio Nakao (1st person)
Figure ((1-) (7・)

Claims (1)

【特許請求の範囲】[Claims] （１）Ｉｌｌ−Ｖ族化合物半導体基板上にインジウムを
溶媒に用いて液相法により最浅部エピタキシャル層を成
長後、前記最浅部エピタキシャル層を被って、同層よシ
も解離圧の低い■−■族化合物半導体層を形成する第１
工程と、前記解離圧の低いｌ１ｌ−ｖ族化合物半導体層
をエツチング除去する第２工程をそなえた化合物半導体
生霊の製造方法。 （巧　最浅部エピタキシャル層がＩｎＰで、解離圧の低
い■−Ｖ族化合物半導体層がＧａＡｓでなる特許請求の
範囲第１項に記載の化合物半導体の製造方法。(1) After growing the shallowest epitaxial layer on the Ill-V group compound semiconductor substrate by a liquid phase method using indium as a solvent, the layer is covered with the shallowest epitaxial layer and has a lower dissociation pressure than that of the same layer. The first step for forming the ■-■ group compound semiconductor layer.
and a second step of etching away the l1l-v group compound semiconductor layer having a low dissociation pressure. (Takumi) The method for manufacturing a compound semiconductor according to claim 1, wherein the shallowest epitaxial layer is made of InP and the ■-V group compound semiconductor layer having a low dissociation pressure is made of GaAs.
JP451283A 1983-01-14 1983-01-14 Manufacture of compound semiconductor Pending JPS59129420A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP451283A JPS59129420A (en) 1983-01-14 1983-01-14 Manufacture of compound semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP451283A JPS59129420A (en) 1983-01-14 1983-01-14 Manufacture of compound semiconductor

Publications (1)

Publication Number Publication Date
JPS59129420A true JPS59129420A (en) 1984-07-25

Family

ID=11586101

Family Applications (1)

Application Number Title Priority Date Filing Date
JP451283A Pending JPS59129420A (en) 1983-01-14 1983-01-14 Manufacture of compound semiconductor

Country Status (1)

Country Link
JP (1) JPS59129420A (en)

Similar Documents

Publication Publication Date Title
JPH0484418A (en) Method of heteroepitaxial development of iii-v group compound semiconductor for different types of substrates
CA1234036A (en) Lpe growth on group iii-v compound semiconductor substrates containing phosphorus
JPS59129420A (en) Manufacture of compound semiconductor
Mahajan et al. Manifestations of melt‐carry‐over in InP and InGaAsP layers grown by liquid phase epitaxy
JPS54152879A (en) Structure of semiconductor laser element and its manufacture
JPS6223191A (en) Manufacture of ridge type semiconductor laser device
JP2705016B2 (en) InP-based compound semiconductor device
JPH0242771A (en) Light-emitting semiconductor element substrate and manufacture thereof
JP3609840B2 (en) Manufacturing method of semiconductor light emitting device
JPH0310222B2 (en)
JPS625330B2 (en)
JPH03180025A (en) Manufacture of semiconductor substrate
JPH02215169A (en) Semiconductor device
JPH02290016A (en) Manufacture of semiconductor device
JPH1012560A (en) Manufacturing of semiconductor multilayer film
JPS626336B2 (en)
JPH0351674B2 (en)
JPH04254321A (en) Liquid phase epitaxial growth method
JPH0475651B2 (en)
JPH04278522A (en) Semiconductor material having si-doped gainp cap layer
JPS6240721A (en) Liquid-phase growing method
JPS58168218A (en) Liquid phase epitaxial growth
JPS6353719B2 (en)
JPH0260209B2 (en)
JPH01244689A (en) Manufacture of semiconductor laser