JPS6290969A - Manufacture of optical integrated circuit - Google Patents

Manufacture of optical integrated circuit

Info

Publication number
JPS6290969A
JPS6290969A JP23154785A JP23154785A JPS6290969A JP S6290969 A JPS6290969 A JP S6290969A JP 23154785 A JP23154785 A JP 23154785A JP 23154785 A JP23154785 A JP 23154785A JP S6290969 A JPS6290969 A JP S6290969A
Authority
JP
Japan
Prior art keywords
layer
doped
inp
ingaasp
ingaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23154785A
Other languages
Japanese (ja)
Inventor
Masato Ishino
正人 石野
Yoichi Sasai
佐々井 洋一
Minoru Kubo
実 久保
Kenichi Matsuda
賢一 松田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP23154785A priority Critical patent/JPS6290969A/en
Publication of JPS6290969A publication Critical patent/JPS6290969A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate the influence of thermal damage by forming a protective layer of specific band gap wavelength on an active layer, removing the protective layer of an optical guide and the active layer, melting back the protective layer, and growing an intermediate layer. CONSTITUTION:A Te-doped N<+> type InP buffer layer 2, an InGaAsP active layer 3, and an InGaAsP or InGaAs protective layer 10 of lambdag=1.5-1.7mum are sequentially epitaxially grown on an S-doped N<+> type InP substrate 1. Then, with a laser A as a mask the layer 10 of an optical guide and the layer 3 are removed. The protective layer is melt back by the second epitaxial growth with the substrate, and a Zn-doped P<-> type intermediate layer 9, Zn-doped P<-> type InGaAs optical guide layer 6, a Zn-doped P<+> type InP clad layer 4, a Zn-doped P<+> type InGaAsP layer are sequentially grown. Thus, since the layer 3 is covered with the layer 10 at soaking time at high temperature in case of second LPE grown, no defect occurs in the boundary of the active layers.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は集積化外部共振器型レーザ(MEC−LD) 
やDBl(−LDさらにはモノリシック光スイッチ一体
化半導体レーザ等の基本構造となる光集積回路(光導波
路一体化半導体レーザ)の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to an integrated external cavity laser (MEC-LD).
The present invention relates to a method of manufacturing an optical integrated circuit (semiconductor laser integrated with an optical waveguide), which is the basic structure of a semiconductor laser integrated with a monolithic optical switch, etc.

従来の技術 光導波路と半導体レーザを同一基板上に化ノリシックに
結合する技術は上述のMl!:C−LDやDBR−LD
、さらにはモノリシクク光スイッチ一体化半導体レーザ
等の光集積回路形成に必要不可欠である。これまで、こ
の結合技術は主にDBR−LDの開発の中で進められて
きた。この中で1986年に東工大が発表した Bun
die −Integvated −Guide  (
BIG)型ど呼ばれるDBR−LDは素子がプレーナ構
造でかつ最適条件化で97%もの結合効率が得られ、他
の構造に比べて最も期待できる構造である。この素子の
構造断面図を第2図に示す。ここで1はSドープのn+
−InP基板、2はTeドープのn+−InPバッファ
層、3はλg=1.3μ@のInG2LAsP活性層、
4ばZnドープのp−InPクラッド層、6はZnドー
プのp −InGlLAsP  :17タクト層、6は
λg=1.1 fi@でZnドープのp  −InGa
AsP  mlンタクト層、さらに9はZnドープのp
−−InP中間層である。
Conventional technology The technology for chemically coupling an optical waveguide and a semiconductor laser on the same substrate is the above-mentioned Ml! :C-LD or DBR-LD
Furthermore, it is indispensable for the formation of optical integrated circuits such as semiconductor lasers integrated with monolithic optical switches. Until now, this coupling technology has been advanced mainly in the development of DBR-LD. Among these, Bun published by Tokyo Tech in 1986
die -Integrated -Guide (
The DBR-LD (BIG) type has a planar structure and can achieve a coupling efficiency of 97% under optimal conditions, making it the most promising structure compared to other structures. A cross-sectional view of the structure of this element is shown in FIG. Here 1 is S-doped n+
-InP substrate, 2 is Te-doped n+-InP buffer layer, 3 is InG2LAsP active layer with λg = 1.3μ @,
4 is a Zn-doped p-InP cladding layer, 6 is a Zn-doped p-InGlLAsP:17 tact layer, and 6 is a Zn-doped p-InGa with λg=1.1 fi@.
AsP ml contact layer, plus 9 Zn-doped p
--InP intermediate layer.

この構造の特徴はレーザー邦人において活性層3と光導
波層6の間に薄いp−−InP 中間層9が存在し、光
導波層6とp  −InPクラッド層4がレーザー邦人
と光導波部Bで共通の層となっている弘である。この構
造の液相成長法(LPIC法)での作製法を第3図に示
す。まず1回目の成長としてSドープn−InP基板1
上にToドープn+−InPバッファ層2、λg=1.
3μmのI nGaムsP活性層3を膜厚0,16μm
1さらに。、1μmの膜厚のZn ドープのp −In
P 中間層まで成長する(第3図(2L) )。次にレ
ーザー邦人をマスクして中間層9、活性層3を選択エッ
チャントで除去する(第3図(b))。マスクを除去し
たのち、2回目の成長として、λg=1.1μmのZn
ドープp −InGaAsP光導波層6(膜厚0.3μ
m)、Znドープのp −InPクラッド層4、λg=
1.1μmのInG&人SP:I77タクトを順次成長
する(第3図(C))。このように□この構造ではほと
んど完全に表面を平坦化することができ(プレーナ構造
)、以後の埋込みエピタキシャル成長やその他の電流狭
搾、光の三次元閉じ込め、および電極形成や配線等のプ
ロセスが非常に容易に行なうことができる。またこの場
合。
The feature of this structure is that a thin p--InP intermediate layer 9 exists between the active layer 3 and the optical waveguide layer 6 in the Japanese laser, and the optical waveguide layer 6 and the p-InP cladding layer 4 are in the Japanese laser and the optical waveguide B. This is Hiroshi, who is a common layer. A method for manufacturing this structure using the liquid phase epitaxy method (LPIC method) is shown in FIG. First, as the first growth, an S-doped n-InP substrate 1
Above is a To-doped n+-InP buffer layer 2, λg=1.
3 μm InGamsP active layer 3 with a film thickness of 0.16 μm
1 more. , Zn-doped p-In with a film thickness of 1 μm
P grows to the intermediate layer (Figure 3 (2L)). Next, the intermediate layer 9 and active layer 3 are removed using a selective etchant using a laser mask (FIG. 3(b)). After removing the mask, Zn with λg = 1.1 μm was grown for the second time.
Doped p-InGaAsP optical waveguide layer 6 (film thickness 0.3μ
m), Zn-doped p-InP cladding layer 4, λg=
A 1.1 μm InG & Human SP:I77 tact was sequentially grown (Figure 3(C)). In this way, the surface can be almost completely flattened (planar structure), and subsequent processes such as buried epitaxial growth, other current confinement, three-dimensional confinement of light, and electrode formation and wiring are extremely difficult. can be easily carried out. Also in this case.

レーザー邦人と光導波部Bの結合効率は97%もの値が
得られ、結合部でのロスはほとんど無視できる。
The coupling efficiency between the Japanese laser and the optical waveguide section B was as high as 97%, and the loss at the coupling section was almost negligible.

発明が解決しようとする問題点 しかしながら、この製造法では2回目のLPE成長前の
高温(600℃以上)でのメルトの溶がし込み時に、I
nP中間層9が露出しており、熱散傷の影響を受けやす
い。というのは、Pは650℃以上の高温になると解離
しやす(InPには多数のガスビットが形成され、この
ピットの深さは数ミクロンにも及ぶ。rnPカバーやP
H,導入により、この熱損傷は抑えられるが、本質的に
は解決されない。またGaムSカバーを用いて熱損傷を
防ぐ方法もあるがこの場合は表面に変質層ができてしま
う。本構造では InP中間層は0.1μmもしくはそ
れ以下でなければならないので、このようなInP O
熱損傷の影響はInP中間層/InG&ムsP活性層界
面にまで及び、欠陥導入による発光効率の低下となり、
レーザーのしきい値の上昇等特性に悪影響を及ぼすこと
になる。
Problems to be Solved by the Invention However, in this manufacturing method, I
The nP intermediate layer 9 is exposed and is susceptible to thermal damage. This is because P easily dissociates at high temperatures of 650°C or higher (many gas bits are formed in InP, and the depth of these pits is several microns.rnP cover and P
Although the introduction of H can suppress this thermal damage, it does not essentially solve it. There is also a method of preventing heat damage by using a Ga-MuS cover, but in this case, an altered layer is formed on the surface. In this structure, the InP intermediate layer must be 0.1 μm or less, so such InP O
The influence of thermal damage extends to the InP intermediate layer/InG&MusP active layer interface, resulting in a decrease in luminous efficiency due to the introduction of defects.
This will adversely affect the characteristics of the laser, such as an increase in the threshold value.

このように従来のBIG構造の製造法では良好なLD特
性の素子を得にくいという問題があった。
As described above, the conventional manufacturing method of the BIG structure has the problem that it is difficult to obtain an element with good LD characteristics.

問題点を解決するだめの手段 本発明は上述の問題慨を克服すべく、1回目のエピタキ
シャル成長でInGa人sP活性層上にバンドギャップ
波長λg=1.5μm〜1.7μmのInGaAsP 
もしくは’ InGaAs 保護層を形成し、先導波路
部の保護層および活性層を除去したのち、2回目の液相
エピタキシャル成長で保護層を選択的にメルトバックす
るとともに、InPもしくはレーザー光に対して透明な
組成のInGaAs P中間層、同じく透明なInGa
ムsP光導波層、InPクラッド層、rnGaムSPコ
ンタクト層を順次成長するという製造法である。
Means for Solving the Problems The present invention aims to overcome the above-mentioned problems by forming an InGaAsP layer with a bandgap wavelength λg of 1.5 μm to 1.7 μm on the InGaAsP active layer in the first epitaxial growth.
Or, after forming an InGaAs protective layer and removing the protective layer and active layer of the leading waveguide, the protective layer is selectively melted back in the second liquid phase epitaxial growth, and InP or a transparent layer to laser light is grown. InGaAs P interlayer of composition, also transparent InGa
This is a manufacturing method in which a Mu-sP optical waveguide layer, an InP cladding layer, and an rnGa-mu SP contact layer are sequentially grown.

作用 上述の手段により、2回目の成長前の高温での熱損傷の
影響のない良好なLD特性を有する光集積回路(先導波
路一体化半導体レーザー)が容易に得られるものである
Effect: By the means described above, it is possible to easily obtain an optical integrated circuit (semiconductor laser integrated with a guided waveguide) having good LD characteristics without being affected by thermal damage at high temperatures before the second growth.

実施例 以下、本発明の一実施例におけるBI(、構造の半導体
レーザーの製造法を述べる。第1図はこの製造法を示す
工程図である。まずSドープのn+−InP基板1上に
Teドープのn+−InPバッファ層2を厚さ5 μm
、 λg=1.3μmのInGaAsP活性層3を0.
1s μ71.  InGaAs保護層1oを023m
を順次液相もしくは気相成長法でエビタキシャル成長す
る(第1図(’a−) )。次にレーザー邦人をマスク
して光導波部のI nGaAa保護層10、In(rl
LAsP活性層3を選択エッチャントで除去する(第1
図(b))。この微少の段差を有するエピタキシャル基
板を用い、2回目のエピタキシャル成長で、Znドープ
p −InP中間層9を0.1 μm 。
EXAMPLE Below, a method for manufacturing a semiconductor laser having a BI structure in an example of the present invention will be described. FIG. 1 is a process diagram showing this manufacturing method. First, Te Doped n+-InP buffer layer 2 with a thickness of 5 μm
, the InGaAsP active layer 3 with λg=1.3 μm was formed with a thickness of 0.0 μm.
1s μ71. InGaAs protective layer 1o 023m
are sequentially grown epitaxially using a liquid phase or vapor phase growth method (Fig. 1('a-)). Next, the laser beam is masked and the InGaAa protective layer 10, In(rl
LAsP active layer 3 is removed using a selective etchant (first
Figure (b)). Using this epitaxial substrate having minute steps, a Zn-doped p-InP intermediate layer 9 was grown to a thickness of 0.1 μm in a second epitaxial growth.

λg = 1.1 μmのZnドープp −InGaA
sP光導波層6、Znドープp −InPクラッド層4
を2μ@、Znドープp −InGaAsP層を0.5
711を順次液相成長法により成長する(第1図(C)
)。
Zn-doped p-InGaA with λg = 1.1 μm
sP optical waveguide layer 6, Zn-doped p-InP cladding layer 4
2 μ@, Zn-doped p-InGaAsP layer 0.5
711 is grown sequentially by liquid phase growth method (Fig. 1(C)
).

InGaAs保護層10はp−−I nP中間層9を成
長する際に瞬時にメルトバックされて除去される。
The InGaAs protective layer 10 is instantaneously melted back and removed when the p--InP intermediate layer 9 is grown.

このInGaAs保護層1oはInGaAsの代わりに
1.7 μ@ ≧λg≧1.5 μmの組成のI nG
aAs Pを用いてもよい。またp −InP中間層9
ばInPの代わりに1.1μm≧λg≧0.92μmの
InGaLASPを用いてもよい。
This InGaAs protective layer 1o is made of InG having a composition of 1.7 μm ≧λg≧1.5 μm instead of InGaAs.
aAsP may also be used. In addition, the p-InP intermediate layer 9
For example, InGaLASP with 1.1 μm≧λg≧0.92 μm may be used instead of InP.

このような製造法で作製した素子は、2回目のLPE成
長の際の高温でのソーク時にInGaAsPnGaAs
保護層3s保護層10で覆われているので、活性層界面
に欠陥が導入されて半導体レーザーの発光効率を低下さ
せることはない。というのはInPと違ってInGaA
sおよびλgの大きいInGaAsP構成長温度付近(
650〜670℃)でほとんど熱損傷を受けないからで
ある。このように本実施例の製造法で作製したBIG構
造光集積回路は良好なレーザー特性を示すとともに、プ
レーナ構造でかつ高い結合効率を有することができる。
The device fabricated using this manufacturing method is made of InGaAsPnGaAs during the high temperature soak during the second LPE growth.
Since the protective layer 3s is covered with the protective layer 10, defects will not be introduced to the active layer interface and reduce the luminous efficiency of the semiconductor laser. This is because unlike InP, InGaA
Near the InGaAsP structure length temperature where s and λg are large (
This is because there is almost no thermal damage at temperatures of 650 to 670°C. As described above, the BIG structure optical integrated circuit manufactured by the manufacturing method of this example exhibits good laser characteristics, has a planar structure, and can have high coupling efficiency.

なお、本実施例においては基板としてn型を用いたがp
型基板を用いたときも同様である。まだ活性層のInG
aAsPの組成も1.3μmに限定されるものではない
In this example, an n-type substrate was used, but a p-type substrate was used.
The same applies when a mold substrate is used. InG still in active layer
The composition of aAsP is also not limited to 1.3 μm.

発明の効果 以上のように、本発明はレーザー部がInP基板、In
Pnツバ2フフ 間層、InGaAs P光導波層、InPクラッド層、
InGaAs Pコンタクト層で構成され、光導波部が
InP基板、InPバフ77層、InGaAs P光導
波層、InPクラッド層、I nGaAs Pコンタク
ト層で「構成された光集積回路を製造するに際し、1回
目の成長で基板上にバッファ層、活性層さらに2μm1
、5〜1.7μmのI nGaムsPもしくはInCa
As保護層を成長したのち、光導波部における保護層と
活性層を除去し、2回目の成長で保護層をメルトバック
するとともに、先導波層、クラッド層、コンタクト層を
順次成長することにより製造するもので、活性層界面で
の欠陥が導入されない良好な半導体レーザー特性を示す
とともにプレーナ構造で高い結合効率を有する光集積回
路を得ることができ、これを基本とする種々のデバイス
で長幼な特性を得ることができる。
Effects of the Invention As described above, in the present invention, the laser section is made of an InP substrate, an InP substrate, and an InP substrate.
Pn flange 2 fluff layer, InGaAs P optical waveguide layer, InP cladding layer,
When manufacturing an optical integrated circuit composed of an InGaAs P contact layer and an optical waveguide section composed of an InP substrate, an InP buff 77 layer, an InGaAs P optical waveguide layer, an InP cladding layer, and an InGaAs P contact layer, the first By growing a buffer layer and an active layer on the substrate, a further 2 μm1
, 5-1.7 μm InGamusP or InCa
After growing the As protective layer, the protective layer and active layer in the optical waveguide are removed, the protective layer is melted back in the second growth, and the guiding wave layer, cladding layer, and contact layer are sequentially grown. As a result, it is possible to obtain an optical integrated circuit that exhibits good semiconductor laser characteristics with no defects introduced at the active layer interface and has a planar structure with high coupling efficiency, and various devices based on this can have long-lasting characteristics. can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例によるBl(、構造MECレ
ーザーの製造方法を示す工程図、第2図は従来のBIG
構造MECレーザーの断面構造図、第3図は同従来のレ
ーザーの製造方法を示す工程図である。 1 ・=−Sドープn−InP基板、3−・= InG
aAsP活性層、6 −−− −・− Z nドープp
 −InGaASP光導波層、9・・・・・・Znドー
プp−−InP中間層、10・・・・・I nGaAs
保護層、A・・・・・レーザー部、B・・・・・・光導
波部。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名i1
図 (cL) 第2図
FIG. 1 is a process diagram showing a method for manufacturing a Bl(, structured MEC laser) according to an embodiment of the present invention, and FIG.
FIG. 3 is a cross-sectional structural diagram of a structured MEC laser, and is a process diagram showing a method of manufacturing the conventional laser. 1.=-S-doped n-InP substrate, 3-.=InG
aAsP active layer, 6 --- --- Z n-doped p
-InGaASP optical waveguide layer, 9...Zn-doped p--InP intermediate layer, 10...InGaAs
Protective layer, A: laser section, B: optical waveguide section. Name of agent: Patent attorney Toshio Nakao and 1 other person i1
Figure (cL) Figure 2

Claims (1)

【特許請求の範囲】[Claims] 1素子内にレーザー部と光導波部をモノリシックに有し
、前記レーザー部はInP基板、InGaAsP活性層
、InPもしくはInGaAsP中間層、InGaAs
光導波層、InPクラッド層、InGaAsPコンタク
層で構成され、前記光導波部は前記InP基板、前記I
nGaAsP光導波層、前記InPクラッド層、前記I
nGaAsPコンタクト層で構成される構造の光集積回
路を製造するに際し、まず液相もしくは気相エピタキシ
ャル成長法で前記InP基板上に、前記InGaAsP
活性層、さらにバンドギャップ波長(λg)が1.5〜
1.7μmのInGaAsPもしくはInGaAs保護
層を形成し、前記光導波部の前記保護層および活性層を
選択的に除去した後、液相エピタキシャル成長法で前記
InPもしくはInGaAsi中間層を成長するメルト
を用いて前記保護層を選択的にメルトバックするととも
に、前記中間層を形成し、引き続き、前記InGaAs
P光導波層、前記InPクラッド層、前記InGaAs
Pコンタクト層を順次形成することを特徴とする光集積
回路の製造方法。
One element monolithically has a laser section and an optical waveguide section, and the laser section is made of an InP substrate, an InGaAsP active layer, an InP or InGaAsP intermediate layer, an InGaAs
The optical waveguide is composed of an optical waveguide layer, an InP cladding layer, and an InGaAsP contact layer.
nGaAsP optical waveguide layer, the InP cladding layer, the I
When manufacturing an optical integrated circuit having a structure composed of an nGaAsP contact layer, the InGaAsP layer is first grown on the InP substrate by liquid phase or vapor phase epitaxial growth.
The active layer further has a bandgap wavelength (λg) of 1.5~
After forming a 1.7 μm InGaAsP or InGaAs protective layer and selectively removing the protective layer and the active layer of the optical waveguide, the InP or InGaAs intermediate layer is grown by a liquid phase epitaxial growth method using a melt. The protective layer is selectively melted back, the intermediate layer is formed, and the InGaAs
P optical waveguide layer, the InP cladding layer, the InGaAs
A method for manufacturing an optical integrated circuit, comprising sequentially forming P contact layers.
JP23154785A 1985-10-17 1985-10-17 Manufacture of optical integrated circuit Pending JPS6290969A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23154785A JPS6290969A (en) 1985-10-17 1985-10-17 Manufacture of optical integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23154785A JPS6290969A (en) 1985-10-17 1985-10-17 Manufacture of optical integrated circuit

Publications (1)

Publication Number Publication Date
JPS6290969A true JPS6290969A (en) 1987-04-25

Family

ID=16925202

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23154785A Pending JPS6290969A (en) 1985-10-17 1985-10-17 Manufacture of optical integrated circuit

Country Status (1)

Country Link
JP (1) JPS6290969A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
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JP2010157691A (en) * 2008-12-02 2010-07-15 Opnext Japan Inc Optical semiconductor device
JP2018018972A (en) * 2016-07-28 2018-02-01 三菱電機株式会社 Optical semiconductor device
WO2020042137A1 (en) * 2018-08-31 2020-03-05 华为技术有限公司 Optical integrated chip

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010157691A (en) * 2008-12-02 2010-07-15 Opnext Japan Inc Optical semiconductor device
JP2018018972A (en) * 2016-07-28 2018-02-01 三菱電機株式会社 Optical semiconductor device
US10374388B2 (en) 2016-07-28 2019-08-06 Mitsubishi Electric Corporation Optical semiconductor device
WO2020042137A1 (en) * 2018-08-31 2020-03-05 华为技术有限公司 Optical integrated chip
CN111971861A (en) * 2018-08-31 2020-11-20 华为技术有限公司 Optical integrated chip
CN111971861B (en) * 2018-08-31 2024-01-30 华为技术有限公司 Optical integrated chip

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