CN111971861B - Optical integrated chip - Google Patents
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- CN111971861B CN111971861B CN201880092318.3A CN201880092318A CN111971861B CN 111971861 B CN111971861 B CN 111971861B CN 201880092318 A CN201880092318 A CN 201880092318A CN 111971861 B CN111971861 B CN 111971861B
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- 230000003287 optical effect Effects 0.000 title claims abstract description 159
- 239000010410 layer Substances 0.000 claims abstract description 419
- 239000004065 semiconductor Substances 0.000 claims abstract description 106
- 239000011241 protective layer Substances 0.000 claims abstract description 91
- 239000000463 material Substances 0.000 claims abstract description 83
- 238000005253 cladding Methods 0.000 claims description 64
- 239000000758 substrate Substances 0.000 claims description 23
- 239000011247 coating layer Substances 0.000 claims description 21
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 17
- 229910052782 aluminium Inorganic materials 0.000 claims description 17
- 238000000926 separation method Methods 0.000 claims description 16
- 230000000670 limiting effect Effects 0.000 claims description 11
- 230000005540 biological transmission Effects 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 5
- 230000000903 blocking effect Effects 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 210000001503 joint Anatomy 0.000 abstract description 44
- 239000013078 crystal Substances 0.000 abstract description 39
- 230000007547 defect Effects 0.000 abstract description 39
- 238000000034 method Methods 0.000 abstract description 32
- 230000008569 process Effects 0.000 abstract description 29
- 230000002829 reductive effect Effects 0.000 abstract description 27
- 230000007774 longterm Effects 0.000 abstract description 17
- 230000006866 deterioration Effects 0.000 abstract description 13
- 230000000694 effects Effects 0.000 abstract description 4
- 238000005530 etching Methods 0.000 description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 230000009471 action Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000004886 process control Methods 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 230000002401 inhibitory effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000011149 active material Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
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- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Optics & Photonics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Lasers (AREA)
Abstract
The application provides an optical integrated chip. In the optical integrated chip, a protective layer (35) is additionally arranged on an active layer area near a butt joint interface of an active layer (33) and a non-active layer (34). The forbidden band width of the protective layer is larger than that of the active layer, so that the current density of the active layer adjacent to the butt joint interface is reduced due to the effect of the protective layer, thereby reducing the influence of high current density in the working process of the optical integrated chip on the active layer adjacent to the butt joint interface, and further reducing the possibility of continuous growth of crystal defects of materials of the active layer adjacent to the butt joint interface in the optical integrated chip. Therefore, the addition of the protective layer reduces the possibility of continuous growth of crystal defects of the active layer material at the butt joint interface, reduces the risk of gradual deterioration and even abrupt failure of the performance of the semiconductor optical chip in operation, and improves the long-term reliability of the semiconductor optical chip.
Description
Technical Field
The present disclosure relates to semiconductor chip technology, and more particularly, to an optical integrated chip.
Background
In the field of optical communications, semiconductor optical integrated chips are one of the most critical components.
Early semiconductor optical chips were relatively simple in structure, such as semiconductor lasers and semiconductor optical amplifiers, with only a single active layer of material, typically III-V semiconductor material, to provide gain. With the development of technology, more complex optical integrated chips have been developed, for example, materials with different forbidden bandwidths are integrated on the basis of an active layer to form other functional units, such as: integrating passive units on the active layer to obtain filters, beam splitters, wave combiners, interferometers, mode converters, column-increasing waveguide gratings, etched diffraction gratings, etc.; or integrated modulator materials are used to integrate some units with modulation functions, commonly known as electro-absorption modulators (Electro Absorption Modulator, EAM) and Mach-zehnder modulators (Mach-Zehnder interferometer Modulator, MZM).
Currently, a mature technology for integrating other functional units is usually an etching regrowth technology. Due to the complex etching, cleaning and epitaxial control processes in the process, at the interface between different types of materials, the materials typically have some crystal defects, do not exhibit a perfect crystal structure and have some lattice dislocations.
In the working process of the semiconductor optical integrated chip, a scene of high current density, high temperature or high light intensity exists, under the influence of the high current density, high temperature or high light intensity, crystal defects at the interface are likely to continue to grow, and when the crystal defects grow to a certain degree, the crystal defects can cause gradual deterioration and even sudden failure of the luminous performance of an active area, so that the semiconductor optical integrated chip has a high risk for the long-term reliability of the semiconductor optical integrated chip.
Disclosure of Invention
In view of this, embodiments of the present application provide an optical integrated chip.
In order to solve the technical problems, the application adopts the following technical scheme:
a first aspect of the present application provides an optical integrated chip comprising:
the semiconductor device comprises a substrate, a first cladding layer, a source layer, a non-active layer, a protective layer and a second cladding layer; the first coating layer is used for covering one side of the surface of the substrate; the active layer and the non-active layer are both positioned on one side of the first coating layer, which is opposite to the substrate, and the side wall of the active layer, which faces the non-active layer, and the side wall of the non-active layer, which faces the active layer, are attached; the inactive layer comprises at least one of a passive layer or a modulation layer, and the modulation layer has a modulation function; the protective layer is used for covering the surface of a first area of the active layer and is positioned on one side of the first area, which is opposite to the first coating layer, and the first area is an area, close to the non-active layer, in the active layer; the forbidden bandwidth of the material of the protective layer is larger than that of the material of the active layer; the second coating layer is used for covering the surface of the second area, which faces away from the first coating layer, the surface of the protective layer, which faces away from the first area, and the surface of the inactive layer, which faces away from the first coating layer; the second region is a region in the active layer other than the first region.
In the optical integrated chip provided in the first aspect, a protective layer is added on the active layer region near the interface between the active layer and the inactive layer. The protective layer can reduce the current density of the active layer area adjacent to the butt joint interface, so that the current density of the active layer adjacent to the butt joint interface can be reduced under the action of the protective layer in the working process of the semiconductor optical integrated chip, the influence of high temperature and high current density on the active layer adjacent to the butt joint interface in the working process of the semiconductor optical integrated chip is reduced, and the possibility that crystal defects of materials of the active layer adjacent to the butt joint interface continue to grow in the working process of the semiconductor optical integrated chip is further reduced. Therefore, the addition of the protective layer reduces the possibility of continuous growth of crystal defects of the active layer material at the butt joint interface, reduces the risk of gradual deterioration and even abrupt failure of the performance of the semiconductor optical integrated chip in operation, and improves the long-term reliability of the semiconductor optical integrated chip.
In a first possible implementation manner, the material of the protective layer is an undoped or low-doped semiconductor material, and the doping concentration of the low-doped semiconductor material is lower than 1e18cm -3 . In a first possible implementation manner, the possibility of continuous growth of crystal defects of the active layer material at the interface of the butt joint can be better reduced, and the risk of gradual deterioration or even sudden failure of the performance of the semiconductor optical integrated chip during operation is reduced.
In a second possible implementation manner, the optical refractive indexes of the first cladding layer and the second cladding layer are smaller than those of the active layer and the inactive layer, so as to limit light in the active layer and the inactive layer.
In a third possible implementation form of the first aspect as such or the first or the second possible implementation form thereof, the material of the protective layer is a group III-V compound. In a third possible implementation manner, the possibility that crystal defects of the active layer material at the butt joint interface continue to grow can be reduced better, and the risk that the performance of the semiconductor optical integrated chip is gradually deteriorated and even suddenly fails during operation is reduced.
Based on the first aspect of the present application and various possible implementations thereon, in a fourth possible implementation, a length of the protective layer along a transmission direction of light within the optical integrated chip is greater than 0 and less than or equal to 20 μm. In a fourth possible implementation manner, the possibility of continuous growth of crystal defects of the active layer material at the butt joint interface is reduced, and the risk of gradual deterioration or even abrupt failure of the performance of the semiconductor optical integrated chip in operation is reduced without affecting the performance of the active layer.
Based on the first aspect of the present application and various possible implementation manners thereon, in a fifth possible implementation manner, a thickness of the protective layer is greater than 0 and less than or equal to 1 μm. In a fifth possible implementation manner, the performance of the active layer is not affected while the possibility of continuous growth of crystal defects of the active layer material at the interface of the butt joint is reduced, and the risk of gradual deterioration or even abrupt failure of the performance of the semiconductor optical integrated chip in operation is reduced.
Based on the first aspect of the present application and the various possible implementations thereof, in a sixth possible implementation, the active layer includes a layer of aluminum-containing quantum well material. In a sixth possible implementation, the optical integrated chip and thus the high temperature characteristics of the optical integrated chip produced therefrom can be improved.
In a seventh possible implementation manner, the active layer includes a phosphorus-containing quantum well material layer according to the first aspect of the present application and any one of the first to fifth possible implementation manners. In this way, the optical integrated chip and thus the high temperature characteristics of the optical integrated chip thus manufactured can be improved.
Based on the sixth or seventh possible implementation manner of the first aspect of the present application, in an eighth possible implementation manner, the active layer further includes: at least one of the first separation confinement heterostructure layer or the second separation confinement heterostructure layer; the first separation limiting heterostructure layer is positioned on one side of the aluminum-containing quantum well material layer facing the first cladding layer; the second separation confinement heterostructure layer is located on a side of the aluminum-containing quantum well material layer toward the second cladding layer. In an eighth possible implementation manner, the gain effect of the aluminum-containing quantum well material layer can be further improved.
Based on the eighth possible implementation manner of the first aspect of the present application, in a ninth possible implementation manner, the active layer further includes: and the electron blocking layer is positioned on one side of the second separation limiting heterostructure layer, which is opposite to the aluminum-containing quantum well material layer. In a ninth possible implementation, electronic leakage can be prevented.
Based on the first aspect of the present application and its various possible implementations, in a tenth possible implementation, the material of the first cladding layer is InP or GaAs.
In an eleventh possible implementation manner, the first cladding layer includes at least one of a spot control layer, an etching barrier layer, or a hollowed-out layer. In an eleventh possible implementation, the function of the first cladding layer can be enriched to better control the manufacturing process, such as controlling the spot, controlling the etching endpoint, etc.
Based on the first aspect of the present application and various possible implementations thereof, in a twelfth possible implementation, the optical integrated chip further includes: and the cover layer is positioned in a second area of the active layer and is opposite to one side of the first cladding layer, and the second area is adjacent to the first area. In a twelfth possible implementation, process control may be better performed.
Based on the first aspect of the present application and its various possible implementation manners, in a thirteenth possible implementation manner, the optical integrated chip is a bragg reflection DBR laser chip.
Based on the first aspect of the present application and its various possible implementations, in a fourteenth possible implementation, the optical integrated chip is an optical amplifier chip.
Based on the first aspect of the application and its various possible implementations, in a fifteenth possible implementation, the optical integrated chip is an emitter array chip.
A second aspect of the present application provides a semiconductor optical integrated chip that is a bragg reflector DBR laser chip comprising a first mirror, a gain region, a phase region, and a second mirror; the first reflector is positioned in a first passive region, the gain region is positioned in a first active region, the phase region and the second reflector are positioned in a second passive region; the first passive region, the first active region and the second passive region are in butt joint in sequence; wherein at least one of a junction between the first inactive region and the first active region or a junction between the first active region and the second inactive region adopts an epitaxial structure, the epitaxial structure comprising: a substrate; a first coating layer for covering a surface side of the substrate; the active layer and the non-active layer are both positioned on one side of the first coating layer, which is opposite to the substrate, and the side wall of the active layer, which faces the non-active layer, and the side wall of the non-active layer, which faces the active layer, are attached; the inactive layer comprises at least one of a passive layer or a modulation layer, and the modulation layer has a modulation function; the protective layer is used for covering the surface of a first area of the active layer and is positioned on one side of the first area, which is opposite to the first coating layer, and the first area is an area, close to the non-active layer, in the active layer; the forbidden bandwidth of the material of the protective layer is larger than that of the material of the active layer; and a second cladding layer for covering a surface of the second region of the active layer facing away from the first cladding layer, a surface of the protective layer facing away from the first region, and a surface of the inactive layer facing away from the first cladding layer; the second region is a region in the active layer other than the first region.
In the semiconductor optical integrated chip provided in the second aspect, a protective layer is added on the active layer region near the interface of the active layer and the inactive layer. The protective layer can reduce the current density of the active layer area adjacent to the butt joint interface, so that the current density of the active layer adjacent to the butt joint interface can be reduced under the action of the protective layer in the working process of the semiconductor optical integrated chip, the influence of high temperature and high current density on the active layer adjacent to the butt joint interface in the working process of the semiconductor optical integrated chip is reduced, and the possibility that crystal defects of materials of the active layer adjacent to the butt joint interface continue to grow in the working process of the semiconductor optical integrated chip is further reduced. Therefore, the addition of the protective layer reduces the possibility of continuous growth of crystal defects of the active layer material at the butt joint interface, reduces the risk of gradual deterioration and even abrupt failure of the performance of the semiconductor optical integrated chip in operation, and improves the long-term reliability of the semiconductor optical integrated chip.
Based on the second aspect of the present application, in a first possible implementation manner, the laser chip further includes: a first semiconductor optical amplifier and a second semiconductor optical amplifier; wherein the first semiconductor optical amplifier is located on the second active region and the second semiconductor optical amplifier is located on the third active region; the second active region, the first inactive region, the first active region, the second inactive region and the third active region are in butt joint in sequence; wherein the epitaxial structure is employed at least one of at a junction between the second active region and the first inactive region or at a junction between the third active region and the third inactive region.
A third aspect of the present application provides a semiconductor optical integrated chip that is a laser chip that includes a distributed feedback laser unit, a modulator, and a semiconductor optical amplifier; wherein the distributed feedback laser unit is located on a fourth active region, the modulator is located on a fourth passive region, and the semiconductor optical amplifier is located on a fifth active region; the fourth active region, the fourth inactive region and the fifth active region are in butt joint in sequence; wherein an epitaxial structure is employed at least one of at a junction between the fourth active region and the fourth inactive region or at a junction between the fourth inactive region and the fifth active region, the epitaxial structure comprising: a substrate; a first coating layer for covering a surface side of the substrate; the active layer and the non-active layer are both positioned on one side of the first coating layer, which is opposite to the substrate, and the side wall of the active layer, which faces the non-active layer, and the side wall of the non-active layer, which faces the active layer, are attached; the inactive layer comprises at least one of a passive layer or a modulation layer, and the modulation layer has a modulation function; the protective layer is used for covering the surface of a first area of the active layer and is positioned on one side of the first area, which is opposite to the first coating layer, and the first area is an area, close to the non-active layer, in the active layer; the forbidden bandwidth of the material of the protective layer is larger than that of the material of the active layer; and a second cladding layer for covering a surface of the second region of the active layer facing away from the first cladding layer, a surface of the protective layer facing away from the first region, and a surface of the inactive layer facing away from the first cladding layer; the second region is a region in the active layer other than the first region.
In the semiconductor optical integrated chip provided in the third aspect, a protective layer is added on the active layer region near the interface of the active layer and the inactive layer. The protective layer can reduce the current density of the active layer area adjacent to the butt joint interface, so that the current density of the active layer adjacent to the butt joint interface can be reduced under the action of the protective layer in the working process of the semiconductor optical integrated chip, the influence of high temperature and high current density on the active layer adjacent to the butt joint interface in the working process of the semiconductor optical integrated chip is reduced, and the possibility that crystal defects of materials of the active layer adjacent to the butt joint interface continue to grow in the working process of the semiconductor optical integrated chip is further reduced. Therefore, the addition of the protective layer reduces the possibility of continuous growth of crystal defects of the active layer material at the butt joint interface, reduces the risk of gradual deterioration and even abrupt failure of the performance of the semiconductor optical integrated chip in operation, and improves the long-term reliability of the semiconductor optical integrated chip.
A fourth aspect of the present application provides a semiconductor optical integrated chip, which is an optical amplifier chip, where the optical amplifier chip includes a laser unit group, a modulator group, a combiner, and a semiconductor optical amplifier, the laser unit group includes N lasers, the modulator group includes N modulators, and N is a positive integer; the laser unit group is positioned on a sixth active region, the sixth active region comprises N sub-active regions, and each path of laser is positioned on each sub-active region; the modulator group is positioned on a fifth inactive area, the fifth inactive area comprises N sub-inactive areas, and each modulator is positioned on each sub-inactive area; the wave combiner is positioned on the sixth passive area, and the semiconductor optical amplifier is positioned on the seventh active area; the sixth active region, the fifth inactive region, the sixth inactive region and the seventh active region are sequentially butted, and one of the sub-active regions is butted with one of the sub-inactive regions; at least one of a junction between each sub-active region and a sub-inactive region or a junction between the sixth inactive region and the seventh active region adopts an epitaxial structure, the epitaxial structure comprising: a substrate; a first coating layer for covering a surface side of the substrate; the active layer and the non-active layer are both positioned on one side of the first coating layer, which is opposite to the substrate, and the side wall of the active layer, which faces the non-active layer, and the side wall of the non-active layer, which faces the active layer, are attached; the inactive layer comprises at least one of a passive layer or a modulation layer, and the modulation layer has a modulation function; the protective layer is used for covering the surface of a first area of the active layer and is positioned on one side of the first area, which is opposite to the first coating layer, and the first area is an area, close to the non-active layer, in the active layer; the forbidden bandwidth of the material of the protective layer is larger than that of the material of the active layer; and a second cladding layer for covering a surface of the second region of the active layer facing away from the first cladding layer, a surface of the protective layer facing away from the first region, and a surface of the inactive layer facing away from the first cladding layer; the second region is a region in the active layer other than the first region.
In the semiconductor optical integrated chip provided in the fourth aspect, a protective layer is added on the active layer region near the interface of the active layer and the inactive layer. The protective layer can reduce the current density of the active layer area adjacent to the butt joint interface, so that the current density of the active layer adjacent to the butt joint interface can be reduced under the action of the protective layer in the working process of the semiconductor optical integrated chip, the influence of high temperature and high current density on the active layer adjacent to the butt joint interface in the working process of the semiconductor optical integrated chip is reduced, and the possibility that crystal defects of materials of the active layer adjacent to the butt joint interface continue to grow in the working process of the semiconductor optical integrated chip is further reduced. Therefore, the addition of the protective layer reduces the possibility of continuous growth of crystal defects of the active layer material at the butt joint interface, reduces the risk of gradual deterioration and even abrupt failure of the performance of the semiconductor optical integrated chip in operation, and improves the long-term reliability of the semiconductor optical integrated chip.
Drawings
In order that the detailed description of the present application may be clearly understood, a brief description of the drawings will be provided below. It is apparent that these figures are only some of the embodiments of the present application.
FIG. 1 is a schematic top view of an optical integrated chip of the prior art;
FIGS. 2 (1) to 2 (4) are schematic cross-sectional views along A-A' in FIG. 1 corresponding to a series of processes for fabricating the optical integrated chip shown in FIG. 1;
FIG. 3 is a schematic cross-sectional view of an optical integrated chip provided in the present application;
FIG. 4 is a schematic diagram of a semiconductor optical integrated chip provided in the present application;
FIG. 5 is a schematic diagram of another semiconductor optical integrated chip provided herein;
FIG. 6 is a schematic diagram of a semiconductor optical integrated chip according to still another embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of still another semiconductor optical integrated chip provided in the present application.
Detailed Description
As described in the background section, the semiconductor optical integrated chip with more abundant functions will integrate other functional units, such as passive units or units with modulation function, on the basis of the active layer. Techniques for integrating new functionality can have some crystal defects at the interface of the interface between different types of materials of the semiconductor optical integrated chip.
In the working process of the semiconductor optical integrated chip, working scenes with high current density, high temperature or high light intensity exist, under the influence of the high current density, the high temperature or the high light intensity, crystal defects at the butt joint interface have the possibility of continuous growth, and when the crystal defects grow to a certain degree, the crystal defects can cause gradual deterioration and even abrupt failure of the performance of the semiconductor optical integrated chip, so that the semiconductor optical integrated chip has a high risk for the long-term reliability of the semiconductor optical integrated chip.
Note that the semiconductor optical integrated chips described in the embodiments of the present application may include, but are not limited to, semiconductor laser integrated chips and semiconductor optical amplifier integrated chips.
As an example, fig. 1 shows a top view of an optical integrated chip applied to a semiconductor laser. In the optical integrated chip, the active optical waveguide 11 and the passive optical waveguide 12 are butt-jointed and integrated together. Wherein an electrode 13 is provided on the surface of the active optical waveguide 11.
The process of fabricating the optical integrated chip shown in fig. 1 is as follows:
first, a first clad layer 21, an active layer 22 and a cap layer 23 are sequentially formed on a substrate 20, and the corresponding cross-sectional structure is schematically shown in fig. 2 (1). In the industry, the first clad layer 21 is generally referred to as a lower clad layer.
Then, the cap layer 23 and the active layer 22 are etched away in the area where the non-active layer needs to be grown, exposing the first cladding layer 21 to form a cross-sectional structure as described in fig. 2 (2);
then, an inactive layer 24 is epitaxially formed on the exposed first clad layer 21, and the inactive layer 24 is abutted against the active layer 22 to form a cross-sectional structure as shown in fig. 2 (3);
finally, a second cladding layer 25 is formed over the active layer 22 and the inactive layer 24, forming a cross-sectional structure as shown in fig. 2 (4). In the industry, the second cladding layer 25 is generally referred to as an upper cladding layer.
Wherein the optical refractive index of the first cladding layer 21 and the second cladding layer 25 are smaller than the optical refractive index of the active layer 22 and the inactive layer 24 to confine light in the active layer 22 and the inactive layer 24.
The active layer 22 is for providing gain;
the cap layer 23 is used for process control.
In the above-mentioned manufacturing process, there are complicated etching, cleaning and epitaxy control processes due to the requirement of forming the non-active layer 24, and there are some crystal defects at the position where the active layer 22 is adjacent to the interface and at the position where the non-active layer 24 is adjacent to the interface due to the different materials of the active layer 22 and the non-active layer 24. It should be noted that the side of the active layer 22 facing the inactive layer 24 and the side of the inactive layer 24 facing the active layer 22 are in contact, or otherwise in abutting contact. In this application, the side of the active layer 22 facing the inactive layer 24 may be referred to as the interface of the active layer 22, and similarly, the side of the inactive layer 24 facing the active layer 22 may be referred to as the interface of the inactive layer 24, and the interface of the active layer 22 and the interface of the inactive layer 24 may form the interface after contacting. These crystal defects continue to grow around when the semiconductor laser is operated in a high-current, high-temperature or high-light-intensity environment, and the crystal defects in the non-active layer 24 have little influence on the performance of the laser after growth, but the crystal defects in the active layer 22 (which may be defects in the quantum well within the active layer 22) reduce the light-emitting efficiency of the laser after growth, and when the crystal defects in the active layer 24 grow to a certain extent, the gradual deterioration or even abrupt failure of the performance of the semiconductor laser is caused, which has a great risk for the long-term reliability of the semiconductor laser.
In order to reduce the continued growth of crystal defects in the active layer adjacent to the interface, and thus improve the long-term reliability of the semiconductor optical device, the present application provides an external optical integrated chip in which a protective layer is added to the active layer in the region adjacent to the interface (see fig. 3, region I is the region adjacent to the interface in the active layer 33). The protective layer can reduce the current density in the area adjacent to the butt joint interface in the active layer, so that the current density in the area adjacent to the butt joint interface in the active layer can be reduced due to the effect of the protective layer in the working process of the semiconductor optical integrated chip, the influence of high current density in the working process of the semiconductor optical integrated chip on the area adjacent to the butt joint interface in the active layer is reduced, and the possibility that crystal defects in the area adjacent to the butt joint interface in the active layer continue to grow in the working process of the semiconductor optical integrated chip is further reduced. Therefore, the addition of the protective layer reduces the possibility of continuous growth of crystal defects in the area adjacent to the butt joint interface in the active layer, reduces the risk of gradual deterioration and even abrupt failure of the performance of the semiconductor optical integrated chip in operation, and improves the long-term reliability of the semiconductor optical integrated chip.
The following describes in detail the specific implementation manner of the optical integrated chip applied to the semiconductor optical integrated chip provided in the present application with reference to the accompanying drawings.
Referring to fig. 3, an optical integrated chip applied to a semiconductor optical integrated chip according to an embodiment of the present application includes:
a base 31;
a first clad layer 32 for covering a surface side of the substrate 31;
the active layer 33 and the inactive layer 34 are both located on the side of the first cladding layer 32 facing away from the substrate 31, and the side wall of the active layer 33 facing the inactive layer 34 is attached to the side wall of the inactive layer 34 facing the active layer 33. Note that the thickness of the active layer 33 and the thickness of the inactive layer 34 may be non-uniform.
A protective layer 35, configured to cover a surface of the first region I of the active layer 33, and located on a side of the first region I facing away from the first cladding layer 32, where the first region I is a region close to the non-active layer 34 in the active layer 33; the forbidden bandwidth of the material of the protective layer 35 is larger than that of the material of the active layer, so as to reduce the current density of the first region I of the active layer 33;
and a second cladding layer 36 for covering a surface of the second region II of the active layer 33 facing away from the first cladding layer 32, a surface of the protective layer 35 facing away from the first region I, and a surface of the inactive layer 34 facing away from the first cladding layer 32; the second region II is a region other than the first region I in the active layer 33.
In addition, in order to achieve better control over the process, the optical integrated chip may further include:
the cap layer 37 is located in the second region II of the active layer 33 and faces away from the first cladding layer 32, and the second region II of the active layer 33 is adjacent to the first region I, so that the second region II of the active layer 33 is an active layer region away from the interface.
The first cladding layer 32 is generally referred to as a lower cladding layer, and the second cladding layer 36 is generally referred to as an upper cladding layer. The first cladding layer 32 and the second cladding layer 36 are typically composed of InP or GaAs. Cap layer 37 may be a III-V compound.
The specific structure of the semiconductor laser may also be described from the orientation or positional relationship shown in fig. 3 for a clearer understanding of the specific implementation provided by the embodiments of the present application. Thus, the semiconductor laser includes:
substrate 31:
a first clad layer 32 located over the substrate 31;
an active layer 33 and an inactive layer 34 located above the first clad layer 32, the active layer 33 and the inactive layer 34 being butted;
a protective layer 35 located over a first region I of the active layer 33, the first region I being an active layer region near the interface; the protective layer 35 serves to reduce the current density of the first region I of the active layer 33; the interface between the active layer 33 and the inactive layer 34;
And a second cladding layer 36 over the active layer 33, the protective layer 35, and the inactive layer 34.
In addition, in order to achieve better control over the process, the optical integrated chip may further include:
the cap layer 37 is located over a second region II of the active layer 33, the second region II being adjacent to the first region I, such that the second region of the active layer 33 is the region of the active layer remote from the interface.
It should be noted that, in the embodiments of the present application, the terms "inner", "outer", "longitudinal", "transverse", "upper", "lower", "top", "bottom", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, which are merely for convenience in describing the embodiments of the present application and not to limit the embodiments of the present application to be necessarily constructed and operated in a specific azimuth, and thus should not be construed as limitations of the embodiments of the present application.
As can be seen from the above, in the above optical integrated chip, a protective layer 35 is added on the first region of the active layer near the interface between the active layer 33 and the inactive layer 34. The protective layer 35 can reduce the current density of the active layer region adjacent to the interface, so that the current density of the active layer 33 adjacent to the interface is reduced due to the protective layer 35 during operation of the semiconductor optical integrated chip, thereby reducing the influence of high current density during operation of the semiconductor optical integrated chip on the active layer 33 adjacent to the interface, and further reducing the possibility of crystal defects of the material of the active layer 33 adjacent to the interface continuing to grow during operation of the semiconductor optical integrated chip. Therefore, the addition of the protective layer 35 reduces the possibility of continuous growth of crystal defects of the active layer material at the butt joint interface, reduces the risk of gradual deterioration and even abrupt failure of the performance of the semiconductor optical integrated chip during operation, and improves the long-term reliability of the semiconductor optical integrated chip.
As an example of the present application, the material of the protective layer 35 may be an undoped or low-doped semiconductor material having a doping concentration of less than 1e18cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The semiconductor compound may have a larger band gap than the material forming the active layer 33. The material of the protective layer 35 may be a III-V compound.
In order to prevent the performance of the active layer 33 from being affected, the length of the protective layer 35 along the light transmission direction within the optical integrated chip is greater than 0 and less than or equal to 20 μm. . Note that, the active layer 33 and the inactive layer constitute the optical waveguide, and the direction of the active layer 33 to the inactive layer is the transmission direction of light within the optical integrated chip, because the length of the protective layer 35 in the transmission direction of light within the optical integrated chip is too short, and the current density is insufficiently reduced; the length of the light of the protective layer 35 in the transmission direction in the optical integrated chip is too long, which is equivalent to that the active region has a very long absorption region near the butt joint interface, so that not only the quantum efficiency is reduced, but also a lot of heat is generated, and the reliability is affected.
The thickness of the protective layer 35 may be greater than 0 and less than or equal to 1 μm.
As an example of the present application, the protective layer 35 may be formed during the etching regrowth, and in the embodiment of the present application, no limitation is made to the process treatment method of the protective layer 35.
In the present embodiment, the first cladding layer 32 and the second cladding layer 36 serve to confine light. The material of the first cladding layer 32 and the second cladding layer 36 may typically be InP or GaAs, or other materials. The refractive index of the first cladding layer 32 and the second cladding layer 36 is lower than the refractive index of the active layer 33 and the inactive layer 34.
To enrich the function of the first clad layer 32, the first clad layer 32 may be a multi-layered structure.
As an example, in order to better control an etching end point of etching the active layer 33 in the etching regrowth process, an etching barrier layer for process control may be included in the first clad layer 32, which may act as a barrier layer for a process of etching the active layer 33.
As another example, to better control the mold spot, the first cladding layer 32 may also include one or more mold spot control layers therein having a refractive index that is greater than the refractive index of the first cladding layer 32. When the material constituting the first cladding layer 32 is InP or GaAs, the refractive index of the mode-spot control layer is larger than that of InP or GaAs.
Further, as yet another example, a hollowed-out layer may also be included in the first cladding layer 32 in order to form an air gap by performing an etching-out process under the first cladding layer 32.
To enrich the function of the second clad layer 36, the second clad layer 36 may have a multi-layered structure.
As an example, an etch stop layer may be included in second cladding layer 36 for better process control.
To facilitate electrode fabrication, as another example, the top end of the second cladding layer 36 may be provided with an electrode layer, which may be a heavily doped InGaAs layer formed by ion doping. The second cladding layer 36 may be provided with a band gap transition layer structure for transition band gap change to prevent excessive voltage, and the layer structure may be an InGaAsP layer as a more specific example.
In addition, in the embodiment of the present application, the inactive layer 34 may be a passive material layer for fabricating passive units such as an arrayed waveguide grating (arrayed waveguide grating, AWG), an Etched Diffraction Grating (EDG), a phase region, a light guide waveguide, a beam splitter, and the like; a modulator material layer may also be used to fabricate EA modulators or MZI modulators.
In addition, in order to improve high temperature performance of the semiconductor optical integrated chip, as an example, the active material used to form the active layer 33 may be an aluminum-containing quantum well material. Based on this, the active layer 33 may include an aluminum-containing quantum well material layer. The aluminum-containing quantum well material layer is used to provide gain. To further enhance the gain effect, as an example of the present application, the active layer 33 may further include a first separation-confinement heterostructure layer (separate confinement heterostructure layer, abbreviated as SCH layer) on a side of the aluminum-containing quantum well material layer facing the first cladding layer 32 layer, and/or a second separation-confinement heterostructure layer on a side of the aluminum-containing quantum well material layer facing the second cladding layer 36. In other words, the upper and lower sides of the aluminum-containing quantum well material layer are respectively provided with a second separation limiting heterostructure layer and a first separation limiting heterostructure layer, and the first separation limiting heterostructure layer and the second separation limiting heterostructure layer are used for controlling the optical field of the aluminum-containing quantum well region so as to adjust the limiting factor.
As another example of the present application, in order to prevent electron leakage, the active layer 33 may further include an electron blocking layer on a side of the second separation limiting heterostructure layer facing away from the aluminum-containing quantum well material layer. In other words, the active layer 33 may further include an electron blocking layer over the second separation limiting heterostructure layer.
As another example, the active material used to form the active layer 33 may be a phosphorous-containing quantum well material. Based on this, the active layer 33 may include a phosphorus-containing quantum well material layer.
The above is a specific implementation manner of the semiconductor optical integrated chip provided in the embodiments of the present application. As a specific example of the semiconductor optical integrated chip provided in the embodiment of the present application, the semiconductor optical integrated chip may be a bragg reflection DBR (distributed bragg reflection) laser chip, an optical amplifier chip, or an emitter array chip.
The specific structure of the bragg reflector DBR laser chip is shown in fig. 4, and the DBR laser chip includes a first mirror 41, a gain region 42, a phase region 43, and a second mirror 44, where the first mirror 41 is located in a first passive region, the gain region is located in a first active region, the phase region 42, and the second mirror 44 is located in a second passive region;
Wherein the first side of the first inactive region interfaces with the first side of the first active region, the second side of the first active region interfaces with the first side of the second inactive region, and the first side of the first active region is opposite the second side of the first active region. In other words, the first inactive region, the first active region, and the second inactive region are sequentially butted together.
Wherein the first mirror 41 and the second mirror 44 are for reflecting light; the first mirror 41 may be the front mirror FM of the DBR laser and the second mirror may be the back mirror BM of the DBR laser;
gain section 42 is used to provide gain;
the phase section 43 is used to adjust the phase.
Wherein, the junction of the first passive region and the first active region can adopt an epitaxial structure, and the epitaxial structure comprises:
a substrate;
a first coating layer for covering a surface side of the substrate;
the active layer and the non-active layer are both positioned on one side of the first coating layer, which is opposite to the substrate, and the side wall of the active layer, which faces the non-active layer, and the side wall of the non-active layer, which faces the active layer, are attached; the inactive layer comprises at least one of a passive layer or a modulation layer, and the modulation layer has a modulation function;
the protective layer is used for covering the surface of a first area of the active layer and is positioned on one side of the first area, which is opposite to the first coating layer, and the first area is an area, close to the non-active layer, in the active layer; the forbidden bandwidth of the material of the protective layer is larger than that of the material of the active layer;
And a second cladding layer for covering a surface of the second region of the active layer facing away from the first cladding layer, a surface of the protective layer facing away from the first region, and a surface of the inactive layer facing away from the first cladding layer; the second region is a region in the active layer other than the first region.
Specifically, in the embodiment of the application, a first protection layer is disposed above the first active region near the interface between the first active region and the first inactive region, and a second protection layer is disposed above the first active region near the interface between the first active region and the second inactive region. The first protective layer and the second protective layer are used for reducing the current density of the first active region below each first protective layer, so that the growth of crystal defects in the material of the first active region below each first protective layer is inhibited, and the long-term reliability of the semiconductor optical chip is improved.
In addition, as another implementation manner of the semiconductor optical integrated chip provided in the embodiment of the present application, on the basis of the bragg reflector DBR laser chip described in fig. 4, as shown in fig. 5, a first SOA (semiconductor optical amplifier ) 51 and a second SOA 52 may be integrated, where the first SOA 51 is located on the second active region and the second SOA is located on the third active region.
Wherein one side of the second active region interfaces with a second side of the first inactive region, the second side of the second inactive region interfaces with one side of the third active region, wherein the first side of the first inactive region is opposite the second side, and the first side of the second inactive region is opposite the second side. In other words, the second active region, the first inactive region, the first active region, the second inactive region, the third inactive region 44, and the third active region are sequentially butted together.
Wherein the above epitaxial structure may be employed at the interface of the second active region and the first inactive region and the interface of the third inactive region 44 and the third active region.
Specifically, in the present embodiment, a third protective layer is disposed over the second active region near the interface between the second active region and the first inactive region, and a fourth protective layer is disposed over the third active region near the interface between the third active region 52 and the third inactive region 44. The third protective layer and the fourth protective layer are used for reducing the current density of the active region below each protective layer, so that the growth of crystal defects in the material of the active region below each protective layer is inhibited, and the long-term reliability of the semiconductor optical integrated chip is improved.
As another implementation manner of the semiconductor optical integrated chip provided in the embodiment of the present application, the semiconductor optical integrated chip may be a semiconductor optical integrated chip integrated with a laser, a modulator and an amplifier; as shown in fig. 6, the semiconductor optical integrated chip includes: a laser unit 61, a modulator 62 and an SOA, wherein the laser unit 61 is located on the fourth active region, the modulator 62 is located on the fourth passive region and the SOA 63 is located on the fifth active region;
wherein the first side of the fourth inactive region interfaces with a side of the fourth active region and the second side of the fourth inactive region interfaces with a side of the fifth active region. That is, the fourth active region, the fourth inactive region, and the fifth active region are sequentially butted. In other words, the fourth active region and the fifth active region are respectively butted at both sides of the fourth inactive region.
As an example, the laser may be a DFB (Distributed Feedback laser ) laser.
As an example, the laser may be a DBR laser.
As an example, the modulator may be an EAM, and as another example, the modulator may be an MZM.
The laser unit is used for providing laser;
the modulator is manufactured on the modulator material and used for modulating the optical signals emitted by the laser unit; thus, in embodiments of the present application, the fourth inactive region may be a layer of modulating material.
The SOA is a semiconductor optical amplifying unit for re-amplifying the light modulated by the modulator.
In this embodiment of the present application, the above epitaxial structure may be used at the junction of the fourth active region and the fourth inactive region, and at the junction of the fourth inactive region and the fifth active region. Specifically, a fifth protective layer is disposed above the fourth active region near the interface between the fourth active region and the fourth inactive region, and a sixth protective layer is disposed above the fifth active region near the interface between the fourth inactive layer 62 and the fifth active region, the fifth protective layer being for reducing the current density in the fourth active region thereunder, thereby inhibiting the growth of crystal defects in the material of the fourth active region thereunder, and improving the long-term reliability of the semiconductor optical integrated chip.
The sixth protective layer is used for reducing the current density in the fifth active region below the sixth protective layer, so that the growth of crystal defects in the material of the fifth active region below the sixth protective layer is restrained, and the long-term reliability of the semiconductor optical integrated chip is improved.
As an implementation manner of the semiconductor optical integrated chip provided in the embodiment of the present application, the semiconductor optical integrated chip may be an emitter array chip, as shown in fig. 7 in particular. It comprises the following steps:
A laser unit group 71, a modulator group 72, a combiner 73, and an SOA 74;
wherein the laser unit group 71 includes N laser units 711 to 71N, the N laser units 711 to 71N are located in a sixth active region including N sub-active regions 1 to N, one laser unit is located on one sub-active region,
the modulator group 72 includes N modulators 721 to 72N; the modulator group 72 is located on a fifth inactive area, which includes N sub-inactive areas 1 to N, one modulator being provided on one sub-inactive area,
the sixth active region, the fifth inactive region, the sixth inactive region and the seventh active region are in butt joint in sequence, and one sub-active region is in butt joint with one sub-inactive region;
wherein N is a positive integer.
In the emitter array chip shown in fig. 7, the above-described epitaxial structure is used at the junction between each sub-active region and the sub-inactive region, and/or the above-described epitaxial structure is used at the junction between the sixth inactive region and the seventh active region.
Specifically, a seventh protective layer is arranged above each sub-active region near the butt joint interface of each sub-active region and each sub-passive layer;
an eighth protective layer is arranged above the seventh active region near the butt joint interface of the sixth passive region and the seventh active region;
The seventh protective layer is used for reducing the current density in each sub-active region below the seventh protective layer, thereby inhibiting the growth of crystal defects in the material of the sub-active region below the seventh protective layer and improving the long-term reliability of the semiconductor laser.
The eighth protective layer is used to reduce the current density in the seventh active region thereunder, thereby inhibiting the growth of crystal defects in the material of the underlying Fang Diqi active region and improving the long-term reliability of the semiconductor laser.
The foregoing is a specific implementation manner of the optical integrated chip provided in the embodiments of the present application.
Claims (13)
1. An optical integrated chip, comprising:
a substrate;
a first coating layer for covering a surface side of the substrate;
the active layer and the non-active layer are both positioned on one side of the first coating layer, which is opposite to the substrate, and the side wall of the active layer, which faces the non-active layer, and the side wall of the non-active layer, which faces the active layer, are attached; the inactive layer comprises at least one of a passive layer or a modulation layer, and the modulation layer has a modulation function;
the protective layer is used for covering the surface of a first area of the active layer and is positioned on one side of the first area, which is opposite to the first coating layer, and the first area is an area, close to the non-active layer, in the active layer; the forbidden bandwidth of the material of the protective layer is larger than that of the material of the active layer;
And a second cladding layer for covering a surface of the second region of the active layer facing away from the first cladding layer, a surface of the protective layer facing away from the first region, and a surface of the inactive layer facing away from the first cladding layer; the second region is a region in the active layer other than the first region.
2. The optical integrated chip of claim 1, wherein the material of the protective layer is an undoped or low doped semiconductor material having a doping concentration of less than 1e18cm "3.
3. The optical integrated chip of claim 1, wherein the first cladding layer and the second cladding layer each have an optical refractive index that is less than an optical refractive index of the active layer and the inactive layer to confine light in the active layer and the inactive layer.
4. An optical integrated chip according to any one of claims 1-3, wherein the material of the protective layer is a group III-V compound.
5. The optical integrated chip of any one of claims 1-4, wherein the protective layer has a length along a transmission direction of light within the optical integrated chip of greater than 0 and less than or equal to 20 μιη.
6. The optical integrated chip of any one of claims 1-5, wherein the protective layer has a thickness of greater than 0 and less than or equal to 1 μm.
7. The optical integrated chip of any of claims 1-6, wherein the active layer comprises a layer of aluminum-containing quantum well material.
8. The optical integrated chip of any of claims 1-6, wherein the active layer comprises a layer of phosphorus-containing quantum well material.
9. The optical integrated chip of claim 7, wherein the active layer further comprises:
at least one of the first separation confinement heterostructure layer or the second separation confinement heterostructure layer;
the first separation limiting heterostructure layer is positioned on one side of the aluminum-containing quantum well material layer facing the first cladding layer;
the second separation confinement heterostructure layer is located on a side of the aluminum-containing quantum well material layer toward the second cladding layer.
10. The optical integrated chip of claim 9, wherein the active layer further comprises: and the electron blocking layer is positioned on one side of the second separation limiting heterostructure layer, which is opposite to the aluminum-containing quantum well material layer.
11. The optical integrated chip of any one of claims 1-10, wherein the optical integrated chip is a bragg reflector DBR laser chip.
12. The optical integrated chip of any one of claims 1-10, wherein the optical integrated chip is an optical amplifier chip.
13. The optical integrated chip of any one of claims 1-10, wherein the optical integrated chip is an emitter array chip.
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| PCT/CN2018/103461 WO2020042137A1 (en) | 2018-08-31 | 2018-08-31 | Optical integrated chip |
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| JPS6290969A (en) * | 1985-10-17 | 1987-04-25 | Matsushita Electric Ind Co Ltd | Manufacture of optical integrated circuit |
| US5153890A (en) * | 1991-03-11 | 1992-10-06 | International Business Machines Corporation | Semiconductor device comprising a layered structure grown on a structured substrate |
| JPH11121787A (en) * | 1997-10-08 | 1999-04-30 | Toshiba Corp | Integrated photoelement and manufacture thereof |
| CN107666110A (en) * | 2016-07-28 | 2018-02-06 | 三菱电机株式会社 | Optical semiconductor device |
| CN108040505A (en) * | 2015-09-21 | 2018-05-15 | 华为技术有限公司 | Semiconductor optical device |
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| JP2005286198A (en) * | 2004-03-30 | 2005-10-13 | Sumitomo Electric Ind Ltd | Optical integrated element |
| US7843982B2 (en) * | 2005-12-15 | 2010-11-30 | Palo Alto Research Center Incorporated | High power semiconductor device to output light with low-absorbtive facet window |
| WO2010050071A1 (en) * | 2008-10-31 | 2010-05-06 | オプトエナジー株式会社 | Semiconductor laser element |
| CN109217108B (en) * | 2017-06-30 | 2020-08-04 | 中国科学院半导体研究所 | Method for manufacturing semiconductor laser by impurity induced hybrid technology |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6290969A (en) * | 1985-10-17 | 1987-04-25 | Matsushita Electric Ind Co Ltd | Manufacture of optical integrated circuit |
| US5153890A (en) * | 1991-03-11 | 1992-10-06 | International Business Machines Corporation | Semiconductor device comprising a layered structure grown on a structured substrate |
| JPH11121787A (en) * | 1997-10-08 | 1999-04-30 | Toshiba Corp | Integrated photoelement and manufacture thereof |
| CN108040505A (en) * | 2015-09-21 | 2018-05-15 | 华为技术有限公司 | Semiconductor optical device |
| CN107666110A (en) * | 2016-07-28 | 2018-02-06 | 三菱电机株式会社 | Optical semiconductor device |
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