JPS6314399A - Semiconductor nonvolatile storage device - Google Patents

Abstract

PURPOSE:To contrive to simplify and ensure a recall by selecting all word lines at recall, giving a prescribed potential to a bit line to reset a flip-flop of a SRAM cell and resetting a node of a flip-flop of the SRAM into a prescribed state. CONSTITUTION:A recall mode signal RC rises at first at recalling, to disconnect a sense amplifier, a write circuit 9 and a bit line. Then a signal AR2 rises, then a transistor (TR)4 at the inverse of BL is connected too ground via the TR5 to be 0V. On the other hand, a bit line BL goes to a high potential power voltage Vcc because a TR3 is turned on. When a signal AR1 rises, the output of a gate 7 goes to an H level, all word lines WL are selected, TRs T1, T2 of a word transfer gate are turned on, nodes N1, N2 of a flip-flop of a static RAM (SRAM) cell ST are reset to be Vcc 1V respectively in response to the Vcc 1V of the bit lines BL the inverse of BL.

Description

[Detailed Description of the Invention] [Summary] In a non-volatile memory device that is integrated by combining an SRAM cell and a non-volatile memory cell in a one-to-one ratio using high-resistance polysilicon as a load resistance, all word lines are selected at the time of recall. It has a control circuit that applies a predetermined potential to the bit line, resets the flip-flop of the SRAM cell, and resets the node of the flip-flop of the SR meter to a predetermined state, thereby easily and reliably performing recall.

[Industrial application field]

The present invention provides a one-to-one connection between SRAM cells and nonvolatile memory cells.
Regarding non-volatile memory devices integrated in combination with
The present invention relates to a circuit for easily and reliably performing (1).

[Conventional technology]

NVR known as non-volatile random access memory
AM uses EEPROM and SRAM as one memory cell.
It is configured by integrating them in a one-to-one correspondence. This NVRA
M functions to save (store) the data stored in the SRAM to the EBFROM when the power is turned off, and to recall it again when the power is turned on.

FIGS. 8(a) and 9(a) are circuit diagrams showing an example of a conventional NVRAM.

Figures 8(b) and 9(b) show the recall (Re).
ca ] 1) Power supply V CC% recall signal RCL
, is a timing diagram of the control signal VR.

Regarding the circuit of Fig. 8(a), patent application No. 58-191039
No. 58-456 for the circuit of Fig. 9(a).
Details are given in No. 97.

In FIGS. 8(a) and 9(a), depletion transistors T, ,'r2, enhancement transistors T3, . T, constitutes an SRAM cell. In addition, in FIG. 8(a), the nonvolatile memory cell is composed of Ts with the gate FC in a floating state, and the
In figure (a), FLOTOX (Floating-gat
e Tunnel Oxide) structure.

Data is written into the nonvolatile memory cell by injecting electrons into or emitting electrons from the floating gates of Ts and T7. As a result, Ts.

The threshold value of T7 changes, and T7 is turned on or off depending on the data in the SRAM. On the other hand, the recall operation is performed as follows. That is, in FIG. 8(a), the recall transistor T5 is turned on as shown in FIG. 8(b), and then the power supply Vcc is turned on. At this time, Ts
If is on, node N2 is at a low level, so only the potential of N rises, T4 is on, Ts is off, and N,
is at a high level and N2 is at a low level. On the other hand, when Ts is off, N2 is in a floating state, so the state of the flip-flop made up of T1 to T4 is not fixed. Therefore, some means must be taken so that the state of the flip-flop is determined to be the opposite state when Ts is on when Ts is off. Therefore,
Conventionally, circuits were configured so that the state of the flip-flop was unbalanced. This unbalanced state of the flip-flop circuit is caused by the load transistor T I + T
2 and the capacitances C, , c2. For example, the imbalance of load transistors T, T2 is determined by the channel width (W) and channel length (L) of each transistor.
It is determined by the size of W/L depending on the size, and the capacity is 1c+, cz
The unbalance of the capacitance values is determined by the shape of the pattern. For example, if the capacitance values are set in the relationship c,>c2, the recall operation when Ts is off is performed as follows. That is, when the power supply voltage Vcc rises, if the capacitance C,>C2, the potential of the node N1 rises later than that of the node N2, so that the node N becomes L level and the node N2 becomes H level. On the other hand, when Ts is on, N2 is forcibly suppressed to the L level as described above, so the node Nl becomes the H level and the node N2 becomes the L level. In addition, the relationship between the channel width W and the channel length of the depletion type load transistor 'r, T2 is that the larger W is, the larger the current flows, and the smaller L is, the larger the current flows, so W/ L
In other words, the value of is equivalent to the magnitude of the resistance value, CI + C
Instead of having a magnitude relationship between 2 and 2, the above-mentioned recall operation can be performed by having a load, that is, W/L, have a magnitude relationship. In the case of FIG. 9(a), since VR is activated at the time of recall, the relationship between the on/off of T7 and the levels of N, , N2 is simply reversed from that of FIG. 8(a). , and other basic operations are the same as in FIG. 8(a). That is, when T7 is on, N2 is at H level and N1 is at L level, and vice versa when T7 is off. however,
The relationship between capacitance values is c, <C2.

[Problem that the invention seeks to solve]

In the NVRAM with the above configuration, the capacitances C, , C2 are ideally determined according to the pattern when designing the layout of the integrated circuit, but in reality, the capacitance C1 occurring at the node N is the capacitance of the transistor. 'r,,'r
=, and the capacitance C2 occurring at node N2 is dependent on transistor T2. T4+ T5. Capacity C2 depends on T@ etc.
Therefore, in order to satisfy the condition c,>C2, it is necessary to intentionally increase the capacitance C3, resulting in an increase in the cell area. On the other hand, a difference is made between the load transistors 'r, , T2, that is,
For example, in order to make T>T2, it is necessary to make a difference in channel width or channel length, which also results in an increase in area. Furthermore, making T1 and T2 or C1 and 02 unbalanced means that, as a characteristic of SRAM, there is a relationship between the node N level and the L level of node N2 or the H level of node N2 (level itself and charging speed). There is a problem in that T and T2 become asymmetric, resulting in slow access, and an imbalance between T and T2 requires a considerable imbalance in cell current, resulting in an increase in current consumption. .

Incidentally, it is conceivable to reduce the current consumption by replacing the load transistor with a high-resistance polysilicon, as is currently done in normal SRAMs. Replacing the load transistor with high-resistance polysilicon can also contribute to improving the degree of integration of semiconductor memory devices.

By making the resistance value of this high-resistance polysilicon extremely high, it is possible to allow current to flow only on the order of picoA. However, in that case, a problem arises when restoring data from the E2 PROM to the SRAM.

In the case where a depletion type transistor is used as the load transistor in the conventional example described above, the power supply VCC is Ov
Then, the node N l of the SRAM flip-flop
5N2 was immediately reset to the equilibrium state (OV, 0 ■). On the other hand, if a high-resistance polysilicon load is used, the resistance value is very large, so the node N of the flip-flop.

, the time required to charge N2 becomes extremely long (for example, several hundred microseconds), resulting in a problem that the restoration operation becomes slow, making it impossible to achieve the desired recall operation time of about 1 microsecond. there were.

[Means for solving problems]

In order to reduce the power consumption of the above-mentioned NVRAM, if the SRAM cell is configured using a high-resistance polysilicon load, the difficulty of resetting the flip-flop node to an ov, ov equilibrium state during recall is solved. In order to achieve this, the present inventor has made various considerations and studies, including changing the conventional method of completely resetting the flip-flop nodes upon recall, and has arrived at the present invention. It is something.

The present invention includes a flip-flop in which a pair of inverters each made of a transistor having a high-resistance polysilicon as a load resistance is cross-connected, and information is read out to a bit line via a word transfer gate, or information is written to the bit line. a static memory cell configured to store data, a nonvolatile memory transistor that is turned on or off according to information stored in the static memory cell when saving data, and a flip-flop transistor and load of the static memory cell. a recall transfer gate inserted between a connection point with the resistor and the first terminal of the nonvolatile memory transistor;
When recalling the information stored in the nonvolatile memory transistor to the static memory cell, all word lines are selected, a predetermined potential is applied to the bit line, the flip-flop is reset to a predetermined state, and the recall is performed. The second terminal of the nonvolatile memory transistor is controlled by controlling the potential of the third terminal of the transfer gate to make it conductive.
A semiconductor nonvolatile memory device is provided, comprising a control circuit that controls the potential of a terminal and sets the flip-flop according to information stored in the nonvolatile memory transistor.

[Effect]

According to the configuration of the present invention, even if a high-resistance polysilicon load resistor is used in a static memory cell, flip-flops can be reset when recalling information from a nonvolatile memory transistor by selecting all word lines and bit lines. Since the flip-flop is reset to a predetermined state by applying a predetermined potential to the flip-flop, the resetting operation can be performed in about the same time as writing information to a normal static memory cell. As a result, it is possible to use a high-resistance load in the SRAM, significantly reducing power consumption compared to using conventional depletion-type load transistors, and to eliminate incomplete resets and recall failures. can. Furthermore, using high-resistance polysilicon as the load simplifies the structure of the memory cell and contributes to improving the degree of integration.

〔Example〕

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention.

Static RAM (SRAM) cells are ST, E
TMM non-volatile memory transistor of EFROM cell
It is expressed as BL is the bit line, WL is the word line, vc
c is a high-level power supply voltage, and Vss is a low-level power supply, which in this case is a ground potential of 0■. The n-ch type MOS transistors constituting the flip-flop of the static RAM cell are shown as TSI and TS2, and the high resistance polysilicon load resistances of the respective loads are shown as LRI and LR2. Here, the load resistance of the SRAM flip-flop connected to the recall transistor TAR is LR2, and the other load resistance is LRI.The other terminal of the recall transistor TAR is connected to the nonvolatile memory transistor TM. ?l is connected to one terminal, and a control voltage VR is applied to the other terminal of TMH.Although S is a store circuit, the present invention relates to recall, and its configuration is the same as the conventional one. Since they are the same, their explanation will be omitted here.

In the above configuration, EEF from the static RAM side
The operation (store) of saving data to the ROM side is exactly the same as the conventional one. On the other hand, EEF from the static RAM side
The operation of recalling data to the ROM side is performed as follows.

■ Bit line voltage V BL = V cc, bit line VB
The word line is raised with L (bar)=OV (word line potential V WL=V cc). Thereby, node N
1 voltage VNI-Vcc, /- voltage of node N2 VN2=O
It is reset to V.

■ Deselect all word lines (word line potential VWL=
0■).

■ Pull the recall signal ARC high (V ARC
=Vcc)L, TAR is conductive. At the same time, the control signal VR
to VCC level. At this time, VNI and VN2 change depending on whether the cell TMH of the HEPROM is turned on or off. That is, in the case of FIG. 1 (a) When the memory transistor TMM of the EEFROM is off - the flip-flop remains as it is.

(V N1= V ccSV N2= OV) (b)
El! When the memory transistor TMM of PROFI is on - the flip-flop is inverted.

(VNI-OV, VN2-Vcc) FIG. 2 shows a recall operation waveform diagram of this embodiment, and will be further explained with reference to this. In the figure, the hunting portion indicates that it is uncertain whether the potential of N1 or N2 is L level or H level. Note that ARC and VR are connected to the word line WL as shown in the figure.
It may be added before the falling edge of .

As is clear from FIG. 2, El! FROM
When the cell is on (assuming that information rOJ is contained), the EEFROM memory transistor T? IM F
Since G has a positive charge, TMM is on,
When the signal ARC goes to H level during recall and the recall transistor TAR is turned on, the node N2 becomes TAR,
It is connected to VR=Vcc through 7. therefore,
SRAM cell node N1. N2 was at H level and L level, respectively, but VR = Vcc at the node of N2
Current flows through TIIM and TAR from N
The potential of 2 rises, the flip-flop is inverted, and N1 goes low.
level, N2 becomes H level. That is, these are EEPl? due to the recall operation. OM memory transistor TM
It means that "0" of M is restored to the SRAM cell.

Furthermore, when the memory transistor TMM of the EHFROM in (b) above is off (assumed to hold information "1"), FC has a negative charge, so TMM is off, and the recall transistor TAR is on. Even if this happens, node N2 is cut off from VR.

Therefore, at the time of recall, the signal ARC becomes H level, and T
Even when the AR is turned on, the state of the SRAM cell is maintained as is, V N1 = V cc, V N2 = OV.

That is, this means that "1" in the memory transistor TMM of the EEPROM is restored to the SRAM cell by the recall operation.

Here, in order to guarantee the operation of the above embodiment, VR must be divided by TMM (ON), TAR, and Ts2, so that the voltage of N2 is equal to the threshold of the flip-flop transistor Tsl The dimensions of transistors TMM and TAR are set so as to exceed the value vth.

Next, FIG. 3 shows the overall circuit configuration for performing the above-mentioned recall operation of this embodiment. In Figure 3, 1 is the row (
ROW ) decoder 1.2 is a column decoder, 3 and 4.5 are control transistors, and 6.7.8 is a NA
ND gate 9 is a sense amplifier and write circuit.

Further, ARI bar (bar: indicates an inverted signal; the same applies hereinafter), AR2, AR2 bar, RC, and RC bar are control signals. Other static memory cells
Regarding T, the same parts as in FIG. 1 are designated with the same reference numerals.

Further, FIG. 4 shows an operating waveform diagram of the circuit of FIG. 3.

To explain Fig. 3 and Fig. 4 in correspondence, at the time of recall,
First, recall mode signal RC is raised. As a result, the output of gate 8 becomes H level, and L level is applied to output gate COL via the inverter, COL is closed and sense amplifier/write circuit 9 is disconnected from the bit line.

Next, when the signal AR2 is raised, the transistor 4 on the BL bar side is turned off and the transistor 5 is turned on, so that the bit line BL bar is grounded through the transistor 5 and becomes Ov. On the other hand, the transistor 3 of the bit line BL is turned on, and the bit line BL is pulled up to a high power supply voltage Vcc.

Next, when the signal ARI is raised, the output of the gate 7 becomes H level, all the word lines WL become selected (H level), the word transfer gate transistors T, , 'r2 are turned on, and the Bit line BL, BL
According to the Vcc and OV of the bar, the nodes Nl and N2 of the flip-flop of the SRAM cell ST are set to Vcc and OV, respectively.
It is reset to V. In this state, ARI changes to L level, all word lines WL go to L level, word transfer gates T, . . . T2 are turned off, and the flip-flop of SRAM cell ST is separated from the bit line.

When the recall control signal ARC goes to H level in this state, the recall transistor TAR turns on and EIli
PROM memory transistor T? When IH contains information "0" (FG contains a positive charge), TMM is on and node N2 is connected to VR. Therefore, the nodes Nl, N2 of the SRAM cell are N1. N
2 were at H level and L level, respectively, but the flip-flop was reversed and Nl and N2 were at L level, respectively.
It becomes H level. Furthermore, when the memory transistor TMM of the EEFROM holds information "1" (FG has a negative charge), the TMM is off, and even if the recall transistor TAR is turned on, the node N2 remains at Vs.
s, the state of the SRAM cell is set as is, and the node N1. N2 potential V N1= OV
, V N2 = V cc.

FIG. 5 shows a circuit configuration for generating the timing necessary for the recall operation of this embodiment, and FIG. 6 shows its operating waveform diagram.

The circuit in Figure 5 has a flip-flop at its input, and a timing generation circuit (inverter, diode-connected depletion type MO3) that generates timing signals from ■ to ■.
) consisting of a transistor and a capacitor), a recall pulse is applied to the input of the flip-flop, and the output (2) of the final stage timing generation circuit is fed back to the flip-flop for resetting. Then, a NAND with the output signals ■ and ■ of the timing generation circuit as inputs.
A signal AR2 is obtained as an inverted signal of the gate output, a signal API is obtained as an output of a NOR gate whose inputs are ■ and ■,
Signal ARC as NOR gate output with ■ and ■ as input
The signal RC is obtained from the output ◎ of the flip-flop.

FIG. 7 is a circuit diagram of another embodiment of the NVRAM of the present invention. The same reference numerals are given to the same parts as in FIG. 1.

The nonvolatile memory transistor TMM' is a transistor having a structure in which the transistor TMM and a part of the storage circuit S are integrated as shown in FIG.
FLOTOX (Floating-ga) corresponding to 7
This is a transistor with a TE Tunnel Oxide) structure.

This non-volatile memory transistor TM? Writing data to 'l' is T (via Tunnel Oxide)
MM' floating gate) is performed by injecting electrons into the FG or ejecting electrons from the floating gate. As a result, the TMM threshold changes and TM? l is SI'lA? It is turned on or off depending on the data of I. At the time of recall, the control gate is set to H level by RCL, and the floating gate FG is turned on or off depending on the positive or negative charge of the floating gate FG.

When the nonvolatile memory transistor TMM has information "1", there is a negative charge in the floating gate and the TMM is off, and when it has information "0", the floating gate has a positive charge and the TMM is on. Then, when resetting the flip-flop, node N1 is reset to H level and N2 is reset to Ov, all word lines are selected as in the previous embodiment, and BL is set at H level and BL bar is set at L level. If we set RCL to Vcc at the time of recall and allow current to flow from VR=Vcc to the flip-flop node only when TMM is on, I! Information in EPROM memory transistors can be restored to SRAM cells.

〔Effect of the invention〕

According to the present invention, when the SRAM load of NVRAM is made of high-resistance polysilicon, flip-flop nodes can be quickly and reliably reset during recall, and the conventional problem of slow recall operation can be solved. . Furthermore, power consumption can be significantly reduced compared to when conventional depletion type load transistors are used, and the configuration can be simplified and the degree of integration can be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the main parts of a circuit according to an embodiment of the present invention, FIG. 2 is an operation waveform diagram of the circuit in FIG. 1, and FIG. 3 is a circuit diagram showing a configuration for performing a recall operation according to an embodiment of the present invention. , Figure 4 is the third
FIG. 5 is a circuit that generates the timing necessary for the embodiment of the present invention shown in FIG. 3. FIG. 6 is a timing waveform diagram of the embodiment shown in FIG. The circuit diagrams of other embodiments of the invention, FIGS. 8(a) and (b), are the circuit diagrams and operation waveform diagrams of the conventional example, and FIGS. 9(a) and (b), respectively.
) are a circuit diagram and an operation waveform diagram of other conventional examples, respectively. ST static RAM cell TMM: EEFROM memory transistor BL
: Bit line WL: Word line Vcc: High power supply voltage Vss: Low voltage TAR: Recall transistor (transfer gate for recall) ARC: Recall control signal LRl, LR2: Load resistance of SRAM flip-flop. High resistance polysilicon

Claims (1)

[Claims] The device includes a flip-flop in which a pair of inverters each having a load resistance of high-resistance polysilicon is cross-connected, and reads information to a bit line through a word transfer gate or writes information on the bit line. a static memory cell configured to store data; a nonvolatile memory transistor that is turned on or off according to information stored in the static memory cell when saving data; and a flip-flop transistor and load of the static memory cell. It has a recall transfer gate inserted between the connection point with the resistor and the first terminal of the nonvolatile memory transistor, and further transfers information stored in the nonvolatile memory transistor to the static memory cell. When recalling, all word lines are selected, a predetermined potential is applied to the bit line, the flip-flop is reset to a predetermined state, and the potential of the third terminal of the recall transfer gate is controlled to make it conductive; A semiconductor nonvolatile memory device comprising a control circuit that controls the potential of a second terminal of the nonvolatile memory transistor and sets the flip-flop according to information stored in the nonvolatile memory transistor. .