JPS61122999A - Memory cell - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Technical fields> The present invention relates to memory cells.

BACKGROUND ART Generally, memory cells can be divided into two main groups, one of which is volatile memory cells and the other non-volatile memory cells.

Volatile memory cells use logic elements to store data that can be continuously updated from an external data source. This type of memory cell is called "volatile" because the stored data is lost if the power supply voltage to the device is interrupted. An example of volatile memory is random access memory (RAM).

Nonvolatile memory cells also use logic elements to store data, but in some types of nonvolatile memory, the logic state of the memory cell is determined by the physical structure of the logic element itself, so that stored data cannot be updated. Can not do it. This type of cell does not lose the data stored in the cell even if there is an interruption in the supply voltage to the device.
called "non-volatile". One type of non-volatile memory is well known as read only memory (ROM).

Another type of non-volatile memory is electrically erasable read only memory (EEPROM).

In this type of device, the basic memory cell is typically a metal oxide silicon (MOS) with two gate electrodes.
It has a transistor. One gate electrode consists of a conventional gate electrode known as a control gate, which is placed overlying the second gate during manufacture of the device. Since the second gate is contained within and completely surrounded by the oxide layer of the MOS transistor, and during use of the device the second gate is not directly connected to any potential source, Known as a floating gate. The floating gate is partially separated from the semiconductor region of the device by a very thin section of oxide layer.

This very thin area of the oxide layer means that when a voltage exceeding a certain predetermined value is developed across the thin area of the oxide layer, charge transfer occurs between the semiconductor region and the floating gate, thereby causing a charge transfer to occur between the semiconductor region and the floating gate. It is known as a tunnel (tLlnnelinO) oxide region because it anchors the charge of .

Since the floating gate is fabricated from a conductive material such as metal or polysilicon, charge that is transferred through the tunnel oxide region quickly dissipates off the top of the floating gate. The floating gate is surrounded by a layer of oxide, usually made of silicon dioxide, which is a good insulator, so any charge transferred to the floating gate will last for years unless removed. survive.

It can therefore be seen that data can be read into a cell and stored on such a floating gate. Since data persists on the floating gate regardless of the supply voltage to the device, the cell functions as a non-volatile memory into which data can be programmed from an external data source.

It has previously been proposed to incorporate such floating gates into volatile random access memory (RAM) to create a memory that can perform the functions of both volatile and non-volatile memory. In such a memory, volatile data information can be updated without disturbing the non-volatile stored data, and this volatile data can be updated by interrogating the cell.
on).

However, tunnel oxide regions usually have very thin areas of oxide, for example 20 to 100 thick. In order to retain the charge accumulated on the floating gate, it is very important that the tunnel oxide region is free of defects such as pinholes. These defects create a leakage path for the charge stored on the floating gate, with subsequent loss of stored data. It has been discovered that it is advantageous to minimize the area of the tunnel oxide region to minimize the likelihood of such defects occurring during memory fabrication.

However, the magnitude and duration of the applied voltage required to induce charge transfer to the floating gate depends on several factors, including the difference between the drain region of the MOS transistor and the floating electrode. This also includes capacitive coupling between the control electrode and the floating electrode.

As mentioned above, such cells are typically fabricated with a control electrode overlying the floating gate, and in this type of cell, a requires relatively large voltage pulses, for example 20 volts.

The control electrode may be a diffusion layer in the semiconductor substrate, extending over the diffusion control bridge in a manner similar to that for the tunnel oxide region, and also extending over the diffusion control bridge. The area of the layer is spaced apart from the diffusion control pole. If the area of the diffusion control electrode is made relatively large, the capacitive coupling that occurs between the floating gate and the control electrode will be relatively large.

Furthermore, the capacitive coupling between the floating gate and the diffusion control electrode is such that the charge transfer to the floating gate in the tunnel oxide region is not adversely affected by the semiconductor layer in the floating gate and the tunnel oxide region. It is large compared to the capacitance between.

Problem and Features of the Invention It is an object of the present invention to provide an improved memory cell having a diffused control electrode and having both volatile and non-volatile modes of operation.

According to the present invention, there is provided a memory cell for volatile or non-volatile storage of data, the memory cell having two inverters, each inverter having one inverter.
a pair of complementary metal oxide silicon (0MO3) transistors in which each inverter has a diffused control electrode and a floating gate common to the complementary transistor of each inverter;
They are cross-coupled by a node between the complementary transistors of each inverter and coupled to the control electrode of the other inverter, thereby allowing non-volatile data on the floating gates of the inverters to be differentially sensed.

Each floating gate can be formed of polysilicon.

<Embodiments of the Invention> Next, embodiments of the present invention will be described with reference to the accompanying drawings.

Referring to FIG. 1, this memory cell has two inverters 2 and 4, which are cross-coupled to function as a bistable latch circuit. Inverter 2.4
are each a pair of complementary metal oxide silicon (0
MO8> Transistors TI, T2 and T3. T4, and each of these transistor pairs is connected to a voltage source SS and VD.
are connected in series across D at nodes N1 and N2.

CMOS transistor T1. T2 and T3. Complementary transistor pairs consisting of T4 have common floating gates FGI and FG2 and diffusion control electrodes C1 and 0 for every 8 pairs.
It has 2. Control electrodes c1 and C2 are formed diffused into the semiconductor layer of the MOS transistor and are separated from the 70-pointing gates FG1 and FG2 by a thin layer of oxide, as shown in FIG.

Charge transfer to floating gates FG1 and FG2 is as follows:
These occur through tunnel oxide regions TR1 and TR2, respectively.

Inverters 2 and 4 are cross-coupled by connecting the control electrode of one inverter to the node of the other inverter, as shown in FIG. Also, nodes N1 and N2 are connected to access transistors T5 and T, respectively.
6, it is connected to the true bit line B and the inverse bit line B (B bar), as well as to the common word line W.

The structure of the CMO8I transistor in the inverter 2.4 can be seen in FIG. Each inverter has an insulating oxide layer 10 with an N-channel transistor 6 and a P-channel transistor 8 extending over the semiconductor layer, a floating gate 12 being completely surrounded within and by the insulating oxide layer 1o. It is formed by Diffusion control bridge 14
is formed within the semiconductor layer of the N-channel transistor 6. The floating gate 12 is formed in the oxide layer 10 and extends in close proximity to the underlying semiconductor layer, which is connected to the tunnel 11 (by forming the ISS region 16 in this region). 16) to allow charge transfer to the O-ting gate 12. Floating gate 12 also extends in close proximity to the surface of diffusion control electrode 14. Floating gate 12 is thus created in region 18.
However, this region 18 exhibits relatively high capacitive coupling between the floating gate 12 and the control electrode 14. This relatively high capacitive coupling causes floating gate 12
is sufficient that charge transfer to can occur through the tunnel region ti116.

The memory cell shown in FIG. 1 has the following operating modes.

(+) Volatile data storage (ii) Non-volatile data storage (iii) Non-volatile data retention (iv) Non-volatile data recall For volatile data storage, this memory cell behaves as a regular CMOS static RAM cell. In this mode of operation, data can be written to and read from the cell via access transistors T5 and T6 and bit lines B and B. In this mode of operation, for example, the supply voltage is vss=o volts and VDD=+5 volts.

Data can be written into the cell by keeping the bit lines B and B in the appropriate state, for example by applying voltages vSS and VDD to these lines and at the same time enabling the access transistors T5 and T6. Set word line W to H. When access transistors T5 and T6 are enabled, the cell latch acquires one state determined by the condition of bit lines B and B. Word line W is then pulled low, disabling access transistors T5 and T6 and isolating the cell from bit lines B and B.

Data can be retrieved from the cell by bringing word line W high and enabling access transistors T5 and T6. The data stored in the cell appears on bit lines B and B at voltage levels at nodes N1 and N2 so that it can be detected by a sense amplifier (not shown). However, since this cell is operating as a volatile RAM cell, its stored data will be lost if there is an interruption in the voltage sources SS and VDD.

The cell shown in FIG. 1 may also operate in a non-volatile data storage mode. In this mode of operation, the floating gate F
By inducing a charge difference on GI and FG2, data is stored as non-volatile data. Initially, the power supply voltages SS and VDD are kept at Opol and +5 volts, respectively,
Data is written into the cells in a manner similar to that described above for volatile data storage.

Non-volatile data storage mode is understood in the following example. Data written into the cell in volatile data storage mode causes node N1 to be H (close to voltage tt voltage VDD), and
Assume that node N2 is set to L (close to power supply voltage SS). Since the node N1 is directly connected to the control electrode C2 of the inverter 4, when the node N1 is high, the control electrode C2 also becomes high, and the transistor T4 conducts and turns on.
become. Similarly, when node N2 is on, the control electrode C1 of inverter 2 becomes L, and transistor T2 becomes OF.
It is held in the F state. At this stage, data is stored as volatile data depending on the state of the latch circuit of the memory cell. For example, if the power supply voltage vDD is +5 volts to +15
When raised to the write voltage VR of volts, the voltage at node N1 also rises to almost +15 volts. When the control electrode C1 is at L (almost 0 volts since it is connected to the node N2), the floating gate FGI also becomes low. Therefore, most of the +15 volt write voltage is applied to the tunnel oxide region of inverter 2 [T
appears across R1, making node N1 positive with respect to floating gate FG1. Tunnel oxide region TR
The write voltage VR appearing across 1 is sufficient to induce tunneling in the region TR, so that positive charges are transferred to the 70-ting gate FGI of the inverter 2.

Since the node N2 of the inverter 4 is almost close to 0 volts and the node N1 is H, the control electrode C2
is also H. Therefore, transistor T4 is kept ON,
Transistor T3 is kept OFF. Power supply voltage VDD
When is raised to the write voltage VR, i.e. from +5 volts to +15 volts, node N2 remains near O volts, but control electrode C2 and floating gate FG2 are connected to node N1, so that control electrode C2 is connected to node N1. is almost raised to the write voltage VR (+15 volts). Therefore, the write voltage VR of +15 volts is almost unchanged in the tunnel oxide region f! of inverter 4! T.R.
2, making node N2 negative with respect to floating gate FG2. This voltage appearing across tunnel oxide region TR2 is sufficient to induce tunneling in region TR2, thus causing negative charge to be transferred to floating gate FG2.

It can be seen that the voltages appearing across each of the tunnel oxide regions R1 and TR2 are substantially equal, but of opposite polarity. Tunnel oxide regions TR1 and TR2
have substantially equal charge transfer efficiency, then 7
The charges stored in the 0-ting gates FG1 and FG2 are of opposite polarity but substantially equal in magnitude, thereby producing a symmetrical threshold voltage shift on each side of the latch circuit. By storing complementary data on each side of the memory cell's latch circuit, differential sensing during recall of non-volatile stored data allows very small disparities in stored charge to be applied to the cells, as described below. This makes it possible to identify the cell, thereby increasing the durability and memory capacity of the cell.

Since charge is held on floating gates FG1 and FG2, data written to the cell is stored as non-volatile data. Furthermore, floating gate FG1
The non-volatile data stored as charge on FG2 is
In the aforementioned volatile data retention mode, data is retained during the next operation of the memory cell.

Non-volatile data is sent to floating gates FG1 and FG2
If the cell is required to be used in volatile data storage mode while being held on, the supply voltage vSS is held at 0 volts and the supply voltage vDD is increased from the write voltage VR of +15 volts to its initial level. It can be lowered to +5 volts. Now, as previously described, volatile data can be written to or read from the cell by enabling access transistors T5 and T6. During this mode of operation, the maximum potential that can appear across the tunnel oxide layers [TR1 and TR2 is VDD, which is at +5 volts, which is insufficient to induce tunneling in the tunnel oxide regions TR1 and TR2. be. Therefore, the charge on the 70-signal gates FG1 and FG2 representing non-volatile data is retained during the volatile data storage mode of operation.

When the power supply voltage is interrupted, the voltages VDD and SS are O volts. The only potential in the cell is provided by the data storage, floating gates FGI and F.
This is the low voltage charge stored on G2. These voltages are much lower than the voltages required to induce tunneling in the tunnel oxide regions TR1 and TR2, and therefore the leakage of charge from the floating FG1 and FG2 is also limited by the oxides in which they are very good insulators. Since it is contained within the layer, it is extremely small.

In order to recall non-volatile data, the power supply voltage VDD and ■
SS is returned to the memory cell. floating gate F
The nonvolatile data stored as the difference between the charges in G1 and FG2 has the effect of repelling or attracting electrons from the surface of the semiconductor substrate in the channel region of the MOS transistor depending on the polarity of the charges on each floating gate. will have. For example, as described above with respect to non-volatile data storage, floating gate FG1 accumulates positive charge and floating gate F
Consider an example where G2 is accumulating negative charge.

Since the floating gate FGI stores positive charge, the threshold voltages of transistors T1 and T2 are shifted negatively with respect to the P-channel device @TI, which has a lower threshold voltage than the N-channel device, transistor T2.

Since floating gate FG2 is storing negative charge, the threshold voltages of transistors T3 and T4 are shifted positively with respect to transistor T3, which is a P-channel device, having a lower threshold voltage than transistor T4, which is an N-channel device. Ru.

As the supply voltage VDD rises towards +5 volts, transistor T3 begins to close before transistor T1. This is because the threshold voltage of transistor T3 is lower than that of transistor T1. As a result, the voltage at node N2 rises faster than the voltage at node N1, causing node N2 to rise faster than the voltage at node N1.
Since it is connected to the t11 electrode, the transistor T2 is switched on before the transistor T4. This situation is enhanced by transistor T2 having a lower threshold voltage than transistor T4. This imbalance causes the node N2 in the memory cell to be close to the power supply voltage V.
How high is DD, and node N1 is almost at the power supply voltage ■SS
The data is initially memorized and the path becomes low, resulting in the acquisition of a stable state.
4° The recalled non-volatile data at nodes N1 and N2 can be read by enabling access transistors T5 and T6 and their true state can be read by passing through an inverter (not shown). can be returned to.

<Effects of the Invention> As understood from the above description, the present invention provides the following unique effects. That is, the memory cell according to the present invention provides volatile and non-volatile modes of storage and is extremely simple to operate. Also, no additional control lines are required compared to conventional volatile static RAM cells. Furthermore, the simple arrangement of the memory cell of the present invention allows it to be fabricated in an integrated circuit device in only a fraction of the area larger than a conventional volatile CMO8 RAM cell.

Although the invention has been described with respect to specific embodiments, it will be understood that modifications may be made within the scope of the invention.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing an embodiment of a memory cell according to the invention, and FIG. 2 is a schematic cross-sectional view of one inverter of the memory cell illustrated in FIG. Brief description of the drawings: 2.4... Inverter, 6.8... Complementary transistor, 10... Oxide layer, 12... Floating gate, 14... Control electrode, 16... Tunnel oxide region, B, B...Bit line C1, C2.-ailla electrode, FG1, FG2... Floating gate, T1. T
2...Transistor pair of inverter 2, T3. T4・
... Transistor pair of inverter 4, T5. T6...
Access transistor, W...word line

Claims (6)

[Claims] (1) Contains two inverters, each inverter is one
A memory cell for volatile and non-volatile data storage comprising a pair of complementary metal oxide silicon transistors: each of said two inverters (2, 4) comprising:
a floating gate (12) common to the diffusion control electrode (14) and the complementary transistors (6, 8) of the inverter;
), and the two inverters (2, 4) have a node (N1, N2) between the complementary transistors of one of the inverters and coupled to the control electrode (C2, C1) of the other inverter. ), whereby the floating gates (FG1, FG2) of the inverter
A memory cell characterized in that differential sensing of non-volatile data on the memory cell is achieved. (2) A memory cell according to claim 1, wherein: for each of the inverters (2, 4), its control electrode (14) is diffused in the semiconductor layer; and its floating The gate (12) consists of an oxide layer (1
0) and the control electrode (14) and the transistors (6, 8
) arranged to extend over the control electrode (14) but separated from the control electrode (14) by a tunnel region (16, 18), the tunnel region permitting charge transfer therethrough. Its dimensions must be determined as follows;
Furthermore, the control electrode (14) and the floating gate (12) are such that the capacitive coupling between them is relatively greater than the capacitive coupling between the floating gate (12) and the drain region of the transistor (6, 8). The memory cell described above is arranged such that the size of the memory cell increases. (3) In the memory cell according to claim 2: the floating gate (12) and the control electrode (14).
) and the floating gate (1
2) and the drain region reduces the charge on the floating gate (12) when a voltage of more than about 10 volts is applied to this memory cell to enable non-volatile storage of data. The memory cell described above is configured such that movement can be induced. (4) A memory cell according to claim 2 or 3, characterized in that the tunnel region (16, 18) has a thickness in the range from 20 angstroms to 100 angstroms. memory cells. (5) Any one of claims 1 to 4
2, wherein the floating gate (12) comprises polysilicon;
The aforementioned memory cell characterized by: (6) A memory cell according to any one of claims 1 to 5, wherein each inverter (
2, 4), one bit line (B, B) for supplying data to the inverter, and the bit line (B, B) connected to the complementary transistors (T1, T1, B) of the inverter (2, 4). T2, T3, T4) between nodes (
said memory cell characterized by one access transistor (T5, T6) for coupling to N1, N2).