JPS63142638A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63142638A JPS63142638A JP28990386A JP28990386A JPS63142638A JP S63142638 A JPS63142638 A JP S63142638A JP 28990386 A JP28990386 A JP 28990386A JP 28990386 A JP28990386 A JP 28990386A JP S63142638 A JPS63142638 A JP S63142638A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor
- semiconductor device
- chip
- cleaning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 19
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims abstract description 16
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000004140 cleaning Methods 0.000 claims abstract description 12
- 150000001875 compounds Chemical class 0.000 claims abstract description 8
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 6
- 239000000203 mixture Substances 0.000 claims abstract description 6
- 239000007864 aqueous solution Substances 0.000 claims 1
- 238000005219 brazing Methods 0.000 abstract description 10
- 239000000463 material Substances 0.000 abstract description 8
- 229910000679 solder Inorganic materials 0.000 abstract description 8
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 6
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 3
- 239000006023 eutectic alloy Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910017401 Au—Ge Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000012459 cleaning agent Substances 0.000 description 1
- SWXVUIWOUIDPGS-UHFFFAOYSA-N diacetone alcohol Natural products CC(=O)CC(C)(C)O SWXVUIWOUIDPGS-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Cleaning By Liquid Or Steam (AREA)
- Die Bonding (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置の製造方法に関する。より詳細に
は、本発明は、回路を搭載したダイシング後の半導体ウ
ェハを基板上に固定するダイボンディング工程における
、ボンディング面に対する新規な処理方法に関するもの
であり、特にＧａＡｓ等を材料とす。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. More specifically, the present invention relates to a novel method for treating a bonding surface in a die bonding process for fixing a diced semiconductor wafer loaded with circuits onto a substrate, particularly when the bonding surface is made of GaAs or the like.
る化合物半導体のボンディングについて有効な方法であ
る。This is an effective method for bonding compound semiconductors.
従来の技術
ダイボンディングとは、回路を形成された半導体ウェハ
を分割して作製した半導体チップを、セラミックパッケ
ージやリードフレーム等のグイパッド上の所定の位置に
固定する技術をいう。これによって、半導体チップはパ
ッケージと機械的および電気的に接続される。BACKGROUND ART Die bonding is a technique for fixing semiconductor chips, which are manufactured by dividing a semiconductor wafer on which a circuit has been formed, to a predetermined position on a support pad such as a ceramic package or a lead frame. This mechanically and electrically connects the semiconductor chip to the package.
ダイボンディングの手法としては、Ａｕ−３ｉ共晶合金
法、はんだ接着法、樹脂接着法に大別できる。Die bonding methods can be broadly classified into Au-3i eutectic alloy method, solder bonding method, and resin bonding method.
Ａｕ−３ｉ共晶合金法は、Ａｕ−３ｉ共品合金の融点が
３７０℃と比較的低いことを利用しており、Ａｕめっき
したグイパッド上にチップの裏面を押し付けながら不活
性雰囲気中で４００℃前後に加熱して両者を接着する方
法である。この方法は、機械的にも、また電気的にも良
好な接着状態が得られるので、現在量も広く利用されて
いる方法である。The Au-3i eutectic alloy method takes advantage of the fact that the melting point of the Au-3i eutectic alloy is relatively low at 370°C. This is a method of bonding the two together by heating them back and forth. This method is currently widely used because it provides good adhesion both mechanically and electrically.
これに対して、はんだ接着法は、接着剤としてｐｂ−３
ｎ、 Ａｕ−Ｇｅ、 Ａｕ−３ｉ、 Ａｕ−３ｎ等のろ
う材を用いる方法である。この場合、作業温度は２００
乃至４００℃の範囲にある。この方法では、半導体チッ
プの裏面を予めＮｉ −Ａｕ、 Ｔｉ −Ｎｉ−Ａｕ等
でメタライズしてろう材との馴染みをよくする付加的な
操作が必要である。On the other hand, the solder bonding method uses PB-3 as the adhesive.
This method uses brazing materials such as Au-Ge, Au-3i, and Au-3n. In this case, the working temperature is 200
The temperature ranges from 400°C to 400°C. This method requires an additional operation in which the back surface of the semiconductor chip is previously metallized with Ni-Au, Ti-Ni-Au, etc. to improve compatibility with the brazing material.
しかしながら、この方法の長所は、基板と半導体チップ
との熱膨張率の違いにより生じる熱歪がはんだ層に吸収
されるので、半導体チップの面積が増大してもチップの
破損が生じにくいことにある。従って、近年の集積回路
の大規模化、並びにＡｕの値段の高騰等に伴って、その
実用化が注目されている。However, the advantage of this method is that the thermal strain caused by the difference in thermal expansion coefficient between the substrate and the semiconductor chip is absorbed by the solder layer, so chip damage is less likely to occur even if the area of the semiconductor chip increases. . Therefore, with the recent increase in the scale of integrated circuits and the rise in the price of Au, its practical application is attracting attention.
樹脂接着法（ま、Ａｇ等の金属粉末を含有する樹脂を接
着剤として半導体チップを固定する方法であり、上述の
２つの方法よりも更に新規なものであるが、接着剤の硬
化に時間がかかる等の問題を含んでおり、今後の研究が
待たれている。Resin bonding method (well, this is a method of fixing semiconductor chips using a resin containing metal powder such as Ag as an adhesive, and is more novel than the above two methods, but it takes time to harden the adhesive. These and other issues are involved, and future research is awaited.
これらダイボンディング技術における課題は、物理的並
びに化学的に安定した結合が得られることと、電気並び
に熱の良好な伝導性である。即ち、ダイボンディングは
、半導体チップが基板上に強固に固定されると共に、半
導体チップと基板とが良好な導電性を保ち、更に、半導
体チップ内で発生した熱が効率良く基板に伝導−放散さ
れるようになされることが望ましい。The challenges in these die bonding techniques are to obtain a physically and chemically stable bond and to have good electrical and thermal conductivity. In other words, die bonding firmly fixes the semiconductor chip on the substrate, maintains good conductivity between the semiconductor chip and the substrate, and also allows heat generated within the semiconductor chip to be efficiently conducted and dissipated to the substrate. It is desirable that the
発明が解決しようとする問題点
ダイボンディングの不良のために、半導体チップが基板
から剥がれることが半導体装置として全く不良品である
ことはいうまでもなく、また、単に半導体チップと基板
との間に間隙が生じた場合でも、半導体チップから基板
への電気抵抗あるいは熱抵抗が高くなり、半導体装置の
誤動作、短寿命化を招くことになる。従って、ダイボン
ディングによる半導体チップの接着は与得る限り強固で
あることが望ましい。Problems to be Solved by the Invention Needless to say, if a semiconductor chip peels off from a substrate due to defective die bonding, it is a completely defective semiconductor device. Even if a gap occurs, the electrical resistance or thermal resistance from the semiconductor chip to the substrate increases, resulting in malfunction and shortened life of the semiconductor device. Therefore, it is desirable that the bonding of semiconductor chips by die bonding be as strong as possible.
そこで、本発明の目的は、上記従来のダイボンディング
技術の課題から、特に化合物半導体チップの有効なダイ
ボンディング方法を実現することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the conventional die bonding techniques described above and to realize an effective die bonding method for compound semiconductor chips in particular.
問題点を解決するための手段
即ち、本発明に従い、ＧａＡｓ等の化合物半導体チップ
の裏面を洗浄する工程と、該半導体チップの裏面をメタ
ライジング処理する工程と、さらに該半導体チップを基
板上に接着するダイボンディング工程とを少なくとも含
む半導体装置を製造する方法において、前記化合物半導
体の裏面を、混合比が１：１：１０の硫酸：過酸化水素
：純水の混合物によって洗浄することを特徴とする半導
体装置の製造方法が提供される。Means for solving the problem, namely, according to the present invention, a step of cleaning the back side of a compound semiconductor chip such as GaAs, a step of metallizing the back side of the semiconductor chip, and further bonding the semiconductor chip on a substrate. A method for manufacturing a semiconductor device including at least a die bonding step, characterized in that the back surface of the compound semiconductor is cleaned with a mixture of sulfuric acid: hydrogen peroxide: pure water in a mixing ratio of 1:1:10. A method of manufacturing a semiconductor device is provided.
作用
本発明の方法は、半導体チップ裏面の洗浄工程にその主
要な特徴を有している。Operation The method of the present invention has its main feature in the step of cleaning the back surface of a semiconductor chip.
即ち、半導体チップのダイボンディングに先立って、従
来はアセトン、イソプロピルアルコール等の有機洗浄液
、あるいは塩酸等の洗浄液を用いていた。That is, prior to die bonding of semiconductor chips, conventionally, an organic cleaning liquid such as acetone or isopropyl alcohol, or a cleaning liquid such as hydrochloric acid has been used.
これに対して、本発明に従う方法においては、硫酸と過
酸化水素と純水との混合物によって行われる。In contrast, the method according to the invention is carried out with a mixture of sulfuric acid, hydrogen peroxide and pure water.
このとき、硫酸と過酸化水素と純水との混合比は１：１
１０であることが極めて有利である。At this time, the mixing ratio of sulfuric acid, hydrogen peroxide, and pure water is 1:1.
10 is very advantageous.
このような本発明の方法を用いると、チップ裏面とメタ
ライジング層との接着性が極めて高くなる。When such a method of the present invention is used, the adhesiveness between the back surface of the chip and the metallizing layer becomes extremely high.
また、この場合、半導体チップの裏面に直接形成される
メタライジング層をＴ１によって形成する゛ことが好ま
しいことが見出されている。Furthermore, in this case, it has been found that it is preferable to form the metallizing layer directly on the back surface of the semiconductor chip by T1.
尚、このメタライジング層とろう材との馴染みを更に良
くするために、ＴＩのメタライジング層の表面に更にＡ
ｕを蒸着することも好ましい。In addition, in order to further improve the compatibility between this metallizing layer and the brazing filler metal, A is added to the surface of the TI metallizing layer.
It is also preferable to vapor deposit u.
実施例
以下に添付の図面を参照して、本発明をより具体的に詳
述するが、以下に示すものは本発明の１実施例に過ぎず
、本発明の技術的範囲を何等限定するものではない。EXAMPLES The present invention will be described in more detail below with reference to the accompanying drawings, but what is shown below is only one example of the present invention, and does not limit the technical scope of the present invention in any way. isn't it.
第１図は、ダイボンディング工程後の半導体チップと基
板との構成を示すと同時に、その接着強度を調べるため
の試験方法を概略的に示したものである。FIG. 1 shows the structure of a semiconductor chip and a substrate after the die bonding process, and at the same time schematically shows a test method for examining the adhesive strength.
半導体チップ１は、その裏面をＴｉによってメタライズ
され、更にこのメタライジング層２と基板３とがろう材
４によって接着されている。これは、はんだ接着法によ
り基板に固定された半導体チップの一般的な構成であり
、本実施例では、本発明の方法と従来の方法とにより作
製したものを各々用意し、それぞれについてダイシア強
度を測定した。The back surface of the semiconductor chip 1 is metallized with Ti, and the metallized layer 2 and the substrate 3 are bonded together using a brazing material 4. This is a general configuration of a semiconductor chip fixed to a substrate by a solder bonding method, and in this example, chips manufactured by the method of the present invention and a conventional method were prepared, and the die shear strength was evaluated for each. It was measured.
本発明に従って作製した半導体装置は、ＧａＡｓ基板上
に素子を形成した半導体回路であり、チップの裏面をグ
ラインディング処理した後に、硫酸と過酸化水素水と純
水とをｌ：１：１０の比で混合した洗浄剤によって、２
５℃で１分間洗浄した。洗浄後のチップ裏面に、メタラ
イジング層として８００への厚さまでＴ１を蒸着し、更
にＡｕを約５．００ＯＡの厚さまで蒸着した。こうして
メタライジング層を備えた半導体チップを、Ａｕ−２０
Ｓｎをろう材としてはんだ接着法によりダイボンディン
グした。The semiconductor device manufactured according to the present invention is a semiconductor circuit in which elements are formed on a GaAs substrate, and after grinding the back side of the chip, sulfuric acid, hydrogen peroxide solution, and pure water are mixed in a ratio of 1:1:10. The cleaning agent mixed with
Washed at 5°C for 1 minute. On the back surface of the chip after cleaning, T1 was deposited as a metallizing layer to a thickness of about 800 Å, and Au was further deposited to a thickness of about 5.00 OA. In this way, the semiconductor chip with the metallizing layer is made of Au-20
Die bonding was performed by a solder bonding method using Sn as a brazing material.
また、上述の実施例と比較するために、同様のＧａＡｓ
チップを、従来の方法と同様に塩酸で洗浄した後、メタ
ライジング層としてＴｉ並びにＡｕをこの順序で蒸着し
、更に、八ｕ−３ｎ （２Ｑｗｔ％）をろう材としては
んだ接着した。In addition, for comparison with the above-mentioned example, similar GaAs
After cleaning the chip with hydrochloric acid in the same manner as in the conventional method, Ti and Au were deposited in this order as a metallizing layer, and 8U-3N (2Qwt%) was further soldered as a brazing material.
尚、上述の１つの半導体装置を形成するために用いた半
導体チップは、共に１．０ｍｍ平方で厚さ０．４５ｍｍ
の同一寸法のチップを用いた。The semiconductor chips used to form one of the semiconductor devices mentioned above are both 1.0 mm square and 0.45 mm thick.
Chips with the same dimensions were used.
このようにして作製した半導体装置において、第１図に
示すように、半導体チップ１の側面から荷重をかけ、チ
ップが基板から剥がれ始めたときの負荷荷重を測定した
。In the semiconductor device manufactured in this way, as shown in FIG. 1, a load was applied from the side surface of the semiconductor chip 1, and the applied load was measured when the chip started to peel off from the substrate.
第２図は、上述のようにして作製したいくつかの半導体
装置に対して、ダイシア強度を測定した結果をプロット
したグラフである。FIG. 2 is a graph plotting the results of measuring die shear strength for several semiconductor devices manufactured as described above.
第２図にも見られるように、本発明の方法に従って作製
された半導体装置では、最も低いダイシア強度を示した
場合でも、従来の方法による半導体装置の平均値を上回
っている。また、本発明の方法に従って作製された半導
体装置の平均ダイシア強度は、従来の方法によるものの
最大強度を上回っている。As can be seen in FIG. 2, even when the semiconductor device manufactured according to the method of the present invention exhibits the lowest die shear strength, it exceeds the average value of semiconductor devices manufactured using the conventional method. Further, the average die shear strength of the semiconductor device manufactured according to the method of the present invention exceeds the maximum strength of the semiconductor device manufactured according to the conventional method.
尚、第２図中の〔σ〕はプロットした値の偏差を示し、
本発明の方法に従う半導体装置のダイシア強度が、実質
的に常に従来方法によるものを上回っていることを示し
ている。In addition, [σ] in Figure 2 indicates the deviation of the plotted values,
It is shown that the die shear strength of semiconductor devices according to the method of the invention substantially always exceeds that according to the conventional method.
発明の効果
以上詳述のように、本発明に従って作製された半導体装
置は、そのダイシア強度が極めて高く、ダイボンディン
グ処理における機械的安定性を高いレベルで達成するこ
とができる。Effects of the Invention As detailed above, the semiconductor device manufactured according to the present invention has extremely high die shear strength and can achieve a high level of mechanical stability during die bonding processing.
また、この方法は、はんだ接着法によるダイボンディン
グ処理の有する特徴を一切損なうことがなく、はんだ接
着法の利点をより有利に適用することを可能とする。Moreover, this method does not impair any of the features of the die bonding process using the solder bonding method, and makes it possible to apply the advantages of the solder bonding method more advantageously.
第１図は、本発明の方法を適用し得る半導体装置の構成
並びにその機械的な安定性の評価方法を概略的に示すも
のであり、
第２図は、本発明の方法に従って作製された半導体装置
と従来の方法に従って作製された半導体装置のダイシア
強度をプロットしたグラフである。
〔主な参照番号〕
１・・・半導体チップ、
２・・・メタライジング層、
３・・・基板、
４・・・ろう材、
５・・・ダイシア強度測定用の工具
１・・・・半導体チップ
２・・・メタライジ゛ング眉
３・・・基板
４・・・・ろう材
５・・・・工其
第２図
洗浄FIG. 1 schematically shows the structure of a semiconductor device to which the method of the present invention can be applied and a method for evaluating its mechanical stability. FIG. 2 shows a semiconductor device manufactured according to the method of the present invention. 3 is a graph plotting the die shear strength of the device and a semiconductor device manufactured according to a conventional method. [Main reference numbers] 1... Semiconductor chip, 2... Metallizing layer, 3... Substrate, 4... Brazing metal, 5... Tool for measuring die shear strength 1... Semiconductor Chip 2... Metallizing eyebrow 3... Substrate 4... Brazing material 5... Process Figure 2 Cleaning
Claims (3)
半導体チップの裏面をメタライジング処理する工程と、
さらに該半導体チップを基板上に接着するダイボンディ
ング工程とを少なくとも含む半導体装置の製造方法にお
いて、 前記半導体チップ裏面のメタライジング処理に先立って
、該半導体チップの裏面を、混合比が１：１：１０の硫
酸：過酸化水素水：純水の混合物によって洗浄すること
を特徴とする半導体装置の製造方法（但し、硫酸は９６
％水溶液、過酸化水素水は３１％の濃度である）。(1) a step of cleaning the back side of the compound semiconductor chip; a step of metallizing the back side of the semiconductor chip;
Furthermore, in the method of manufacturing a semiconductor device, which includes at least a die bonding step of bonding the semiconductor chip onto a substrate, prior to metallizing the back surface of the semiconductor chip, the back surface of the semiconductor chip is coated at a mixing ratio of 1:1: A method for manufacturing a semiconductor device characterized by cleaning with a mixture of sulfuric acid: hydrogen peroxide and pure water (however, sulfuric acid is 96%
% aqueous solution, hydrogen peroxide solution has a concentration of 31%).
を搭載した化合物半導体チップであることを特徴とする
特許請求の排気第１項に記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the compound semiconductor chip is a compound semiconductor chip in which a circuit is mounted on a GaAs substrate.
タライジング層のうち、少なくとも該半導体チップの裏
面に直接形成される層がＴｉによるものであることを特
徴とする特許請求の範囲第１項または第２項に記載の半
導体装置の製造方法。(3) Among the metallizing layers formed on the back surface of the semiconductor chip after cleaning, at least the layer directly formed on the back surface of the semiconductor chip is made of Ti. A method for manufacturing a semiconductor device according to item 1 or 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28990386A JPS63142638A (en) | 1986-12-05 | 1986-12-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28990386A JPS63142638A (en) | 1986-12-05 | 1986-12-05 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63142638A true JPS63142638A (en) | 1988-06-15 |
Family
ID=17749263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28990386A Pending JPS63142638A (en) | 1986-12-05 | 1986-12-05 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63142638A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02210830A (en) * | 1989-02-10 | 1990-08-22 | Matsushita Electric Ind Co Ltd | Surface treatment method of gaas substrate |
| WO1996026808A1 (en) * | 1995-03-01 | 1996-09-06 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Metallised under-layer for (soldering) filler materials |
| KR101055491B1 (en) * | 2009-05-26 | 2011-08-08 | 주식회사 네패스 | Semiconductor package and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5633836A (en) * | 1979-08-29 | 1981-04-04 | Fujitsu Ltd | Patterning method of gaas thermal oxide film |
| JPS6156422A (en) * | 1984-08-28 | 1986-03-22 | Nec Corp | Semiconductor device |
-
1986
- 1986-12-05 JP JP28990386A patent/JPS63142638A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5633836A (en) * | 1979-08-29 | 1981-04-04 | Fujitsu Ltd | Patterning method of gaas thermal oxide film |
| JPS6156422A (en) * | 1984-08-28 | 1986-03-22 | Nec Corp | Semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02210830A (en) * | 1989-02-10 | 1990-08-22 | Matsushita Electric Ind Co Ltd | Surface treatment method of gaas substrate |
| WO1996026808A1 (en) * | 1995-03-01 | 1996-09-06 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Metallised under-layer for (soldering) filler materials |
| KR101055491B1 (en) * | 2009-05-26 | 2011-08-08 | 주식회사 네패스 | Semiconductor package and manufacturing method thereof |
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