JPH0927498A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0927498A JPH0927498A JP17507295A JP17507295A JPH0927498A JP H0927498 A JPH0927498 A JP H0927498A JP 17507295 A JP17507295 A JP 17507295A JP 17507295 A JP17507295 A JP 17507295A JP H0927498 A JPH0927498 A JP H0927498A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- electrode
- semiconductor device
- wafer
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、はんだ電極を有する半
導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a solder electrode.
【0002】[0002]
【従来の技術】半導体装置をリードフレームや回路基板
に実装する方法としては、接着剤、導電性接着剤(例え
ば、Agペースト)を用いたり、AuSnなどの低融点
金属を裏面電極として形成し、加熱溶融させ半導体装置
を固定し(特開平2−260671)、次に、金、アル
ミ等を利用したワイヤボンディング法により配線が行わ
れるのが一般的である。一方、近年、ワイヤボンディン
グ法より信頼性が高く、工程も簡単で生産性に優れる方
法として、半導体装置と回路基板(例えば、プリント基
板)をはんだを用いて接合する方法も開発されている。
この方法は、半導体装置に形成された電極上にはんだバ
ンプを形成する。半導体装置ははんだバンプと、回路基
板上に形成されたはんだで表面を覆った配線電極とが接
触するように回路基板上に設置される。その後、約20
0℃程度で熱処理(リフロー工程)を行って、はんだ付
けし、半導体と回路基板を電気的、物理的に接合する。2. Description of the Related Art As a method for mounting a semiconductor device on a lead frame or a circuit board, an adhesive, a conductive adhesive (for example, Ag paste) is used, or a low melting point metal such as AuSn is formed as a back electrode, It is general that the semiconductor device is fixed by heating and melting (JP-A-2-260671), and then wiring is performed by a wire bonding method using gold, aluminum or the like. On the other hand, in recent years, a method of joining a semiconductor device and a circuit board (for example, a printed board) using solder has been developed as a method having higher reliability than the wire bonding method, a simple process, and excellent productivity.
This method forms solder bumps on the electrodes formed on the semiconductor device. The semiconductor device is installed on the circuit board so that the solder bumps are in contact with the wiring electrodes whose surface is covered with solder formed on the circuit board. Then, about 20
A heat treatment (reflow process) is performed at about 0 ° C. and soldering is performed to electrically and physically join the semiconductor and the circuit board.
【0003】これらのはんだバンプは、半導体表面に形
成された下地金属電極(例えば、Au/Cu/Cr構造
など)の表面に、蒸着法、ディップ法などを用いてはん
だ層を形成し、熱処理を行ってはんだを一旦溶解させ、
はんだバンプを得る方法が知られている(特開平2−2
78743、特開昭61−141155)。これらの方
法は、電極ピッチが0.2mm、電極径は0.1mm程
度のパターンが形成できるが、それより微細なパターン
形成は困難である。メッキ法は比較的パターン精度が良
いが、はんだ層厚を厚くできない、層厚がばらつく、組
成がずれる等の欠点がある。また、電解メッキ法は、電
気的導通が必要で島状の電極には適用できない。従っ
て、集積回路(LSI)などの半導体装置では比較的チ
ップサイズが大きく、電極間隔を大きく取れる半導体装
置に適用されている。チップサイズが小さい発光ダイオ
ードやホール素子の様な磁電変換素子には、前記したワ
イヤボンディング法を用いるのが一般的である。この理
由は、チップサイズの小さい半導体装置はチップに分離
する前のウェーハ状態では、一つの素子内の電極および
隣の素子の電極との間隔もしくは電極面積が小さいた
め、前記のようなはんだ電極形成方法でははんだブリッ
ジなどの短絡や接合不良が多発するためである。In these solder bumps, a solder layer is formed on the surface of a base metal electrode (for example, Au / Cu / Cr structure) formed on the semiconductor surface by using a vapor deposition method, a dip method, or the like, and heat treatment is performed. Go and melt the solder once,
A method for obtaining a solder bump is known (Japanese Patent Laid-Open No. 2-2
78743, JP-A-61-1141155). These methods can form a pattern having an electrode pitch of 0.2 mm and an electrode diameter of about 0.1 mm, but it is difficult to form a finer pattern. The plating method has relatively good pattern accuracy, but has the drawbacks that the solder layer thickness cannot be increased, the layer thickness varies, and the composition shifts. Further, the electroplating method requires electrical conduction and cannot be applied to island-shaped electrodes. Therefore, the semiconductor device such as an integrated circuit (LSI) has a relatively large chip size and is applied to a semiconductor device in which an electrode interval can be made large. The wire bonding method described above is generally used for a magnetoelectric conversion element such as a light emitting diode or a Hall element having a small chip size. The reason for this is that in a semiconductor device having a small chip size, in the wafer state before being separated into chips, the distance between the electrode in one element and the electrode of an adjacent element or the electrode area is small, so that the solder electrode formation as described above is performed. This is because the method often causes short circuits such as solder bridges and defective joints.
【0004】また、電極間隔を大きくすると必要なチッ
プ面積が大きくなり、ウェーハ1枚から得られる素子の
数が減少し生産性を著しく低下させる。また、チップに
分離し、チップ間隔を拡大した後すなわち電極間隔を拡
大した後、はんだ電極を形成する方法はチップを個別に
取り扱うためハンドリングが非常に困難であり、実用化
されていない。Further, if the electrode interval is increased, the required chip area is increased, the number of elements obtained from one wafer is reduced, and the productivity is remarkably reduced. Further, the method of separating solder into chips and expanding the chip interval, that is, the method of forming the solder electrode after expanding the electrode interval is very difficult to handle because the chips are handled individually, and has not been put into practical use.
【0005】[0005]
【発明が解決しようする課題】従来のワイヤボンディン
グ法は、ボンディング時に超音波や機械的圧力を加える
ため半導体を損傷し劣化させる事や、ボンディング面で
の剥離、ワイヤの断線が生じることがあり信頼性が低
い。一方、従来のはんだ電極製造方法では、電極サイズ
を小さくして電極間隔を狭くすると、はんだの層厚分布
が大きくなったり、隣接する電極同士の短絡(ブリッ
ジ)が発生する。はんだの層厚分布は接合強度のばらつ
きを増大させる問題点があった。従来技術ではチップサ
イズの小さい半導体装置を製造する場合、ウェーハ状態
でのはんだ電極の形成が困難であり、素子に分離した後
はんだ電極を形成しなければならない。この場合、チッ
プ側面を保護する工程等が必要となり、工程が複雑化
し、チップの取扱いが困難で著しく生産性を低下させ
る。In the conventional wire bonding method, ultrasonic waves and mechanical pressure are applied at the time of bonding, which may damage and deteriorate the semiconductor, and may cause peeling on the bonding surface and wire breakage. It is not very popular. On the other hand, in the conventional solder electrode manufacturing method, when the electrode size is reduced and the electrode interval is reduced, the solder layer thickness distribution becomes large, or short-circuiting (bridge) between adjacent electrodes occurs. The layer thickness distribution of the solder has a problem of increasing the variation in the bonding strength. In the case of manufacturing a semiconductor device having a small chip size in the conventional technique, it is difficult to form a solder electrode in a wafer state, and it is necessary to form the solder electrode after separating the elements. In this case, a process for protecting the side surface of the chip is required, which complicates the process, makes it difficult to handle the chip, and significantly reduces the productivity.
【0006】これらの問題は、電極が光を吸収するため
電極面積を極力小さくする事が特性向上において必要で
ある発光ダイオード、受光素子などの光素子や、小さい
チップの中に4つの電極があり、電極間隔が狭いホール
素子などの磁電変換素子のような半導体装置に於いて特
に重大である。本発明の目的は、チップサイズが小さい
素子に於いても信頼性が高く、生産性の良いはんだ電極
を有する半導体装置を再現性よく製造することである。These problems are caused by the fact that the electrodes absorb light and therefore it is necessary to reduce the electrode area as much as possible in order to improve the characteristics. Therefore, there are four electrodes in a small chip such as a light emitting diode and a light receiving element. This is particularly important in semiconductor devices such as magnetoelectric conversion elements such as Hall elements having a narrow electrode interval. An object of the present invention is to manufacture a semiconductor device having a solder electrode having high reliability and high productivity even in an element having a small chip size with good reproducibility.
【0007】[0007]
【課題を解決するための手段】本発明者らは、前述の課
題を解決するため、鋭意研究した結果、半導体ウェーハ
上に形成した微細な金属電極パターン表面にのみ選択的
にはんだ粉末を付着させ得ることに着目し、本発明に到
った。本発明は複数個の素子を形成した半導体ウェーハ
を、個々の素子に分離することなくウェーハのまま処理
してはんだ電極を形成し、しかる後個々の素子に分離す
るものである。本発明で用いる半導体は、Si、Geや
化合物半導体に適用できる。化合物半導体は、GaA
s、InP、GaP、GaAlAs、GaNなどの III
−V族半導体やZnSeなどのII−VI族半導体が使用で
きる。半導体装置としては、電極面積が特性に大きな影
響を与える発光ダイオード、レーザーダイオード、受光
素子や、電極の間隔が狭いホール素子が最適であるが、
トランジスタ、ダイオードアレイ、LSI等にも適用で
きる。In order to solve the above-mentioned problems, the inventors of the present invention have conducted extensive studies and as a result, have made it possible to selectively attach solder powder only to the surface of a fine metal electrode pattern formed on a semiconductor wafer. The present invention has been achieved with a focus on obtaining. According to the present invention, a semiconductor wafer on which a plurality of elements are formed is processed as it is without separating into individual elements to form solder electrodes, and then separated into individual elements. The semiconductor used in the present invention can be applied to Si, Ge and compound semiconductors. Compound semiconductor is GaA
s, InP, GaP, GaAlAs, GaN, etc. III
II-VI group semiconductors such as -V group semiconductors and ZnSe can be used. As a semiconductor device, a light emitting diode, a laser diode, a light receiving element, or a hall element having a narrow electrode gap, whose electrode area greatly affects the characteristics, is most suitable.
It can also be applied to transistors, diode arrays, LSIs and the like.
【0008】半導体装置本体は、通常の方法で製造され
た半導体単結晶ウェーハ(例えばSi、GaAsなど)
に公知のイオン注入法やエピタキシャル成長法などを用
いて、機能を発生させる活性層を形成した後、電気的接
触を確保するための電極を形成したものである。半導体
の主機能面と接触する金属電極材質は、半導体に適した
ものを選択すれば良い。例えば、「最新 化合物半導体
ハンドブック」((株)サイエンスフォーラム発行)に
記載されている様な公知の技術が利用できる。金属電極
形成方法も公知の蒸着、スパッタ法などを利用できる。
但し、はんだとの濡れ性の悪い材質(例えば、Ti、
W)や、はんだに食われる材質(例えば、Au)の場合
は、その上にはんだとの濡れ性が良好ではんだ食われの
小さいCu、Niなどのはんだ下地金属を形成すれば良
い。また、これらのはんだ下地金属と半導体と接触する
金属とが、合金化し特性上問題がある場合は、半導体と
接触する金属と下地電極との間に高融点のバリア金属層
(例えばTi、Cr、W、Moなど)を形成すれば良
い。金属電極のパターン形成方法は、公知のフォトリソ
グラフィー法を用いれば良い。半導体表面に形成する保
護膜は、酸化珪素、窒化珪素などの無機膜、ポリイミド
などの有機膜もしくは半導体の酸化膜など一般に知られ
ている物を利用すれば良い。このようにして半導体ウェ
ーハ上に金属電極を備えた複数個の素子を形成する。The main body of the semiconductor device is a semiconductor single crystal wafer (eg, Si, GaAs, etc.) manufactured by a usual method.
In addition, a well-known ion implantation method or epitaxial growth method is used to form an active layer for generating a function, and then an electrode for ensuring electrical contact is formed. The metal electrode material that contacts the main functional surface of the semiconductor may be selected from materials suitable for the semiconductor. For example, known techniques such as those described in "Latest compound semiconductor handbook" (published by Science Forum Co., Ltd.) can be used. As the method for forming the metal electrode, known vapor deposition, sputtering method or the like can be used.
However, materials with poor wettability with solder (for example, Ti,
In the case of W) or a material that is eroded by solder (for example, Au), a solder base metal such as Cu or Ni that has good wettability with solder and has little solder erosion may be formed thereon. Further, when the solder base metal and the metal in contact with the semiconductor are alloyed and there is a problem in characteristics, a high melting point barrier metal layer (for example, Ti, Cr, or the like) is formed between the metal in contact with the semiconductor and the base electrode. W, Mo, etc.) may be formed. A known photolithography method may be used as a method for forming the pattern of the metal electrode. As the protective film formed on the semiconductor surface, a generally known material such as an inorganic film such as silicon oxide or silicon nitride, an organic film such as polyimide or an oxide film of a semiconductor may be used. In this way, a plurality of devices having metal electrodes are formed on the semiconductor wafer.
【0009】次に、金属電極表面の特定の部分に粘着性
を付与する方法は、表面の金属と作用して粘着性を発現
する化合物で処理すれば特に限定はない。その化合物と
しては、例えば、特開平7−30243等に開示されて
いるCu電極に対して強い粘着性を発現するベンゾトリ
アゾール系誘導体、ナフトトリアゾール系誘導体、イミ
ダゾール系誘導体、ベンゾイミダゾール系誘導体、メル
カプトベンゾチアゾール系誘導体、ベンゾチアゾール脂
肪酸系誘導体等を含む水溶液を用いる。前記水溶液の濃
度は酸性、好ましくはpH3〜5程度の微酸性に調整
し、濃度は0.05〜20重量%が好ましい。さらに銅
イオンを100〜1000ppm程度共存させると、粘
着性膜の生成速度、生成量などの生成効率が高まるので
好ましい。金属電極の処理方法は前記のように調整した
水溶液を、浸漬法、塗布法、スプレー法などの手段を用
いて金属露出部に接触させる。金属電極上でもはんだの
不要な部分はレジスト膜等で覆って、金属面を露出させ
ないようにしておく。処理温度は室温乃至60℃位の範
囲が良い。接触時間は5秒乃至5分間位の範囲で適宜選
択する。次に適宜溶媒による洗浄、乾燥を経れば金属露
出部にのみ粘着性が付与される。粘着性を付与された金
属電極表面にはんだ粉末を振りかけ付着させ、余分なは
んだを圧力空気で吹き飛ばしたり湿式洗浄などにより取
り除けば、金属電極表面の必要な部分だけにはんだ粉末
が残る。はんだ粉末は、一般的に使用されている共晶は
んだ、銀入りはんだ、ビスマス入りはんだ等で構わな
い。はんだ粉末の粒度も目的とするはんだ電極のはんだ
層厚に応じて10μm〜数百μmの間で適宜選択すれば
良い。その後、はんだを電極表面に加熱定着させて、微
量なはんだ粉末を取り除き、市販のフラックスを塗布後
加熱してはんだを溶解させれば金属電極部のみにはんだ
が付いたはんだ電極が形成される。電極パターンが微細
でない場合は、加熱定着の工程を除いても良い。次に、
通常のダイシングソーやスクライブ法などによりウェー
ハを切断し個別の素子に分離する。半導体素子は分離後
回路基板やリードフレームにダイボンドし、加熱しては
んだを溶解し接合する。Next, the method of imparting tackiness to a specific portion of the surface of the metal electrode is not particularly limited as long as it is treated with a compound that acts on the surface metal to develop tackiness. Examples of the compound include a benzotriazole derivative, a naphthotriazole derivative, an imidazole derivative, a benzimidazole derivative, and a mercaptobenzone which exhibit strong adhesion to a Cu electrode disclosed in JP-A-7-30243. An aqueous solution containing a thiazole derivative, a benzothiazole fatty acid derivative, or the like is used. The concentration of the aqueous solution is adjusted to be acidic, preferably slightly acidic with a pH of about 3 to 5, and the concentration is preferably 0.05 to 20% by weight. Further, coexistence of about 100 to 1000 ppm of copper ions is preferable because the production efficiency such as production rate and production amount of the adhesive film is enhanced. As the method of treating the metal electrode, the aqueous solution prepared as described above is brought into contact with the exposed metal portion by means of a dipping method, a coating method, a spray method or the like. Even on the metal electrodes, unnecessary portions of the solder are covered with a resist film or the like so that the metal surface is not exposed. The processing temperature is preferably in the range of room temperature to about 60 ° C. The contact time is appropriately selected within the range of 5 seconds to 5 minutes. Next, if appropriately washed with a solvent and dried, tackiness is imparted only to the exposed metal portion. If the solder powder is sprinkled and adhered to the surface of the metal electrode to which tackiness has been imparted, and excess solder is blown off with pressurized air or removed by wet cleaning or the like, the solder powder remains only on a necessary portion of the surface of the metal electrode. The solder powder may be a commonly used eutectic solder, silver-containing solder, bismuth-containing solder, or the like. The particle size of the solder powder may be appropriately selected from 10 μm to several hundreds of μm depending on the intended solder layer thickness of the solder electrode. After that, the solder is heated and fixed on the electrode surface, a trace amount of the solder powder is removed, commercial flux is applied, and then the solder is melted by heating to form a solder electrode in which the solder is attached only to the metal electrode portion. When the electrode pattern is not fine, the heat fixing step may be omitted. next,
The wafer is cut by a normal dicing saw or a scribing method to be separated into individual elements. After the semiconductor element is separated, it is die-bonded to a circuit board or a lead frame and heated to melt and bond the solder.
【0010】[0010]
【作用】本発明において、半導体ウェーハの金属電極表
面の所定の部分のみに粘着性を付与し、はんだ粉末を付
着させる事により、はんだの付着位置と付着量を高精度
に制御できる作用がある。In the present invention, the adhesion position and the adhesion amount of the solder can be controlled with high accuracy by imparting the adhesiveness only to the predetermined portion of the metal electrode surface of the semiconductor wafer and adhering the solder powder.
【0011】[0011]
【実施例】以下、本発明の内容を実施例を挙げて具体的
に説明する。 (実施例1)実施例としてGaAlAs発光ダイオード
用エピタキシャルウェーハに複数個のLED素子を作っ
た例を示す。図1に本ウェーハの平面図の一部を、図2
に図1のA−A’に沿った断面構造を示す。エピタキシ
ャルウェーハは面方位(100)のp型半絶縁性GaA
s基板に、液相エピタキシャル法にてZnドープのp型
GaAlAsクラッド層4を厚さ5μmに成長させ、そ
の上に活性層としてZnドープp型GaAlAs層2を
厚さ1μmに成長させ、Teドープのn型GaAlAs
クラッド層3を厚さ150μmに成長させて作成した。
その活性層2のAl混晶比は発光波長が660nmとな
るようAl0.35Ga0.65Asに調整した。p、nのクラ
ッド層3、4のAl混晶比は、この発光波長に対して透
明なAl混晶比としてある。EXAMPLES The contents of the present invention will be specifically described below with reference to examples. (Embodiment 1) As an embodiment, an example in which a plurality of LED elements are formed on an epitaxial wafer for a GaAlAs light emitting diode will be shown. A part of the plan view of this wafer is shown in FIG.
1 shows a sectional structure taken along line AA ′ of FIG. The epitaxial wafer has a plane orientation (100) of p-type semi-insulating GaA.
On the s substrate, a Zn-doped p-type GaAlAs clad layer 4 was grown to a thickness of 5 μm by a liquid phase epitaxial method, and a Zn-doped p-type GaAlAs layer 2 was grown to a thickness of 1 μm as an active layer thereon, and Te-doped. N-type GaAlAs
The clad layer 3 was formed by growing it to a thickness of 150 μm.
The Al mixed crystal ratio of the active layer 2 was adjusted to Al 0.35 Ga 0.65 As so that the emission wavelength was 660 nm. The Al mixed crystal ratio of the p and n clad layers 3 and 4 is an Al mixed crystal ratio transparent to this emission wavelength.
【0012】次にp型GaAs基板を、公知のアンモニ
ア−過酸化水素系エッチング液によりエッチング除去し
た。その後、p型GaAlAsクラッド層4の表面の、
n型電極形成部分である70μm×150μm、ピッチ
300μmの大きさの部分およびダイシングラインとな
る部分を残して、その他の部分をフォトリソグラフィー
によるレジスト材で保護した。また、裏面のn型クラッ
ド層3もレジスト材で保護した。次いでリン酸−過酸化
水素系エッチング液によりn型電極形成部分及びダイシ
ングライン部分のp型GaAlAsクラッド層4をエッ
チング除去した。次に、p型GaAlAsクラッド層4
の表面の300μmピッチで70μm×150μmの大
きさのn型電極形成領域以外の部分をフォトリソグラフ
ィーによるレジスト材で保護した。ウェーハを真空蒸着
装置にセットし、AuGe/Ti/Cu(厚さはそれぞ
れ、1000Å/1000Å/6000Å)からなるn
型電極材料を真空蒸着した。レジストを剥離し、リフト
オフ法でn型電極パタ−ン5aを形成した。再び、p型
GaAlAsクラッド層4の表面に300μmピッチで
70μm×150μmのp型電極領域以外をフォトリソ
グラフィーによるレジスト材で保護した。p型GaAl
Asクラッド層4の表面にAuBe/Ti/Cu(厚さ
はそれぞれ、1000Å/1000Å/6000Å)か
らなるp型電極材料を真空蒸着した。レジストを剥離
し、リフトオフ法でp型電極パタ−ン5bを形成した。
次に、窒素雰囲気下420℃で5分間アロイングをして
n型、p型ともオーミック電極を形成した。その上に感
光性ポリイミド樹脂7(旭化成工業(株)製PIMEL
シリ−ズ、ガラス転移点355℃)をスピンコーターで
均一に塗布した。フォトリソグラフィー法により電極領
域5a,5bとダイシングストリート部8以外の領域を
保護するようにパターンを形成した。樹脂を硬化させる
ために、窒素雰囲気で350℃、60分熱処理を行っ
た。ポリイミド樹脂の膜厚は、2μmであった。Next, the p-type GaAs substrate was removed by etching with a known ammonia-hydrogen peroxide type etching solution. After that, on the surface of the p-type GaAlAs cladding layer 4,
The n-type electrode formation part, 70 μm × 150 μm, pitch 300 μm, and the part to be the dicing line were left, and the other parts were protected with a resist material by photolithography. Further, the n-type clad layer 3 on the back surface was also protected by a resist material. Then, the p-type GaAlAs cladding layer 4 in the n-type electrode forming portion and the dicing line portion was removed by etching with a phosphoric acid-hydrogen peroxide-based etching solution. Next, the p-type GaAlAs cladding layer 4
The surface of the substrate was protected with a resist material by photolithography except for the n-type electrode formation region having a size of 70 μm × 150 μm with a pitch of 300 μm. The wafer is set in a vacuum evaporation system and is made of AuGe / Ti / Cu (thickness is 1000Å / 1000Å / 6000Å) n
The mold electrode material was vacuum deposited. The resist was peeled off, and the n-type electrode pattern 5a was formed by the lift-off method. Again, the surface of the p-type GaAlAs cladding layer 4 was protected with a resist material by photolithography except for the p-type electrode regions of 70 μm × 150 μm at a pitch of 300 μm. p-type GaAl
A p-type electrode material made of AuBe / Ti / Cu (thickness: 1000Å / 1000Å / 6000Å) was vacuum-deposited on the surface of the As clad layer 4. The resist was peeled off, and the p-type electrode pattern 5b was formed by the lift-off method.
Next, alloying was performed for 5 minutes at 420 ° C. in a nitrogen atmosphere to form ohmic electrodes for both n-type and p-type. On top of that, a photosensitive polyimide resin 7 (PIMEL manufactured by Asahi Kasei Corporation)
A series and a glass transition point of 355 ° C.) were uniformly applied with a spin coater. A pattern was formed by photolithography so as to protect the regions other than the electrode regions 5a and 5b and the dicing street portion 8. To cure the resin, heat treatment was performed at 350 ° C. for 60 minutes in a nitrogen atmosphere. The film thickness of the polyimide resin was 2 μm.
【0013】次に、ウェーハを酢酸によりpHを約4に
調整した2−ドデシルイミダゾ−ル(1wt%)水溶液
に45℃で5分間秒浸漬させ、その後、水洗、乾燥を行
い、Cu電極5a,5bの表面に粘着性を付与した。平
均粒径25μmの共晶はんだ粉末を振りかけ、余分なは
んだを圧力空気で吹き飛ばした。その後、140℃で2
0分間はんだを電極表面に加熱定着させた。微量なはん
だ粉末をブラシで取り除き、市販の水溶性フラックスを
塗布後、230℃で1分間リフロー炉に入れはんだ粉末
を溶融した。Cu電極5a,5bの表面に厚さ約30μ
mの微細なはんだ電極パターン6a,6bが形成され
た。ウェーハを粘着シートに貼り付け、ダイシングソー
により300μmピッチで切断し発光半導体装置20と
した。分離後、発光半導体装置20を回路基板(プリン
ト基板)9の導電回路10の電極と発光半導体装置のは
んだ電極(6a,6b)とが接触するようにダイボンド
し、リフロ−炉で230℃で1分間加熱しはんだを溶融
し回路基板に接合した。この状態を図3に示す。Next, the wafer is immersed in an aqueous solution of 2-dodecyl imidazole (1 wt%) whose pH is adjusted to about 4 with acetic acid at 45 ° C. for 5 minutes, then washed with water and dried to form Cu electrodes 5a, The surface of 5b was made tacky. A eutectic solder powder having an average particle diameter of 25 μm was sprinkled, and excess solder was blown off with pressurized air. Then 2 at 140 ℃
The solder was heated and fixed on the electrode surface for 0 minutes. A small amount of solder powder was removed with a brush, and after applying a commercially available water-soluble flux, it was put in a reflow furnace at 230 ° C. for 1 minute to melt the solder powder. Thickness of about 30μ on the surface of Cu electrodes 5a, 5b
m fine solder electrode patterns 6a and 6b were formed. The wafer was attached to an adhesive sheet and cut with a dicing saw at a pitch of 300 μm to obtain a light emitting semiconductor device 20. After the separation, the light emitting semiconductor device 20 is die-bonded so that the electrodes of the conductive circuit 10 of the circuit board (printed circuit board) 9 and the solder electrodes (6a, 6b) of the light emitting semiconductor device are in contact with each other, and the die is bonded in a reflow oven at 230 ° C. for 1 hour. It was heated for a minute to melt the solder and bond it to the circuit board. This state is shown in FIG.
【0014】この試料200個について通電試験を実施
した。本方法で得られた発光半導体表示装置では短絡ま
たは断線の不良率は0%であった。本実施例では、Al
GaAs/GaAs系発光半導体装置を用いたが、他の
発光半導体装置でも同様な効果が得られた。An energization test was conducted on 200 samples. In the light emitting semiconductor display device obtained by this method, the defective rate of short circuit or disconnection was 0%. In this embodiment, Al
Although a GaAs / GaAs-based light emitting semiconductor device was used, similar effects were obtained with other light emitting semiconductor devices.
【0015】(比較例1)はんだ電極形成方法以外は、
実施例1と同じGaAlAs発光半導体装置を作った例
を示す。オーミック電極形成、ポリイミド保護膜形成ま
では、実施例1と同じである。ウェーハをはんだメッキ
浴に浸漬(ディップ法)し、Cu表面にはんだ層を形成
した。はんだ層厚は、約30μmであった。はんだ層形
成後、はんだブリッジが多数発生していた。以下実施例
1と同じ方法で回路基板に組み込んだ。この試料200
個について通電試験を実施した。本方法で得られた発光
半導体表示装置では短絡不良率は、16%、断線の不良
率は2%であった。(Comparative Example 1) Other than the method for forming solder electrodes,
An example in which the same GaAlAs light emitting semiconductor device as that of the first embodiment is manufactured will be shown. The process up to formation of the ohmic electrode and formation of the polyimide protective film is the same as in the first embodiment. The wafer was immersed in a solder plating bath (dip method) to form a solder layer on the Cu surface. The solder layer thickness was about 30 μm. After forming the solder layer, many solder bridges were generated. Then, it was incorporated into a circuit board in the same manner as in Example 1. This sample 200
An energization test was performed on each piece. The light emitting semiconductor display device obtained by this method had a short-circuit defect rate of 16% and a disconnection defect rate of 2%.
【0016】(実施例2)以下、本発明をホール素子に
適用した例を挙げて説明する。1枚の基板に複数個のホ
ール素子を作った。この平面配置図を図4に示す。また
図4のB−B’に沿った断面構造図を図5に示す。素子
形成後、単一素子に切断して使用する。(Embodiment 2) Hereinafter, an example in which the present invention is applied to a Hall element will be described. A plurality of Hall elements were made on one substrate. This plan layout is shown in FIG. Further, FIG. 5 shows a sectional structural view taken along the line BB ′ of FIG. After forming the element, it is cut into a single element for use.
【0017】比抵抗が約107 Ω・cm、面方位(10
0)の半絶縁性GaAs基板12上に、 70×140μ
mの十字型感磁部並びに入出力用電極6a,6bとなる
領域以外の領域をフォトリソグラフィーによるレジスト
材で保護し、エネルギー;180KeV、ドーズ量;3
×1012cm-2の条件でイオン注入法により29Si+を
選択注入した後、レジスト材を除去後、ヒ素圧雰囲気下
で800℃、30分間アニール処理を実施し、n型導電
層14を形成した。プラズマCVD法によりウェーハ表
面に反応温度300℃で酸化珪素膜13を0.15μm
の厚さに形成した。電極領域以外をレジスト材で覆い、
酸化珪素膜をフッ酸でエッチング後、金属電極材料とし
てAuGe(Ge:7.5%)/Ti/Cu(それぞれ
の厚さは、1000Å/1000Å/6000Å)を真
空蒸着した。リフトオフ法により電極パターン5a,5
bを形成した。この時のパターンは、400μm□内に
80×80μmの4つの金属電極が存在する。The specific resistance is about 10 7 Ω · cm, and the plane orientation (10
0) on the semi-insulating GaAs substrate 12 of 70 × 140 μ
The area other than the area of the cross-shaped magnetic sensitive portion of m and the input / output electrodes 6a and 6b is protected by a resist material by photolithography, energy: 180 KeV, dose: 3
After selectively implanting 29 Si + by the ion implantation method under the condition of × 10 12 cm −2 , the resist material is removed, and then annealing treatment is performed at 800 ° C. for 30 minutes in an arsenic pressure atmosphere to form the n-type conductive layer 14. Formed. A silicon oxide film 13 of 0.15 μm was formed on the surface of the wafer by plasma CVD at a reaction temperature of 300 ° C.
It was formed in thickness. Cover the area other than the electrode area with a resist material,
After etching the silicon oxide film with hydrofluoric acid, AuGe (Ge: 7.5%) / Ti / Cu (each thickness is 1000Å / 1000Å / 6000Å) was vacuum-deposited as a metal electrode material. Electrode patterns 5a, 5 by lift-off method
b was formed. The pattern at this time has four metal electrodes of 80 × 80 μm in 400 μm □.
【00018】窒素雰囲気下420℃で5分間アロイン
グをし、オーミック電極を形成した。その上に感光性ポ
リイミド(旭化成工業(株)製PIMELシリーズ、ガ
ラス転移点355℃)をスピンコーターで均一に塗布し
た。フォトリソグラフィー法により電極領域6a,6b
とダイシングストリート部8以外の領域を保護するよう
にパターンを形成した。樹脂を硬化させるために、窒素
雰囲気で350℃、60分熱処理を行った。ポリイミド
の膜厚は2μmであった。フッ酸により、ダイシングス
トリート8の酸化珪素膜13をエッチングした。Alloying was performed at 420 ° C. for 5 minutes in a nitrogen atmosphere to form an ohmic electrode. A photosensitive polyimide (PIMEL series manufactured by Asahi Kasei Kogyo Co., Ltd., glass transition point 355 ° C.) was uniformly applied thereon by a spin coater. Electrode regions 6a and 6b by photolithography method
A pattern was formed so as to protect the area other than the dicing street portion 8. To cure the resin, heat treatment was performed at 350 ° C. for 60 minutes in a nitrogen atmosphere. The film thickness of the polyimide was 2 μm. The silicon oxide film 13 on the dicing streets 8 was etched with hydrofluoric acid.
【0019】次に、ウェーハを酢酸によりpHを約4に
調整した2−ドデシルイミダゾール(1wt%)水溶液
に40℃で30秒浸漬させ、その後、水洗、乾燥を行
い、露出しているCu電極5a,5bの表面のみに粘着
性を付与した。次いで平均粒径50μmの共晶はんだ粉
末を振りかけ、余分なはんだを圧力空気で吹き飛ばし
た。その後、170℃で30秒間加熱しはんだを電極表
面に定着させた。微量なはんだ粉末をブラシで取り除
き、市販の水溶性フラックスを塗布後、230℃で1分
間リフロー炉に入れはんだ粉末を溶融した。Cu電極5
a,5bの表面に厚さ約30μmの微細なはんだ電極パ
ターン6a,6bが形成された。このように処理したウ
ェーハを粘着シートに貼り付け、ダイシングソーによ
り、ウェーハを400μmピッチで切断しホール素子1
5とした。分離後、ホール素子を回路基板(プリント基
板)9の電極と前記ホール素子のはんだ電極(6a,6
b)とが接触するようにダイボンドし、リフロー炉で2
30℃で1分間加熱しはんだを溶融し回路基板に接合し
た。この状態は図3と同様である。Next, the wafer is immersed in an aqueous solution of 2-dodecylimidazole (1 wt%) whose pH is adjusted to about 4 with acetic acid at 40 ° C. for 30 seconds, followed by washing with water and drying to expose the exposed Cu electrode 5a. , 5b was provided with tackiness only. Then, a eutectic solder powder having an average particle size of 50 μm was sprinkled, and excess solder was blown off with pressurized air. Then, it was heated at 170 ° C. for 30 seconds to fix the solder on the electrode surface. A small amount of solder powder was removed with a brush, and after applying a commercially available water-soluble flux, it was put in a reflow furnace at 230 ° C. for 1 minute to melt the solder powder. Cu electrode 5
Fine solder electrode patterns 6a and 6b having a thickness of about 30 μm were formed on the surfaces of a and 5b. The wafer thus treated is attached to an adhesive sheet, and the wafer is cut at a pitch of 400 μm with a dicing saw to cut the Hall element 1.
It was set to 5. After separation, the Hall element is connected to the electrodes of the circuit board (printed circuit board) 9 and the solder electrodes (6a, 6a) of the Hall element.
Die-bond so that it contacts with b), and use a reflow furnace for 2
It was heated at 30 ° C. for 1 minute to melt the solder and bond it to the circuit board. This state is the same as in FIG.
【0020】この試料200個について通電試験を実施
した。本方法で得られたホール素子では短絡または断線
の不良率は0%であった。本実施例では、GaAsホー
ル素子を用いたが、InSb、InAsを用いたホール
素子でも同様な効果が得られる。An energization test was conducted on 200 samples. In the Hall element obtained by this method, the defective rate of short circuit or disconnection was 0%. In this embodiment, the GaAs Hall element is used, but the same effect can be obtained with a Hall element using InSb or InAs.
【0021】(比較例2)はんだ電極形成方法以外は、
実施例2と同じGaAsホール素子を作った例を示す。
オーミック電極形成、ポリイミド保護膜形成までは、実
施例2と同じである。ウェーハをはんだメッキ浴に浸漬
(ディップ法)し、Cu表面にはんだ層を形成した。は
んだ層厚は、約30μmであった。はんだ層形成後、は
んだブリッジが多数発生していた。以下実施例2と同じ
方法で半導体装置を組み立てた。この試料200個につ
いて通電試験を実施した。本方法で得られたホール素子
では短絡不良率は、21%、断線の不良率は8%であっ
た。(Comparative Example 2) Other than the method for forming the solder electrode,
An example in which the same GaAs Hall element as in Example 2 is manufactured will be shown.
The process up to the ohmic electrode formation and the polyimide protection film formation is the same as in the second embodiment. The wafer was immersed in a solder plating bath (dip method) to form a solder layer on the Cu surface. The solder layer thickness was about 30 μm. After forming the solder layer, many solder bridges were generated. A semiconductor device was assembled in the same manner as in Example 2 below. An energization test was performed on 200 of these samples. The Hall element obtained by this method had a short circuit failure rate of 21% and a disconnection failure rate of 8%.
【0022】[0022]
【発明の効果】本発明により、半導体ウェーハ表面の微
細なパタ−ンにおいてもはんだ電極の形成が可能となっ
た。特に、小サイズの素子に対する効果が大きく、信頼
性、生産性を大幅に向上させた。According to the present invention, it is possible to form a solder electrode even in a fine pattern on the surface of a semiconductor wafer. In particular, it has a great effect on small-sized elements, and greatly improves reliability and productivity.
【図1】実施例1のウェーハの平面配置の一部分を例示
した図である。FIG. 1 is a view exemplifying a part of a plane arrangement of a wafer according to a first embodiment.
【図2】図1のウェーハのA−A’に沿った断面構造を
説明する図である。FIG. 2 is a diagram illustrating a cross-sectional structure along the line AA ′ of the wafer of FIG.
【図3】本発明の半導体装置をプリント基板に組込んだ
状態を示す図である。FIG. 3 is a view showing a state in which the semiconductor device of the present invention is incorporated in a printed board.
【図4】実施例2のウェーハの平面配置の一部分を示す
図である。FIG. 4 is a diagram showing a part of a plane arrangement of wafers according to a second embodiment.
【図5】図2のウェーハのB−B’に沿った断面構造を
説明する図である。5 is a diagram illustrating a cross-sectional structure along the line BB ′ of the wafer of FIG.
1 エピタキシャルウェーハ 2 活性層 3 n−クラッド層 4 p−クラッド層 5a 金属電極 5b 金属電極 6a はんだ電極 6b はんだ電極 7 ポリイミド樹脂 8 ダイシングストリート 9 プリント基板 10 導電回路 11 感磁部 12 半絶縁性GaAs基板 13 酸化珪素膜 14 n型導電層 20 半導体装置 1 Epitaxial Wafer 2 Active Layer 3 n-Clad Layer 4 p-Clad Layer 5a Metal Electrode 5b Metal Electrode 6a Solder Electrode 6b Solder Electrode 7 Polyimide Resin 8 Dicing Street 9 Printed Circuit Board 10 Conductive Circuit 11 Magnetic Field 12 Semi-insulating GaAs Substrate 13 Silicon Oxide Film 14 n-Type Conductive Layer 20 Semiconductor Device
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/92 603Z ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 21/92 603Z
Claims (4)
た後、該金属電極表面の所定の部分と粘着性付与化合物
を含む組成物とを反応させることにより粘着性を付与
し、粘着性付与部分にのみはんだ粉末を付着させた後、
加熱してはんだ粉末を溶融させ、金属電極表面にはんだ
層を形成した後、ウェーハを切断して半導体装置を分離
することを特徴とするはんだ電極を有する半導体装置の
製造方法。1. A metal electrode is formed on the surface of a semiconductor wafer, and then a predetermined portion of the surface of the metal electrode is reacted with a composition containing a tackifier compound to impart tackiness to the tackifier portion. After applying the solder powder only,
A method for manufacturing a semiconductor device having a solder electrode, which comprises heating to melt solder powder to form a solder layer on the surface of a metal electrode, and then cutting the wafer to separate the semiconductor device.
とする請求項1に記載の半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor is a compound semiconductor.
を特徴とする請求項1および請求項2に記載の半導体装
置の製造方法。3. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a light emitting diode.
特徴とする請求項1および請求項2に記載の半導体装置
の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a magnetoelectric conversion element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17507295A JP3755166B2 (en) | 1995-07-11 | 1995-07-11 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17507295A JP3755166B2 (en) | 1995-07-11 | 1995-07-11 | Manufacturing method of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0927498A true JPH0927498A (en) | 1997-01-28 |
JP3755166B2 JP3755166B2 (en) | 2006-03-15 |
Family
ID=15989748
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17507295A Expired - Fee Related JP3755166B2 (en) | 1995-07-11 | 1995-07-11 | Manufacturing method of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3755166B2 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1197742A (en) * | 1997-09-22 | 1999-04-09 | Nichia Chem Ind Ltd | Nitride semiconductor element |
US6428911B2 (en) * | 2000-04-17 | 2002-08-06 | Fujitsu Limited | Soldering method and soldered joint |
US6468582B1 (en) * | 1999-04-05 | 2002-10-22 | Matsushita Electric Industrial Co., Ltd. | Method of solder pre-coating and solder pre-coated circuit board |
US6595404B2 (en) | 2000-01-13 | 2003-07-22 | Hitachi, Ltd. | Method of producing electronic part with bumps and method of producing electronic part |
JP2005117035A (en) * | 2003-09-19 | 2005-04-28 | Showa Denko Kk | Flip-chip gallium-nitride-based semiconductor light-emitting element and method of fabricating same |
US7829910B2 (en) | 2005-01-31 | 2010-11-09 | Shin-Etsu Handotai Co., Ltd. | Light emitting device and method of fabricating light emitting device |
JP2013070092A (en) * | 2012-12-20 | 2013-04-18 | Asahi Kasei Electronics Co Ltd | Manufacturing method of magnetic device |
JP2021027073A (en) * | 2019-07-31 | 2021-02-22 | 日亜化学工業株式会社 | Light-emitting device |
-
1995
- 1995-07-11 JP JP17507295A patent/JP3755166B2/en not_active Expired - Fee Related
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1197742A (en) * | 1997-09-22 | 1999-04-09 | Nichia Chem Ind Ltd | Nitride semiconductor element |
US6468582B1 (en) * | 1999-04-05 | 2002-10-22 | Matsushita Electric Industrial Co., Ltd. | Method of solder pre-coating and solder pre-coated circuit board |
US6595404B2 (en) | 2000-01-13 | 2003-07-22 | Hitachi, Ltd. | Method of producing electronic part with bumps and method of producing electronic part |
SG99331A1 (en) * | 2000-01-13 | 2003-10-27 | Hitachi Ltd | Method of producing electronic part with bumps and method of producing elctronic part |
US6695200B2 (en) | 2000-01-13 | 2004-02-24 | Hitachi, Ltd. | Method of producing electronic part with bumps and method of producing electronic part |
US6428911B2 (en) * | 2000-04-17 | 2002-08-06 | Fujitsu Limited | Soldering method and soldered joint |
JP2005117035A (en) * | 2003-09-19 | 2005-04-28 | Showa Denko Kk | Flip-chip gallium-nitride-based semiconductor light-emitting element and method of fabricating same |
US7829910B2 (en) | 2005-01-31 | 2010-11-09 | Shin-Etsu Handotai Co., Ltd. | Light emitting device and method of fabricating light emitting device |
JP2013070092A (en) * | 2012-12-20 | 2013-04-18 | Asahi Kasei Electronics Co Ltd | Manufacturing method of magnetic device |
JP2021027073A (en) * | 2019-07-31 | 2021-02-22 | 日亜化学工業株式会社 | Light-emitting device |
Also Published As
Publication number | Publication date |
---|---|
JP3755166B2 (en) | 2006-03-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5338967A (en) | Semiconductor device structure with plated heat sink and supporting substrate | |
KR940001149B1 (en) | Chip bonding method of semiconductor device | |
KR100323657B1 (en) | How to Form Soul the Bump | |
JP4020977B2 (en) | Manufacturing method of light emitting device | |
US6284554B1 (en) | Process for manufacturing a flip-chip integrated circuit | |
JP3755166B2 (en) | Manufacturing method of semiconductor device | |
US3747202A (en) | Method of making beam leads on substrates | |
KR20080059590A (en) | Method for forming solder contacts on mounted substrates | |
US3986251A (en) | Germanium doped light emitting diode bonding process | |
US20110272792A1 (en) | Die backside standoff structures for semiconductor devices | |
JPH098082A (en) | Method of solder bonding | |
JPH08236808A (en) | Led and its manufacture | |
US20100133577A1 (en) | Method for producing electronic component and electronic component | |
US8735277B2 (en) | Methods for producing an ultrathin semiconductor circuit | |
JPH09148331A (en) | Semiconductor integrated circuit device and method for manufacturing the same | |
JP3826989B2 (en) | Semiconductor device and manufacturing method thereof | |
JP4140140B2 (en) | Metal bump manufacturing method | |
KR100233866B1 (en) | The structure of semiconductor chip for flip-chip and its manufacturing method | |
JPH10209154A (en) | Semiconductor device | |
JPH11191640A (en) | Electrode for semiconductor light-receiving and light-emitting element | |
JPH07273133A (en) | Manufacture of semiconductor device | |
JPS6394639A (en) | Manufacture of semiconductor device | |
JPH07106377A (en) | Manufacture of semiconductor device | |
JPH07226402A (en) | Tin adhesion gold bump for eutectic bonding | |
JPS61144095A (en) | Feeding of solder |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD13 | Notification of appointment of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7433 Effective date: 20050510 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20051212 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120106 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120106 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150106 Year of fee payment: 9 |
|
LAPS | Cancellation because of no payment of annual fees |