JPS63142449A - Patrol check system for control memory - Google Patents

Abstract

PURPOSE:To prevent the reduction in processing speed of a device body by performing the patrol check of a control memory to detect and restore soft errors while a waiting a processing request. CONSTITUTION:If a microinstruction for reading an attention register 10 in an idle loop is executed, the microinstruction is executed in two machine cycles. When the microinstruction is executed and a control signal 13 is outputted, a control signal obtained by logically differentiating the control signal 13 in one cycle is generated in a clock circuit 7. As the result, a control memory 1 is accessed by the address outputted from an address register 4 to set contents of the address to a pipeline register 2, and the parity check is performed, and the patrol check of the address is executed. Thus, a microprogram is loaded again from an external device if the parity error is detected.

Description

[Detailed Description of the Invention] [Summary] In a data processing device that executes a microprogram in response to a microprogram processing request from a host device, in order to reduce the decrease in reliability due to soft errors in the control memory, While waiting for a processing request (idle loop), a specific microinstruction is executed as a 2-cycle instruction, and in the first machine cycle, a patrol check is performed on the control memory to detect and recover from soft errors. It was designed to do so.

[Industrial application field]

The present invention relates to a patrol check method for detecting and recovering from soft errors in a control memory in a data processing device controlled by a microprogram.

With recent advances in semiconductor technology, control memory (WCS)
As the capacity of microprograms increases, and as the number of microprogram steps increases with the diversification of processing contents in data processing devices controlled by microprograms, the number of microprogram steps increases. The probability of occurrence of soft errors is also increasing, and effective soft error countermeasures are now required.

[Prior art and problems to be solved by the invention] FIG. 4 is a diagram illustrating a conventional control mechanism using a microprogram.

The data processing device controlled by the microprogram shown here is a type in which, for example, a display control device, when a processing request is activated from a host device, a microprogram corresponding to the activation content is executed. This device is in an idle loop state while waiting for activation from a higher level, and periodically updates the contents of the attention register (ATNIN) 10 to the arithmetic unit (ALU).
9 and executes a microinstruction that detects whether there is a processing request from the host device.

Here, when a processing request is received from the host device via the host bus 11, the attention register (ATNIN) 1
0 is set.

A processing request from the host device (10 cents in the attention register (ATNIN)) is recognized by the specific microinstruction, and a condition indicating that the processing request has been made activates the sequencer (SEQ) 5. By doing so, the microprogram branches to a specific address in the control memory (WCS) 1 and a microprogram corresponding to a processing request from the host device is executed.

In such a data processing device, the control memory (l
Conventionally, the following method has been used to detect and recover from the soft error of IC3)■.

■ By reading the microinstruction from the control memory, setting it in pipeline register (PLR) 2, and executing the microinstruction, the microinstruction is executed using, for example, a pipeline with two or more stages. The parity check circuit (PC) 3 detects soft errors before
Recovery is performed by reloading the microprogram into the control memory Cl4C3)1.

■ When a microinstruction is read from control memory (WCS) 1, the soft error is first detected and recovered, and then the read microinstruction is set in pipeline register (PLR) 2, and the microinstruction is executed. I do.

■ Do nothing while the microinstruction is being executed (during operation),
At regular intervals, the control memory (WCS) enters an operating mode for soft error detection and recovery.

Therefore, in the conventional methods that employ such a method, the method (2) has problems in that the control becomes complicated and the amount of hardware increases.

In the method (2), there is a problem in that the cycle time for the control memory (WCS) 1 becomes longer due to soft error detection and recovery.

In the method of ■, at appropriate intervals (for example, once a day),
There was a problem in that a trigger was required for patrol checking the control memory (WCS) 1.

In view of the above conventional drawbacks, the present invention provides a patrol check that does not significantly increase the amount of hardware, does not lengthen the cycle time of the control memory, and does not require a specific trigger signal for the patrol check. The purpose is to provide a method.

[Means for solving problems]

FIG. 1 is a diagram showing a configuration example of a patrol check method for a control memory according to the present invention.

In the present invention, in a data processing device that is controlled by a microprogram and executes the microprogram based on a processing request from a host device, a register (REG) for sending a patrol address to the control memory (WCS) 1 is provided.
4, a clock circuit 7 equipped with a clock thinning circuit for executing a specific microinstruction in two machine cycles, and means for detecting the specific microinstruction in an idle loop waiting for a processing request from the host device. 13 is provided, and when the detection means 13 detects the specific microinstruction to be executed while waiting for a processing request from the host device, the specific microinstruction is set as a two-cycle execution instruction, and the first half 1 The configuration is such that a patrol check of the control memory 1 is performed in each machine cycle.

[Effect]

That is, according to the present invention, in a data processing device that receives a microprogram processing request from a higher-level device and executes the microprogram, the processing request is While waiting (idle loop), a specific microinstruction is executed as a two-cycle instruction, and in the first machine cycle, a patrol check of the control memory is performed,
Since soft error detection and recovery are executed, there is no need to be aware of the timing of starting and stopping patrol from the host device, and since it is performed during the idle loop, there is no reduction in the processing speed of the device concerned. There is an effect that says no.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram showing a configuration example of the patrol check method for the control memory of the present invention, FIG. 2 is a time chart of the patrol check operation according to the present invention, and FIG. 2 is a flowchart of the operation of the data processing device in which the address register (
REG) 4. Clock circuit with thinning function added 7. Decoder (DEC) for starting the clock circuit
Output 13 is the means necessary to implement the invention. Note that the same reference numerals refer to the same objects throughout the plan.

Hereinafter, the patrol check method for the control memory (WCS) of the present invention will be explained with reference to FIG. 1 while referring to FIGS. 2 and 3.

Even if the present invention is implemented, the operation itself without reading out the control memory (WCS) 1 will not change in particular, so it will be omitted, and the description will focus here on the patrol check operation of the present invention.

As shown in the flowchart of FIG.
N) When the microinstruction that reads to is recognized as being in an idle loop state where it is being executed at a constant cycle and that there is a processing request from the higher-level device,
The microprocessing corresponding to the processing request is executed, and when the microprocessing is completed, the operation returns to the idle loop again.

The present invention focuses on the fact that a specific microinstruction (a microinstruction that reads the attention register (ATN IN) 10) is always executed during this idle loop, and
When the microinstruction is executed, the decoder (DEC)
Specific control signal (ATNIN) output from 8 1
3 is used to energize the clock circuit 7.

As shown in FIG. 1(b), the clock circuit 7 receives the control signal (8TNIN) from the decoder (DIEC) 8.
13, the control signal (ATNIN) 13 is logically differentiated as shown in the time chart of FIG.
■By outputting "ATNIN-1" for only the machine cycle, one clock (CKI) is output, and during that time other clocks (CR2, CR2) are blocked, and when the control signal "ATNIN-1" is , clock (CR
2, (J3) to return to normal operation.

That is, in the present invention, when a microinstruction to read the attention register (ATNIN) 10 is executed during an idle loop, the clock (CR2, CR2) is stopped once and the clock (CKI) is output instead. , the microinstruction is executed in two machine cycles.

Here, the clock (CKI) is a clock given only to patrol address register (REG) 4,
Clock (CK2. CK3) is sequencer (SEQ)
5. and pipeline register (PLR) 2. This is a normal clock supplied to an arithmetic unit (ALU), etc.

Therefore, as mentioned above, during the idle loop, certain microinstructions are executed and the control signal (^TNIN) 13
When the clock circuit 7 outputs the control signal (ATNIN) 13, a control signal (^TNIN-1) is generated by logically differentiating the control signal (ATNIN) 13 for one cycle.
l) and output the normal clock (CK2. CK3).
occlude.

As a result, the address output by address register (RUG) 4 is 11? When the wholesale memory (WC3) 1 is accessed, the contents of the address are set in the pipeline register (PLR) 2, a parity check is performed, and a patrol check is executed for the address.

If a parity error is detected during the patrol check, it can be recognized as a soft error and can be recovered by reloading the microprogram from an external device (not shown).

Since soft errors are intermittent errors, the frequency with which soft errors occur again during actual operation can be reduced.

Before the microinstruction for checking the presence or absence of a processing request from the above-mentioned upper-level device is executed, there is a processing request from the above-mentioned upper-level device, and the attention register (8TNIN) 10
(If set, the arithmetic unit (ALU) 9 determines a condition indicating that the microinstruction has been executed and a processing request from the host device has been read after the patrol check is completed. The sequencer (SEQ) 5 will be activated and the microprogram corresponding to the processing request from the host device will be executed, and it will take some extra time to execute the microprogram. In the data processing device, the number of steps of the microprogram corresponding to the processing request from the host device is sufficiently long compared to the patrol check time, so this does not become a factor that impedes the present invention.

As described above, the present invention provides an idle loop that waits for a processing request from the higher-level word U in a data processing device that executes a microprogram corresponding to the higher-level device when there is a processing request from the higher-level device. [1. Each time a specific micro-instruction for checking the presence or absence of a processing request is executed, the micro-instruction is made into a 2-cycle instruction, and in the first machine cycle, the control memory is accessed and the processing request is executed. The feature is that a patrol check is performed on the control memory.

〔Effect of the invention〕

As described above in detail, the control memory patrol check method of the present invention is implemented in a data processing device that receives a microprogram processing request from a higher-level device and executes a microprogram. In order to reduce the decrease in frequency, a specific microinstruction is executed as a 2-cycle instruction while waiting for the processing request (idle loop), and the first 1
Since the system performs a patrol check of the control memory during the machine cycle, detects soft errors, and performs recovery, starting the patrol from the host device,
In addition to not having to worry about the timing of stopping, there is also the effect that there is no reduction in the processing speed of the main unit because it is done during the idle loop.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of a patrol check method for a control memory according to the present invention. FIG. 2 is a time chart of the patrol check/strip operation according to the present invention. FIG. 3 is a flowchart of the operation of the data processing device to which the present invention is applied. FIG. 4 is a diagram illustrating a conventional control mechanism using a microprogram. It is. In the drawing, l is control memory (WCS). 2 is a pipeline register (PLR). 3 is a parity check circuit (PC). 4 is an address register (REG). 5 is a sequencer (SHQ), and 7' is a clock circuit. 7 is a clock circuit equipped with a clock thinning circuit. 8 is a decoder (DEC), 9 is an arithmetic unit (ALU)
. 10 is an attention register (ATNIN). 11 is an upper bus, and 12 is an internal bus. 13 is a decoder (DEC) output (ATNIN). CK1.2.3 are clocks. are shown respectively. Cb) Graduation 1 Figure 1 Hatrol nfin to 2 hatrol ℃ la 1 - 1 to go to knot 1 Rahii Noe Senji + 1 river 4th leap

Claims (1)

[Claims] In a data processing device that is controlled by a microprogram and executes the microprogram based on a processing request from a host device, a register (REG) for sending a patrol address to the control memory (1) ( 4), a clock circuit (7) equipped with a clock thinning circuit for executing a specific microinstruction in two machine cycles, and a clock circuit (7) that executes the specific microinstruction in an idle loop waiting for a processing request from the host device. and detecting means (13), and when the detecting means (13) detects the specific microinstruction to be executed while waiting for a processing request from the host device, the specific microinstruction is executed for two cycles. A patrol check method for a control memory, characterized in that the control memory (1) is controlled to perform a patrol check in one machine cycle in the first half of the command.