JP2564290B2 - Instruction restart processing method and apparatus - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an instruction restart processing method and apparatus in a microprogram control type data processing apparatus.

[Conventional technology]

Conventionally, re-execution of an instruction from the beginning has been generally used as a method of recovering from an intermittent malfunction of a processing device. Such instruction re-execution saves the contents of the register or the contents of the storage device destroyed by the instruction to be executed, as described in JP-B-47-48614, and saves the original register or memory when a malfunction is detected. I returned to the device and re-executed the instruction from the beginning. However, when the function of the instruction is enhanced, there is a problem that the information that must be saved increases and the processing speed decreases.

On the other hand, as the system architecture becomes more sophisticated,
As an instruction interruption factor, there is a missing page fault or the like that is inevitably generated for virtual memory support in addition to the malfunction, and when a missing page fault or the like occurs during the execution of such a high-performance instruction, When the instruction is restarted, it is difficult to re-execute the high-performance instruction from the beginning. To solve this problem, a restart method has been proposed in the middle of processing an instruction. USP 4488228 or JP-A-53-84540
In the mid-instruction restart method described in No. 6, when the instruction is interrupted, the contents at the time of the instruction interruption are saved, the saved information is recovered at the time of restart, and the processing is re-executed. However, there is a problem that the saved information at the time of interruption becomes large in the above-mentioned instruction midway restart method. In particular, in a pipeline type data processing device, it is necessary to save control information of a plurality of units, and the hardware for saving / restoring becomes large-scale and the saving / restoring time becomes long.

[Problems to be solved by the invention]

The conventional instruction midway restart method has a problem that a large amount of save information is required for restarting an instruction.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a restart processing method and apparatus with little saved information at the time of retry for intermittent malfunction or interruption of an instruction such as a mixing page fault.

[Means for solving problems]

The object is to have hardware capable of setting a restart point by designating a microprogram (microinstruction), that is, a register for saving the restart address of the control memory storing the microprogram and a save instruction for the save register by designating the microinstruction. Resuming point writing means, a resuming point valid flag for storing that the resuming point has been written in the save register, means for discriminating the contents of the resuming point valid flag by a micro instruction, and writing in the save register. It has the hardware to re-execute the processing from the embedded restart point, and when the interrupt instruction is restarted, instead of restarting from the interrupt point, the contents of the restart point valid flag are judged and the restart point is set. If it is, the processing is re-executed from the restart point of the save register, and if the restart point is not set, the instruction It is accomplished by re-executed from the switch.

[Action]

Since the restart point is specified by the microprogram, it can be set to a step that allows restart in advance, and if restart cannot be performed (the source register is updated after the restart point), the next restart point can be set. . In this way, the restart point is appropriately set in advance, and a flag indicating whether or not the restart point has been set is provided. Further, by discriminating the flag by the micro instruction, the correct restart is executed.

〔Example〕

FIG. 2 shows an example of the system configuration of the present invention, which includes a basic processing unit BPU1 for executing instructions and a cache memory.
The memory control unit MCU2 for address conversion and memory control, the main memory unit MS3 for storing instructions and data, the I / O adapter I / O ADPT4 for controlling the high-speed bus H-BUS9 and the low-speed bus L-BUS10 are components. There is.

 The operation of this system will be described below.

BPU1 is control bus 11, logical address bus 12, data bus
Access MCU2 through 13. The MCU 2 converts the logical address into a logical address and transfers the data corresponding to the physical address to the BPU 1 through the data bus 13 in the built-in cache memory (hereinafter abbreviated as cache). If there is no data in the cache, control bus 15,
MS3 is accessed through the physical address bus 16 and the data address 17. Further, the MCU2 reports the mixing page fault to the BPU1 through the signal line 14 when the corresponding page is not present on MS3 when performing the address conversion.

The I / O ADPT4 performs arbitration of transfer requests from the H-BUS 9 and the L-BUS 10, and accesses the MCU 2 through the control bus 18, physical address bus 19 and data bus 2. A high speed device such as a file device 6 is mainly connected to the H-BUS 9. In the present embodiment, the file control device 5 is connected to the H-BUS 9 and controls the file device 6 to control the DM.
A Transfer. An I / O control device 7 is connected to the L-BUS 10 and controls the I / O device 8 to perform DMA transfer.

 FIG. 3 shows an example of the internal configuration of BPU1.

The IF100 is a unit for prefetching instructions. It stores the prefetched instructions in an internal buffer and DA10
For each command request coming from 1 through the signal line 106, the command of the internal buffer is passed through the signal line 107. DA101 is IF10
The instruction passed from 0 is decoded and the address of the microprogram corresponding to the instruction of the execution unit E102 is generated and passed through the signal line 109. The DA 101 also passes the address of the instruction together with the address of the microprogram to the E 102 through the signal line 110. The DA 101 also calculates the effective address of the operand of the instruction and sends it through the signal line 111.
Hand it over to unit 102. E102 is an instruction execution unit of the microprogram control method, and executes an instruction by the address of the microprogram passed from DA101 and the effective address of the operand. When reading the operand, the E102 issues an access request to the MINF 103 through the control bus 113, the logical address bus 114, and the data bus 115. IF10
When 0 performs the instruction fetch, the instruction read access request is issued to the MINF 103 through the control bus 104, the logical address bus 105 and the data bus 116. The MINF 103 performs the aviation of the access request of the IF 100 and the E 102, and makes the access request to the MCU 2.

A pipeline for each operand is provided between DA101 and E102. When DA101 executes address calculation a plurality of times, DA101 and E102 process the same instruction. Further, the signal line 112 is an address signal line, and IF100, DA101
, For specifying the command after initialization.

FIG. 1 shows the internal structure of the E unit 102. A micro address selector (SEL) 201 is a selector for selecting a micro address to be executed next to the current micro instruction, and its input is the start address of the micro program passed from the DA 101 through the signal line 109, and the incrementer 205. Currently executing microprogram address +
1, a branch address from the control memory 204, a fixed address for exception processing, an address from the ALU 214 output bus 216, and the like. The micro address selected by the micro address selector 202 is CSAR (Control Storage Address Register) 20.
3 is sent to CS (Control Storage) 204. C
S204 is a control memory that stores a 64-bit x 8K step microprogram. The output of CS204 is read every BPU1 machine cycle, and MIR (Micro Instrument Register)
It is stored in 206 and transmitted to the internal hardware of BPU1 through the internal control bus 217 to read / write registers.
Controls the computing unit. The micro address selector 202 is controlled by the CS output branch designation signal and the Test Bit circuit 201. The Test Bit circuit 201 controls the micro address selector 202 by performing a condition determination according to a micro instruction through the CS output signal. As the input signal of the Test Bit circuit 201, the Ready signal of the micro address (signal 109) transmitted through the control line 108 and the effective address (signal 11)
1) Ready signal, operation result status signal from status register 215, MCU 2 transmitted through signal line 113
Access response signal to, a signal indicating that the CSAR 203 has been saved by the current instruction, and an effective restart address (check point address) has been set in the RPR 207. In addition, the Test Bit circuit 201 responds to the access response transmitted through the signal line 113 with a page fault.
The micro address selector is controlled so as to select a fixed address when an instruction interruption factor such as the above is included. An RPR (Restart Pointer Register) 207 is a register for saving the address of the CSAR 203 according to the designation of a micro instruction (a write signal is output from CS204), and when writing to this register, it is a valid bit. V2
08 is set. The operation unit of the execution unit 102 is composed of source buses 211 and 212, register files 213, ALU 214, status register 215, and destination bus 216. The register file 213 is composed of eight general-purpose registers, eight work registers and a stack pointer, and is selected by the output control signal 217 of the MIR206 and read or write is performed. ALU214 is Source Bus 211,21
The operation is executed by the data of 2 and is output to the destination bus 216 and the status of the operation result is set to SR215.
To be stored. The SEL 218 selects either the effective address passed from the DA 101 through the signal line 111 or the data of the destination bus 216, and the MAR (Memory Address Rewrite) is selected.
gister) 219 to output. The MAR 219 transmits the memory access address to the MINF 103 via the signal line 114.

The RDR 220 receives data from the MINF 103 through the signal line 115 and outputs it to the source bus 211. The WDR 221 receives the data of the day station bus 216, and sends the data to the MINF 103 through the signal line 115. Program counter PC2
10 stores the address on MS3 of the instruction being executed in E102, and is passed from SEL209. The SEL 209 selects the instruction address passed from the DA 101 through the signal line 110 and the input of the destination bus 216 and outputs it to the PC 210. The signal line 112 is a signal line for passing the next instruction execution address to the DA 101 and the IF 100 when initializing or executing a branch instruction.

FIG. 4 shows the processing of a microprogram, an error processing microprogram and an OS program when a mixing page fault occurs.

FIG. 4 (a) shows the flow when writing data to the memory in the instruction microprogram, and one step shows one micro instruction as it is. Step (1) 'WDR
← DRO 'indicates to set the contents of general register DRO in register file 213 to WDR221, and'RPRSET' indicates CSA.
It shows that the control storage address of R203 is set in RPR207 and V208 is set. "MWT" in step (2) indicates that write access to the memory is activated. 'MAW' in step (3) is a step waiting for a response to the write access activation in step (2). If this writing access causes a mixing page fault, the TEST BIT circuit 201 causes the microprogram address selector 209 to select a fixed address for error processing and jump to it. If a normal end response is returned, the error processing is not jumped and the process proceeds to the next step.

 The detailed contents of FIG. 4 (b) are shown in FIG.

One step in FIG. 5 is executed by a plurality of micro instructions. In step (1), whether the V208 is on or not is determined by the TEST BIT circuit 201, and if it is on, the address of the incrementer 205 is selected by the microprogram selector 202 and the process proceeds to step (2). If it is not turned on, the branch address of the CS output is selected by the micro address selector 202 and the process proceeds to step (6). Step (2) is a step for saving the current internal register. Step (3) specifies the address of the next instruction
Received from DA101 through signal line 110 and saved in the stack. Step (4) writes the identifier α for restarting in the middle at the time of restart. Step (6) indicates branching to the page fault processing of the OS program. Step (6) indicates saving the internal registers required to resume from the instruction fetch. Step (7) indicates that the identifier β for resuming from the instruction fetch is written when resuming.

In FIG. 4 (c), first, the process of transferring the page in which the page fault is generated from the file 6 to the MS3 (Page
Fault processing), and after completion, returns to the original instruction RTE
(Return From Exception) command is executed.

FIG. 6 shows the detailed contents of the RTE instruction. Step (1) determines whether the instruction is restarted midway (identifier = α) or the instruction fetch is restarted (identifier = β) based on the identifier on the stack. Step (2) reads the PC of the next instruction from the stack and instructs the IF100 and DA101 to start executing the instruction from the next instruction. At this time, the next instruction address is sent from E102 to IF100 and DA10 via the signal line 112.
Passed to 1. Step (3) is a step for recovering the internal register, and recovers the save registers other than RPR. Step (4) is a step of setting the save information of the RPR in the CSAR 203 and returning to the restart point of the interrupt instruction.
Step (5) is a step for recovering the saved information, and step (6) is a step for re-executing the interrupt instruction from the instruction fetch. The address of the interrupt instruction is the signal line 11.
Passed from E102 to IF100 and DA101 through 2. Further, in step (6), the E102 enters a command waiting state.

As described above, according to the present invention, it is possible to flexibly set the restart point different from the instruction break point, and by setting the restart point at an appropriate step, the save information of the execution unit E102 is minimized, and the instruction fetch , Unit IF100, decode & address calculation unit DA101 does not need to save the control information of the unit which pre-processes instruction execution.

〔The invention's effect〕

As described above, according to the present invention, saving information when an instruction interruption occurs is reduced, and particularly in a data processing device that performs pipeline processing of a plurality of units, saving of control information of a unit that performs preprocessing is unnecessary. . In addition, a wide range of retry processing for high-performance instructions can be realized without the need for large-scale hardware.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of hardware of the present invention. FIG. 2 is a system configuration example of the present invention. FIG. 3 is an internal block diagram of the data processing apparatus of the present invention. FIG. 4 is a schematic diagram of page fault processing in the embodiment of the present invention. Figure 5 shows an error (Page Faul
t) Flow chart showing the contents of the processing microprogram,
FIG. 6 is a flow chart showing the contents of the RTE instruction. 1 ... Basic processing unit (BPU), 2 ... Memory control unit (MCU), 3 ... Main memory (MS), 203 ... Control memory address register (CSAR), 204 ... Control memory (CS), 207 …
… Restart Point Register (RPR), 208 …… Restart Po
int Valid Bit (V).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tadaaki Bando 4026 Kujimachi, Hitachi City Hitachi, Ltd., Hitachi Research Laboratory (72) Shinichiro Yamaguchi 4026 Kujicho, Hitachi City Hitachi, Ltd. Hitachi Research Co., Ltd. In-house (56) Reference JP-A-57-164343 (JP, A) JP-A-53-32646 (JP, A) JP-A-53-84540 (JP, A)

Claims (5)

(57) [Claims] 1. A data processing device of a microprogram control system for executing an instruction read from a main storage device by a microprogram, wherein at least one of the instructions is in the instruction execution microprogram after the instruction is interrupted. Has a microinstruction that determines the read address of the microprogram for restarting, and when the execution of the instruction is interrupted, the microinstruction is executed and saved to hold the read address of the microprogram for restarting. Then, a graph indicating that the read address has been saved is set, and the process proceeds to error processing including retry processing for a malfunction or missing page fault processing, and when returning from the error processing to the execution of the instruction, Depending on the flag, the read-out address of the microprogram for restarting Check whether the address has been saved, and if it is saved, read the microprogram corresponding to the saved read address and start executing the instruction.If it is not saved, the interrupted instruction The instruction restart processing method is characterized in that the operation is started by a read operation from the main memory device. 2. A check microprogram is used to check whether or not the read address of the microprogram for restarting is saved by the flag. The instruction restart processing method according to item 1. 3. The read address of the saved microprogram is determined based on the address of the microprogram at that time by the designation of the microprogram during the execution of the microinstruction. The instruction restart processing method according to claim 1. 4. A data processing apparatus of a microprogram control system for executing an instruction read from a main memory by a microprogram, wherein a first read address of a control memory storing the microprogram is stored. Storage means, means for storing a read address of the control storage in the first storage means by designating a micro program, second storage for storing whether or not the read address is stored in the first storage means Means for determining the contents of the second storage means by a microprogram, means for reading the microprogram from the address stored in the first storage means and starting execution of the instruction, If an instruction interruption occurs during execution of the When the read address to be stored in the first storage means is designated and the error processing including the retry processing or the missing page fault processing for the malfunction is returned to the execution of the instruction, the contents of the second storage means are judged. If it is determined that the read address is stored in the first storage means and that it is stored in the second storage means, the execution of the read instruction of the microprogram is started from the read address, and the read address is If it is determined that the instruction is not stored in the first storage means but is stored in the second storage means, the interrupted instruction is started from the operation of reading again from the main storage device. An instruction restart processing device characterized by: 5. A first unit for reading an instruction from a main storage device to prepare for execution of the instruction, and a signal necessary for executing the instruction from the first unit to execute the instruction by a microprogram. In a microprogram-controlled data processing device in which at least the first and second units adopt a pipeline system, at least the first and second units are configured to execute the A first storage means for storing a read address of a microprogram of an instruction; and a second storage means for storing whether or not the first storage means stores the read address, When an interruption occurs, the error processing including the retry processing or the missing page fault processing for the malfunction is performed, and the error processing is recovered. In doing so, the contents of the second storage means are determined, and when it is determined that the read address is stored in the first storage means, the microprogram is read from the read address and the instruction is executed. The first unit is made to start from the operation of reading the instruction following the interruption instruction from the main storage device, and the read address for restart is stored in the first storage means. If not, the second unit
The instruction restart processing method, wherein the first unit is made to start the interrupt instruction again from a read operation from the main storage device.