JPS63140967A - Tester - Google Patents

Abstract

PURPOSE:To vary a test speed optionally and to set the optimum test speed for each pattern by varying a test clock and decision timing according to information from a pattern memory. CONSTITUTION:A test clock generating circuit 3 operates according to the contents of a test program stored in a program memory 1 and the contents of the pattern memory 2 and this test clock is supplied to a sample 7 to be tested. The output signal of the sample 7 is sent to a comparing circuit 6 and compared with an expected value, but the timing of the comparison is determined by a decision timing control circuit 5 at this time. Further, a clock control circuit 4 is operated according to information on a specific location of the pattern memory 2 to vary the phase of the test clock and the phase of the decision timing signal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to control of timing signals for pass/fail judgment in a tester that tests whether a test sample such as an LSI is a good product or a defective product. It is related to.

[Conventional technology]

Conventionally, the pass/fail judgment timing signal in this type of tester can be generated at any timing (phase) by programming, but test clock control information and expected value pattern information are not stored. The phase could not be controlled using the information in the pattern memory.

[Problem that the invention seeks to solve]

In the conventional pass/fail judgment timing signal generation method described above,
As long as the data on the program is not changed, the phase will not change, so the speed of other tests will be determined according to the part where the test speed must be slowed down the most, so even parts that can be tested at a faster speed will be slowed down. If the test speed is specified for each test pattern, if the judgment timing is changed in detail in the program to solve this problem, if the test speed is specified for each test pattern, the program alone will cause a problem. There are 9 drawbacks that could lead to this.

Of course, the test speed depends on the internal operating speed limit of the test sample itself, but it also depends on the environment in which the test sample and the tester's station controller are connected, such as wiring length and wiring impedance. Since the speed is often almost fixed, it is often necessary to test the speed by reducing it to a fraction of the operating limit, or even several hundredths in extreme cases.

[Means for solving problems]

The method of generating the pass/fail judgment timing signal of the present invention includes a circuit that can be controlled based on the designation on the pattern memory, in addition to the conventional circuit that is controlled by the designation on the program, for each pattern. It is now possible to specify the test speed.

Depending on this, for example, when the test clock is only input to the sample under test, the test clock frequency is increased to increase the test speed, and when the expected value of the pattern memory and the output of the sample are compared and judged, the judgment timing signal is used. By allowing sufficient time for the output to stabilize, the test speed can be effectively increased to the operating limit speed of the sample or tester.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which a test clock generation circuit operates according to the contents of a test program stored in a program memory 1 and the contents of a pattern memory 2, and this test clock is transmitted to a test sample 7. supplied to The output signal of No. 7 is sent to the comparison circuit 6 and compared with the expected value of No. 2. At this time, the timing of the comparison is determined by the output of the judgment timing control circuit 5 which operates in response to the signal No. 1. It is.

Furthermore, information on a specific position in pattern memory 2, for example 64
In a bottle tester, if the number of samples to be tested is 30 bottles, the clock control circuit 4 is operated based on the portion corresponding to the remaining pins (34 bins) or information in a specific memory provided for test control. , the test clock phase is changed and the determination timing signal phase is changed.

Figure 2 is a timing chart of the main parts of Figure 1,
In (a), when the test is performed at the same test speed, when the output signal of the sample changes (from H to L) in the n+1st pattern, the judgment will be made if the falling edge of the signal is slow due to the wiring capacitance of the measuring section, etc. This indicates that the result will be FAIL, (b)
indicates the case where the display information of the (n+1)th pattern is included (Similar to Fig. 31, even if the output signal of the sample is distorted, PASS judgment can be made by delaying the judgment timing.

Therefore, for example, if the number of test patterns is 1000 and the number of changing points of the sample output signal is 100, when one pattern = 2 ms, the total is 2000 m5, but excluding the f point, it is 1 m s. In this case, the total time can be significantly shortened to 1100ms.

〔Effect of the invention〕

As explained above, the present invention is configured so that the test clock and judgment timing can be changed according to the information in the putter 7 memory, so that the test speed can be changed arbitrarily, and the test speed can be adjusted according to the operating limits of the test sample and tester, the measurement environment, etc. The optimum test speed depending on the measurement conditions is, in extreme terms, 1
The effects that can be set for each pattern are very unique and can contribute to a significant reduction in test time.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention. FIG. 2 is a timing chart of the present invention, and (a) shows that FAIL4!4J is determined when carried out using the same test method as the conventional method.
(b) shows that a PASS determination is made by setting the speed at the severe signal point to be the same. DESCRIPTION OF SYMBOLS 1...Program memory, 2...Pattern memory, 3...Test clock generation circuit, 4...Clock control circuit, 5...Judgment timing control circuit, 6...
- Comparison circuit, 7...test sample.

Claims (1)

[Claims] A tester for testing the pass/fail of LSI etc., which has a function of arbitrarily varying the timing of comparing and determining the output of a test sample and the expected value in the pattern memory, depending on the information on the pattern memory.