JPS63131544A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63131544A JPS63131544A JP27819886A JP27819886A JPS63131544A JP S63131544 A JPS63131544 A JP S63131544A JP 27819886 A JP27819886 A JP 27819886A JP 27819886 A JP27819886 A JP 27819886A JP S63131544 A JPS63131544 A JP S63131544A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- semiconductor device
- metallic
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000000126 substance Substances 0.000 claims abstract description 4
- 239000012808 vapor phase Substances 0.000 claims description 2
- 125000002524 organometallic group Chemical group 0.000 claims 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 239000010936 titanium Substances 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- 229910052719 titanium Inorganic materials 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical class [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 3
- 239000011521 glass Substances 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- VSCWAEJMTAWNJL-UHFFFAOYSA-K aluminium trichloride Chemical compound Cl[Al](Cl)Cl VSCWAEJMTAWNJL-UHFFFAOYSA-K 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 150000002902 organometallic compounds Chemical class 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- MCULRUJILOGHCJ-UHFFFAOYSA-N triisobutylaluminium Chemical compound CC(C)C[Al](CC(C)C)CC(C)C MCULRUJILOGHCJ-UHFFFAOYSA-N 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に係り、より詳しくは半導体装置の
金属配線層の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to the structure of a metal wiring layer of a semiconductor device.
近年、半導体装置においては、微細加工技術の進歩によ
り、配線幅及び接続孔（フンタクト・ホール）等の微細
化が進んでいるが、それに伴う配線技術の問題が生じて
いる。2. Description of the Related Art In recent years, in semiconductor devices, advances in microfabrication technology have led to miniaturization of interconnect widths, contact holes, etc., but problems with interconnect technology have arisen as a result.
以下、従来の半導体装置の一実施例につき、図面を参照
して説明する。An example of a conventional semiconductor device will be described below with reference to the drawings.
第２図は、従来の半導体装置の一実施例の断面図を示す
。FIG. 2 shows a cross-sectional view of one embodiment of a conventional semiconductor device.
第２図に示す半導体装置は、半導体基板１０上に酸化膜
１２を介して多結晶シリコンミ！極１３が形成され、さ
らＫこの多結晶シリコン電極１３上にはリンガラス（Ｐ
ＳＧ）膜１４を介してスパッタ法により数パーセントの
シリコンを含有したアルミニウム（Ａｎ−８１）膜から
なる配線層２０が形成されている。The semiconductor device shown in FIG. A pole 13 is formed, and on this polycrystalline silicon electrode 13, a phosphor glass (P
A wiring layer 20 made of an aluminum (An-81) film containing several percent silicon is formed by sputtering via the SG) film 14.
また、酸化膜１１及びＰＳＧ膜１４には選択的に開孔部
（コンタクト・ホール）１５が設はラレ、半導体基板１
０内に形成された半導体層１１と配線層２０とが電気的
に接続されている。Further, openings (contact holes) 15 are selectively provided in the oxide film 11 and the PSG film 14, and the semiconductor substrate 1
The semiconductor layer 11 and the wiring layer 20 formed in the semiconductor layer 0 are electrically connected to each other.
しかしながら、前述の従来の半導体装置の構成によれば
、パターン幅の微細化が進むと、コンタクト・ホール１
５の７スペクト比が大きくなるため・第２図に示すよう
にコンタクト・ホール１５の側壁でのスパッタ法による
配線層２０の膜厚が薄くなり、配線層２０のステップ・
カバレージが悪化する。さらに、スパッタ法により形成
した配線層においては、多結晶シリコン電極１３による
段差部におけるＰＳＧ膜１膜上４上配線層２０の膜厚は
平坦部の膜厚に比べて薄くなる。これらのことから、配
線層の断線及び耐エレクトロ・マイグレーション性等の
配線の信頼性が低下するという問題点が生じる。However, according to the configuration of the conventional semiconductor device described above, as the pattern width becomes finer, the contact hole 1
As shown in FIG. 2, the thickness of the wiring layer 20 formed by sputtering on the side wall of the contact hole 15 becomes thinner, and the step ratio of the wiring layer 20 increases.
Coverage deteriorates. Furthermore, in the wiring layer formed by the sputtering method, the thickness of the wiring layer 20 on the PSG film 1 4 at the stepped portion formed by the polycrystalline silicon electrode 13 is thinner than that at the flat portion. These problems cause problems such as reduction in reliability of wiring such as disconnection of the wiring layer and resistance to electromigration.
そこで、本発明はこのような問題点を解決するもので、
その目的とするところは、配線金属層のステップ・カバ
レージが良好で耐エレクトロ・マイグレーション性等の
配線の信頼性を向上させた半導体装置を提供するところ
にあるＱ
〔問題点を解決するための手段〕
本発明の半導体装置は、複数の金属層の積層構造からな
る配線層を有する半導体装置において、前記複数の金属
層の少なくとも１層が、有機金属気相化学成長（Ｍｅｔ
ａｌｏｖｇａｎｉｏ Ｃｈｅｍｉｃａｌ’Ｖａｐｏｒ
Ｄｅｐｏｓｉｔｉｏｎ ％以下ＭＯ（！ＶＤと略記する
。）法により形成された金属層からなることを特徴とす
る。Therefore, the present invention aims to solve these problems.
The purpose is to provide a semiconductor device with good step coverage of the wiring metal layer and improved wiring reliability such as electromigration resistance. ] The semiconductor device of the present invention has a wiring layer having a stacked structure of a plurality of metal layers, in which at least one of the plurality of metal layers is grown by metal organic vapor phase chemical growth (Met).
alovganio Chemical'Vapor
Deposition % or less It is characterized by being made of a metal layer formed by the MO (abbreviated as !VD) method.
以下、本発明の代表的な実施例を図面を参照して説明す
る。Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.
第１図は、本発明による半導体装置の一実施例の断面図
を示す。FIG. 1 shows a cross-sectional view of an embodiment of a semiconductor device according to the present invention.
第１図に示す半導体装置は、半導体基板１０上に２００
〜１ｏｏｏｏＸの酸化膜１２を介して１０００〜５ｏｏ
ｏＸの多結晶シリコンＮ極１３が形成され、さらに、こ
の多結晶シリコン電極１３上には５０００〜１００００
χリンガラス（ＰｓＧ）＠１４を介して、３００〜１０
００χのチタンナイトライド（Ｔｌａ）膜１６とＭＯＯ
ＶＤ法により形成された５０００〜１ｏｏｏｏＸアルミ
ニウム（Ａ２）膜１７と３００〜１０００Ｘのチタン（
Ｔ１）膜１８の積層構造からなる金属配線層１９が形成
されている。The semiconductor device shown in FIG.
~1000~5oo through the oxide film 12 of ~1ooooX
oX polycrystalline silicon N electrode 13 is formed, and furthermore, on this polycrystalline silicon electrode 13, 5000 to 10000
300-10 via χ phosphorus glass (PsG) @14
00χ titanium nitride (Tla) film 16 and MOO
A 5000-1000X aluminum (A2) film 17 formed by the VD method and a 300-1000X titanium (A2) film 17 are formed by the VD method.
T1) A metal wiring layer 19 having a laminated structure of films 18 is formed.
また、酸化膜１１及びｐｓｏ膜１４には選択的に開孔部
（コンタクト・ホール）１５が設けられ、° 半導体基
板１０内に形成された半導体領域１１と金属配線層１９
とが電気的に接続されている。Further, openings (contact holes) 15 are selectively provided in the oxide film 11 and the pso film 14, and the semiconductor region 11 formed in the semiconductor substrate 10 and the metal wiring layer 19 are connected to each other.
are electrically connected.
ここで注目すべき事項は、前記ＭＯＯ’ＶＤ法により形
成されたＡＱ膜１７の段差部におけるステップ・カバレ
ージが良好であるということである。What should be noted here is that the step coverage in the step portion of the AQ film 17 formed by the MOO'VD method is good.
このため、第１図に示すように、多結晶シリコン１１１
ｔｉ上の段差、さらにはコンタク）−ホール１５におけ
る段差での金属配線層１９のステップ・カバレージが改
善され、その部分における金属配線層の断線が回避でき
る。そしてこれにより、この金属配線層１９上に形成さ
れる絶縁膜もしくは金属配線層（第１図には図示せず。Therefore, as shown in FIG.
The step coverage of the metal wiring layer 19 at the step in the hole 15 is improved, and disconnection of the metal wiring layer at that portion can be avoided. As a result, an insulating film or a metal wiring layer (not shown in FIG. 1) is formed on this metal wiring layer 19.
）のステップ・カバレージをも良好にすることができる
。さらに、金属配線層１９の膜厚が平坦部のそれに比べ
部分的に薄くなることがないため、耐エレクトロ・マイ
グレーション性等が大幅に向上し１配線の信頼性を向上
することができる、という優れた効果が得られる０
ところで、前記ＭＯＩＣｖＤ法によるＡ２膜は、アルミ
ニウムトリクロライド（ＡＱＯｆ１３） 、）リメチル
アルミニウム（ＡＲ３（ＣＨ３）ｓ ）、もしくはトリ
イソブチルアルミニウム（Ａｆｉ （０，Ｈ，）３）の
いずれかのソースガスをグロー放電もしくは６００℃以
下の高温雰囲気中で熱分解することにより形成される。) can also have good step coverage. Furthermore, since the thickness of the metal wiring layer 19 does not become partially thinner than that of the flat portion, the electromigration resistance is greatly improved, and the reliability of one wiring can be improved. By the way, the A2 film produced by the MOICvD method is made of aluminum trichloride (AQOf13), )trimethylaluminum (AR3(CH3)s), or triisobutylaluminum (Afi(0,H,)3). It is formed by glow discharge or thermal decomposition of one of the source gases in a high temperature atmosphere of 600° C. or lower.
また、減圧雰囲気中で堆積を行なうことが好ましい＠
なお、第１図の半導体装置においては、ＴｉＮ膜１膜上
６リアーメタルの作用を・しており、コンタクト・ホー
ル１５を含めた配線金属層１９全体の下に敷かれている
が、フンタクト・ホール１５部のみに選択的に形成して
も良い。In addition, it is preferable to perform the deposition in a reduced pressure atmosphere @ Note that in the semiconductor device shown in FIG. Although the hole is laid under the entire hole 19, it may be formed selectively only in the hole 15.
また、Ｔ１膜１８はＡ２膜１７のヒロック発生を抑制す
るために形成されているが、配線金属層１９の下に形成
されてもかまわない。Further, although the T1 film 18 is formed to suppress the occurrence of hillocks in the A2 film 17, it may be formed under the wiring metal layer 19.
前述の本発明の一実施例においては、ＩＡ ＯＯＶＤ法
による金属層がＡ２膜である場合について述べたが、こ
の金属層がタングステン（６）、モリブデン（Ｍｏ）、
チタン（Ｔ１）、銅（Ｏｕ）、アルミニウム（人込）、
シリコン（Ｓｌ）等を含ｆした有機金属化合物のＭＯＯ
ＶＤ法により形成された金属層である場合においても、
本発明が有効であることは言うまでもない。また、前述
の本発明の一実施例においては、金属配線層が３層の積
層構造からなる場合について述べたが、バリア・メタル
等は適当に選択可能であり、２層もしくは４層の積層構
造にもすることができる。In the embodiment of the present invention described above, the metal layer formed by the IA OOVD method was an A2 film, but this metal layer was made of tungsten (6), molybdenum (Mo),
Titanium (T1), copper (Ou), aluminum (crowd),
MOO of organometallic compounds containing silicon (Sl) etc.
Even in the case of a metal layer formed by the VD method,
It goes without saying that the present invention is effective. In addition, in the embodiment of the present invention described above, the metal wiring layer has a three-layer stacked structure, but the barrier metal etc. can be appropriately selected, and the metal wiring layer can have a two-layer or four-layer stacked structure. It can also be done.
以上述べたようＫ、本発明の半導体装置によれば、複数
の金属層の積層構造からなる配線層を有する半導体装置
において、金属配線層の少なくとも１層をＭＯ（１！Ｖ
Ｄ法により形成することに、金属配線層のステップ・カ
バレージか改善され、段差部における金属層の膜厚が平
坦部のそれに比べ薄くなることがないため、金属層の耐
エレクトロ・マイグレーション性等が大幅に向上し、配
線の信頼性を向上することができるという効果を有する
。As described above, according to the semiconductor device of the present invention, in a semiconductor device having a wiring layer having a laminated structure of a plurality of metal layers, at least one of the metal wiring layers is
By forming using the D method, the step coverage of the metal wiring layer is improved, and the thickness of the metal layer at the stepped portion is not thinner than that at the flat portion, so the electromigration resistance of the metal layer is improved. This has the effect of significantly improving the reliability of wiring.
なお、本発明は前述の実施に限定されず、その要旨を逸
脱しない範囲で種々変更可能であり、金属２層以上の多
層金属配線を有する半導体装置へも適用可能であること
は言うまでもない０It should be noted that the present invention is not limited to the above-described implementation, but can be modified in various ways without departing from the gist thereof, and it goes without saying that it is also applicable to semiconductor devices having multilayer metal interconnections with two or more metal layers.
第１図は本発明の半導体装置の一実施例を示す主要断面
図、第２図は従来の半導体装置を示す主要断面図である
。
１６・・・チタンナイトライド膜
１７・・・・・・ＭＯＯＶＤ法により形成されたＡ２膜
１８・・・・・・チタン膜
以 上
出願人 セイコーエプソン株式会社
、゛′FIG. 1 is a main sectional view showing an embodiment of the semiconductor device of the present invention, and FIG. 2 is a main sectional view showing a conventional semiconductor device. 16...Titanium nitride film 17...A2 film formed by MOOVD method 18...Titanium film or more Applicant: Seiko Epson Corporation, ゛'
Claims (1)
装置において、前記複数の金属層の少なくとも１層が、
有機金属気相化学成長法により形成された金属層からな
ることを特徴とする半導体装置。In a semiconductor device having a wiring layer having a laminated structure of a plurality of metal layers, at least one of the plurality of metal layers is
A semiconductor device comprising a metal layer formed by an organometallic vapor phase chemical growth method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27819886A JPS63131544A (en) | 1986-11-21 | 1986-11-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27819886A JPS63131544A (en) | 1986-11-21 | 1986-11-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63131544A true JPS63131544A (en) | 1988-06-03 |
Family
ID=17593961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27819886A Pending JPS63131544A (en) | 1986-11-21 | 1986-11-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63131544A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5804501A (en) * | 1994-11-23 | 1998-09-08 | Lg Semicon Co., Ltd. | Method for forming a wiring metal layer in a semiconductor device |
| KR100238438B1 (en) * | 1996-11-20 | 2000-01-15 | 정선종 | Method of formation of metallization film for anti-corrosion in dry etching of al and alcu film |
-
1986
- 1986-11-21 JP JP27819886A patent/JPS63131544A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5804501A (en) * | 1994-11-23 | 1998-09-08 | Lg Semicon Co., Ltd. | Method for forming a wiring metal layer in a semiconductor device |
| KR100238438B1 (en) * | 1996-11-20 | 2000-01-15 | 정선종 | Method of formation of metallization film for anti-corrosion in dry etching of al and alcu film |
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