JPS63131538A - Manufacture of isolation - Google Patents

Abstract

PURPOSE:To form an isolation of extremely narrow width by laminating a specific layer on the upper surface of a semiconductor substrate, forming a groove of the width in the same degree as the thickness of an oxide film by an oxide film formed on the side end of the layer in the substrate, and oxidizing the surface of the groove. CONSTITUTION:A silicon oxide film 5 and a nitride film 6 are laminated on a P<-> type semiconductor substrate 4, and a polysilicon layer 7 and a poly oxide film 8 of suitable shapes are deposited thereon. The range of the same degree as the width W of the layer 7 of the film 8 is removed by etching to expose the upper end of the layer 7, the surface of the film 6 is exposed by removing by etching, and the film 8 is retained. A groove 10 of the width in the same degree as the thickness of the film 8 is formed in the substrate by the film 8, and an isolation is formed by oxidizing the surface of the groove 10. Thus, the extremely narrow isolation can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing isolation, which is provided to electrically isolate a plurality of semiconductor elements from each other in a semiconductor integrated circuit.

(Conventional example) The structure of a conventional isolation will be explained based on FIG. The figure shows the structure of an isolation layer in a COD (charge transfer device). The comb-shaped part 1 shown with diagonal lines is the isolation region, and the high concentration impurity is diffused from the surface of the semiconductor substrate to the inside. It is formed by A plurality of transfer electrodes 2 are formed on the upper surface of the semiconductor substrate via a gate oxide film (not shown), and a charge transfer channel 3 is formed under the transfer electrodes 2 except for the isolation region l. Signal charges are transferred by applying transfer drive signals Dav1 to Ov4 to each transfer electrode 2, and adjacent transfer channels 3 are electrically isolated by an isolation region 1. Therefore, the signal charge always moves through a predetermined transfer channel 3.

(Problems to be Solved by the Invention) However, in the isolation of such a structure, photolithography (Photolithography) is required.
raphy), the minimum width l (see Figure 10) is 1 to 2 μm in a normal manufacturing process, and the limit is about 0.8 μm even in a high-density manufacturing process. This made development difficult.

(Means for Solving the Problems) The present invention has been made in view of the above problems, and an object of the present invention is to provide a manufacturing method that can form extremely narrow isolations. In order to achieve this object, the present invention stacks a specific layer on the upper surface of a semiconductor substrate, uses an oxide film formed on the side edge of the layer, and has a width similar to the thickness of the oxide film. The technical point is that a trench is formed in a semiconductor substrate and the surface of the trench is oxidized to form isolation.

(Example) Hereinafter, an example of the isolation manufacturing method according to the present invention will be described with reference to the drawings. 1 to 9 are longitudinal cross-sectional views of main parts sequentially showing a series of manufacturing steps.

The manufacturing method and structure will be explained based on these drawings. For example, a silicon oxide film (Sin2) 5 and a nitride film (S2) are formed on the surface of a P-type semiconductor substrate (substrate) 4.
i3N4)6 is laminated, and a polysilicon layer 7 of an appropriate shape is further deposited on the upper surface. For example, when forming a CCD, the length and width W are designed according to the shape of the transfer channel to be formed.

In the second manufacturing step, as shown in FIG. 2, a polyoxide film 8 is deposited on the surface of the polysilicon layer 7 by vapor phase growth (CVD) or the like. Here, - as an example 1. The thickness of the silicon oxide film 5 is 250λ, and the thickness of the nitride film 6 is 15.
00X, ytPIJ silicon layer 7 thickness 5000X,
Then, polyoxide film 8 is formed to have a thickness of about 0.2 μm.

Next, in a third manufacturing step shown in FIG. 3, a region of the polyoxide film 8 having a width W comparable to that of the polysilicon layer 7 is removed by etching to expose the upper end surface of the polysilicon layer 7.

In the fourth manufacturing step, the polysilicon layer 7 is removed by etching to form a nitride film 6 as shown in FIG.
The surface of the polyoxide film 8 is exposed and the polyoxide film 8 is left.

In the fifth manufacturing step, after etching the nitride film 6, the silicon oxide film 5 is further etched.

That is, after these etchings are performed, what remains as shown in FIG. fP +7 Nitride film 6 located under W oxide film 8
Since the silicon oxide film 50 remains, the surface of the semiconductor substrate 40 is exposed except for the remaining nitride film 6 and silicon oxide film 5, as shown in FIG. .

Next, as shown in FIG. 6, in a sixth manufacturing step, an insulating layer 9 of silicon dioxide (8102) with a thickness of about 6000λ is formed on the surface portion of the semiconductor substrate 40 by thermal oxidation, for example, wet oxidation. Here, the insulating layer 9 is not formed in the portion covered with the nitride film 6 and the silicon oxide film 5.

In the next seventh manufacturing step, the remaining nitride film 6 is removed by etching, and then the silicon oxide film 5 is removed by etching. During etching of this silicon oxide film 5, the upper surface of the insulating layer 9 is removed by about 250×, and the seventh
As shown in the figure, a portion of the semiconductor substrate 4 will be exposed, and the width ΔW of these exposed portions will be approximately equal to the width of the nitride film 5 shown in FIG.

In the eighth step shown in FIG. 8, a groove 10 is formed inside the semiconductor substrate 4 through the exposed portion by anisotropic etching. Note that the width of each groove portion 10 is the width ΔW of the exposed portion.
is almost equal to Next, zero ions are implanted into the bottom end of the trench 10 to form a p+Q) region 11. and,
Insulating layer 9 is removed by etching to expose the surface of semiconductor substrate 4.

In the next K, ninth manufacturing process, a Kn- region 12 on the surface of the semiconductor substrate 40 is formed by ion implantation technology, and an oxide film (S10□) 13 is further formed on the upper surface, and then a -7
A recon layer 14 is deposited.

This allows the n-region 12 to be transferred to the oxide film 13.
A COD is formed in which the gate oxide film is used as a gate oxide film and the polysilicon layer 14 is used as a transfer electrode. Each transfer channel is electrically insulated by the oxide film 13 and P+ region 11 formed in the trench 10.

In this way, the width of the isolation region formed by the groove 10 is equal to ΔW for each button as shown in FIG. 8, and can be made extremely narrower than in the past, making it possible to achieve high integration. be.

In this embodiment, the manufacturing of the CCD is shown as one line, but it can be applied to other semiconductor integrated circuits, and similarly enables high integration. 11 to enhance the insulation effect,
The formation of this region 11 may be omitted as appropriate.

(Effects of the Invention) As explained above, according to the isolation manufacturing method of the present invention, a specific layer is laminated on the upper surface of a semiconductor substrate, and an oxide film formed on the side edge of the layer is used to Since isolation is formed by forming a trench with a width comparable to the thickness of the oxide film in the semiconductor substrate and oxidizing the surface of the trench, it is possible to form extremely narrow isolation. Furthermore, the grooves provide an extremely excellent insulation effect, and furthermore, the effect of making it possible to manufacture highly integrated semiconductor integrated circuits is obtained.

[Brief explanation of the drawing]

FIGS. 1 to 9 show manufacturing steps for illustrating an embodiment of the isolation manufacturing method according to the present invention.
FIG. 10 is a schematic plan view showing a conventional isolation structure in the case of COD. 4... Semiconductor substrate, 5... Silicon oxide film, 6...
・Nitride film, 7... Polysilicon layer, 8... Bumpy oxide film, 9... Insulating layer, 10... Groove, 11... P+
region, 12... n- region, 13... oxide film, 14.
...Polysilicon layer (3 others) Figure 1 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9

Claims (1)

[Scope of Claims] A first step of sequentially laminating a silicon oxide film and a nitride film on the upper surface of a semiconductor substrate, and forming a polysilicon layer of an appropriate shape on the upper surface of the nitride film, and a surface of the polysilicon layer. a second step of forming an oxide film on the oxide film; a third step of removing the upper end of the oxide film by etching to expose the upper surface of the polysilicon layer; and removing the polysilicon layer by etching. a fourth step; a fifth step of removing the silicon oxide film and nitride film except for the silicon oxide film and nitride film under the oxide film by anisotropic etching; A sixth step of forming an insulating layer by thermal oxidation, a seventh step of removing the remaining silicon oxide film and nitride film by etching, and etching the semiconductor substrate 4 excluding the insulating layer portion by anisotropic etching. A method for manufacturing an isolation device, comprising: an eighth step of forming a groove; and a ninth step of forming a silicon oxide film on the surface of the groove by thermal oxidation.