JPH0228330A - Production of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive the minuteness and high speed of an element by forming a base extraction electrode on an exposed substrate while shaping an outside base area in the part just under the base extraction electrode of the substrate and forming an inside base area and an emitter area in the part just under the part in which a second minute pattern of the substrate is etched. CONSTITUTION:An element separating area by a trench 10 is formed by a mask layer 7, a base extraction electrode 18 is shaped by the use of pattern retreat by side etching of a first semiconductor layer 5 constituting the mask layer 7 and a base area (an outside base area 19 and an inside base area 23) and an emitter area 25 are formed on a remaining pattern part. Thereby position matching margin for position mismatching among the element separating area by the trench 10, the base area (the base area 19 and the inside base area 23) and the emitter area 25 is not performed and the interval among the element separating area, the base area and the emitter area 25 can sufficiently be narrowed and element minuteness and high speed can be realized.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art Problems to be Solved by the Invention Means for Solving the Problems Action Embodiments First Embodiment of the Invention Other Embodiments of the Invention Effects of the invention (Fig. 1) (Fig. 2) [Summary] Regarding the method of manufacturing a semiconductor device, it is possible to perform element isolation without providing alignment margin for misalignment between the element isolation region and the base region/emitter region. The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can sufficiently reduce the distance between the region and the base region/emitter region, thereby realizing element miniaturization and speeding up. a step of forming at least three or more mask layers that are oxidation-resistant films, a step of selectively etching the substrate using the mask layer as a mask to form grooves of different widths, and a step of covering the grooves of different widths. a process of forming a film made of a material different from that of the mask layer; and anisotropic etching of the film made of a material different from that of the mask layer so that only the wide groove bottoms of the grooves of different widths are opened. selectively etching the substrate using the mask layer and a film made of a different material from the mask layer as a mask to form a wrench groove at the bottom of the wide groove. a step of removing a film made of a different material from the mask layer; and a step of selectively oxidizing the inside of the trench having different widths and the inside of the trench groove to form a silicon oxide film.
filling the grooves with different widths and the trench grooves so as to insulate at least the upper surface of the substrate;
forming a first fine pattern by selectively etching the upper layer of the mask layer in a state in which it is self-aligned with the oxidation-resistant film on the lower layer; forming a second fine pattern by etching a portion of the film exposed by etching the upper film to expose the substrate; and forming a base lead-out electrode on the exposed substrate. , forming an external base region in a portion of the substrate immediately below the base extraction electrode; selectively etching the second fine pattern; and etching the second fine pattern of the substrate. forming an internal base region and an emitter region in a portion immediately below the portion.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and can be applied, for example, to a method of manufacturing a high-speed bipolar transistor. The present invention relates to a method of manufacturing a semiconductor device that can be formed finely.

Various conventional methods for manufacturing semiconductor devices have been proposed in which a base region and an emitter region are formed in a self-aligned manner, but a method using an element isolation region using a field oxide film is known as a more conventional method.

The reason why the base region and the emitter region are formed in a self-aligned manner is that there is an advantage that they can be formed with fine dimensions. However, in devices that use device isolation regions made of field oxide films, alignment margins are required against misalignment, etc., and the distance between the device isolation regions and the base/emitter regions cannot be made sufficiently narrow. There was a limit to miniaturization.

Therefore, there is a need for a method of manufacturing a semiconductor device that can sufficiently narrow the distance between the element isolation region and the base region/emitter region, and in particular can realize element miniaturization and higher speed.

[Conventional technology]

Conventionally, for example, in order to achieve miniaturization and increase in speed of bipolar transistors, it is necessary to reduce the area of the base region, the base contact's pH region, the element isolation region, and the like.

Particularly in a semiconductor device such as a bipolar transistor, an element isolation region, a base region, and an emitter region formed by a field oxide film are defined by alignment, and a margin for misalignment is required.

[Problem to be solved by the invention]

In the conventional manufacturing method of semiconductor devices, it is necessary to have alignment margin for misalignment between the element isolation region and the base/emitter region, and the distance between the element isolation region and the base/emitter region is required. There was a problem in that it was not possible to make the area sufficiently narrow, making it difficult to miniaturize the device and increase speed.

Therefore, the present invention is capable of sufficiently narrowing the distance between the element isolation region and the base/emitter region without providing alignment margin for misalignment between the element isolation region and the base/emitter region. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can realize miniaturization and speeding up of elements.

[Means to solve the problem]

a step of forming at least three or more mask layers whose lower layer side is an oxidation-resistant film on a substrate; a step of selectively etching the substrate using the mask layer as a mask to form grooves of different widths; forming a film made of a different material from the mask layer so as to cover grooves with different widths; selectively etching the substrate using the mask layer and a film made of a different material from the mask layer as a mask to form a trench groove at the bottom of the wide groove. a step of removing a film made of a material different from that of the mask layer; a step of selectively oxidizing and forming a silicon oxide film in the grooves having different widths and in the trench grooves; filling the different grooves and the trench grooves so as to insulate at least the upper surface of the substrate, and self-aligning the upper film of the mask layer with the lower oxidation-resistant film. forming a first fine pattern by selectively etching the lower oxidation-resistant film in a state where the upper film is etched; and exposing the substrate by etching a portion of the lower oxidation-resistant film exposed by etching the upper film forming a base extraction electrode on the exposed substrate and forming an external base region in a portion of the substrate directly below the base extraction electrode; and forming an internal base region and an emitter region in a portion of the substrate immediately below the etched portion of the second fine pattern.

In the present invention, the substrate includes, for example, an embodiment in which the substrate is composed of a semiconductor layer having p-type conductivity, a buried semiconductor layer having n-type conductivity, and an epitaxial layer having n-type conductivity. .

In the present invention, the step of filling grooves and trench grooves with different widths so as to insulate at least the top surface of the substrate means that when filling grooves with different widths, at least the surface of the top surface of the substrate is insulated. If the trench groove and all grooves of different widths are filled with an insulating material to insulate the surface, then the trench groove is filled with a semiconductor such as polysilicon, and then the grooves of different widths are filled with an insulating material. This includes an embodiment in which the surface is insulated.

[Effect]

In the present invention, at least three or more mask layers whose lower layer is an oxidation-resistant film are formed on a substrate, and grooves of different widths are formed by selectively etching the substrate using these mask layers as masks. A film made of a different material from the mask layer is formed to cover different grooves. Next, anisotropic etching is performed on a film made of a material different from that of the mask layer so that only the wide bottom of the trenches of different widths is opened. After a trench groove is formed at the bottom of the wide groove by selective etching of the substrate, a film made of a material different from that of the mask layer is removed. Next, a silicon oxide film is formed by selective oxidation in the grooves and trenches of different widths, and the grooves and trenches of different widths are filled so that the upper surface of the substrate is insulated. The upper layer of the layer is
A first fine pattern is formed by selectively etching in a self-aligned state with respect to the underlying oxidation-resistant film.

Next, the part of the lower oxidation-resistant film exposed by etching the upper film is etched to expose the substrate and form a second fine pattern, and then a base extraction electrode is formed on the exposed substrate. At the same time, an external base region is formed in a portion of the substrate immediately below the base lead-out electrode. Next, after the second fine pattern is selectively etched, an internal base region and an emitter region are formed in a portion of the substrate immediately below the etched portion of the second fine pattern.

Therefore, the element isolation region and the base region (corresponding to the external base region and the internal base region in FIG. 1) and the emitter region due to trench grooves are not provided for alignment margins. The distance between the base region and the emitter region can be made sufficiently narrow, making it possible to realize finer device size and higher speed.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIGS. 1A to 1E are diagrams for explaining an embodiment of a method for manufacturing a semiconductor device according to the present invention. Here N
A case where the method is applied to a method for manufacturing a PN type transistor is shown.

In these figures, ■ is made of SL, for example, a p-type substrate, 2 is, for example, an n-type buried semiconductor layer, and 3 is a p-type substrate, for example.
is, for example, an n-type epitaxial layer, and 4 is, for example, S, , N
The lower layer side of the first oxidation-resistant film consisting of 4 corresponds to the oxidation-resistant film according to the present invention. 5 is a first layer made of polysilicon, for example.
This semiconductor layer corresponds to the upper layer film according to the present invention. 6
is a second oxidation-resistant film made of, for example, 3.3N4; 7 is a mask layer (corresponding to the mask layer according to the present invention); It is composed of a chemical film 6. 8a and 8b are a (corresponding to the grooves with different widths according to the present invention), and the groove 8a is wider than the guide 8b (
It is formed. Reference numeral 9 denotes a first silicon oxide film made of, for example, Sin, which corresponds to a film made of a different material from that of the mask layer according to the present invention. 10 is a trench groove, which corresponds to the trench groove according to the present invention. Reference numeral 11 denotes a second silicon oxide film of, for example, 8.0□, which corresponds to F, 14 for the silicon oxide film according to the present invention. 12 is, for example, polysilicon (PSG).
or non-doped SG), 13 is a third silicon oxide film made of, for example, S, 02, and 14 is a first fine pattern (corresponding to the first fine pattern according to the present invention). , a first oxidation-resistant film 4, a first semiconductor layer 5, and a second oxidation-resistant film 6.

15 is a fourth silicon oxide film made of, for example, S, 0□;
16 is a second fine pattern (corresponding to the second fine pattern according to the present invention), which includes the first oxidation-resistant film 4, the first semiconductor layer 5, the second oxidation-resistant film 6, and the fourth silicon Oxide film 1
It consists of 5. 17 is a third semiconductor layer made of polysilicon, for example, and 18 is a base extraction electrode, which corresponds to the base extraction electrode according to the present invention. 19 is an external base area, which corresponds to the external base area according to the present invention. 20 is a collector contact SR region, 21 is, for example, 8.
22 is an emitter window, 23 is an internal base region, 24 is a fourth semiconductor layer made of, for example, polysilicon, 25 is an emitter 9H region, 26 is a base electrode window, and 27 is a collector. The electrode window 28 is, for example, Af
31 is a collector lead-out electrode.

Note that the three layers consisting of the substrate 1, the buried semiconductor N2, and the epitaxial layer N3 correspond to the substrate according to the present invention.

Next, the manufacturing process will be explained.

First, as shown in FIG. 1(a), a buried semiconductor layer 2 and an epitaxial layer 3 are sequentially formed on a substrate 1. Next, a first oxidation-resistant film 4, a first semiconductor layer 5, and a second oxidation-resistant film 6 are sequentially formed on the epitaxial layer N3 by, for example, a CVD method.

Here, the thickness of the first oxidation-resistant film 4 is, for example, 500 A, the thickness of the first semiconductor layer 5 is, for example, 2000 A, and the thickness of the second oxidation-resistant film 6 is, for example, 1500 A. Next, unnecessary portions of the second oxidation-resistant film 6, the first semiconductor layer 5, and the first oxidation-resistant film 4 are selectively etched by, for example, the RIE method, and the first oxidation-resistant film 4 and the first oxidation-resistant film 4 are etched. Semiconductor layer 5 and second
A mask layer 7 made of an oxidation-resistant film 6 is formed. This applies to the process of forming three or more mask layers, the lower layer of which is an oxidation-resistant film, on a substrate in the present invention.

Next, as shown in FIG. 1(b), the epitaxial layer N3 is selectively etched by, for example, RIE using the mask layer 7 as a mask to form grooves 8a and 8b having different widths. This corresponds to the step of the present invention in which the substrate is selectively etched using the mask layer as a mask to form grooves of different widths.

Next, as shown in FIG. 1(c), a film with a thickness of, for example, 3000 is coated by, for example, the CVD method to cover the grooves 8a and 8b (a material different from that of the mask N7 is used).
After depositing S and O2, portions where S and O2 are not needed are selectively etched by anisotropic etching (for example, RIE method) to form a first silicon oxide film 9. At this time, only the bottom of the wide groove 8a of the epitaxial layer 30 is opened to expose the epitaxial layer 3, and the S, O□ film remains on the entire narrow groove 8b and the sidewalls of the wide groove 8a. This is the step of forming a film made of a material different from the mask layer so as to cover the grooves of different widths of the present invention, and the step of forming a film made of a material different from the mask layer so as to cover the grooves of different widths, and to form a film made of a material different from the mask layer so that only the wide groove bottoms of the grooves of different widths are opened. S is applied to the step of anisotropically etching the film.

Next, as shown in FIG. 1(d), anisotropic etching (
For example, using the mask layer 7 and the first silicon oxide film 9 as a mask, the epitaxial layer 3 is transferred to the substrate 1 by RIE method).
A trench groove 10 for element isolation is formed by selectively etching. This corresponds to the process of the present invention in which the substrate is etched using a mask layer and a film made of a different material as a mask to form a trench groove.

Next, as shown in FIG. 1(e), after selectively etching only the first silicon oxides v and 9 by, for example, RIE, 18a, 8b and the inside of trench groove 10 are etched by, for example, thermal oxidation. A second silicon oxide film 11 is formed by selective oxidation. This corresponds to the step of removing a film made of a material different from that of the mask layer and the step of oxidizing the insides of grooves and trench grooves of different widths to form a silicon oxide film, according to the present invention.

Next, as shown in FIG. 1(f), polysilicon is deposited by, for example, the CVD method so as to cover the trench 2s10, and unnecessary portions of the polysilicon are selectively etched by etch-back to form the trench groove 10. A second semiconductor IW12 is formed to fill the inside. Then, for example, C
After depositing S, 0□ to cover the trenches 88.8b by the VD method, the unnecessary portions of the stow are selectively etched using an etch bank, and a third silicon oxide film is deposited to fill the insides of the trenches 8a and 8b. form 13. Here, the side walls of the first semiconductor layer 5 are etched and thinned, but this is because when the insides of the grooves 8a and 8b are oxidized, the side walls of the first semiconductor layer 5 are etched and thinned. This is because the oxidized portion was removed by the etch bank when forming the third silicon oxide film 13. This corresponds to the step of filling grooves and trench grooves with different widths so as to insulate at least the upper surface of the substrate according to the present invention.

Next, as shown in FIG. 1(g), unnecessary portions of the first semiconductor layer 5 are selectively etched by side etching to form a first fine pattern 14. At this time, the narrow pattern of the first semiconductor layer 5 is lifted off,
The region directly under the remaining portion of the first semiconductor layer 5 of the epitaxial layer N3 becomes an emitter region, that is, the first semiconductor layer 5 becomes a pattern for determining the emitter, and the first semiconductor layer 5 becomes an emitter region.
The side-etched portion of the semiconductor layer 5 becomes an external base region. This corresponds to the step of the present invention in which the upper film of the mask layer is self-aligned with the lower oxidation-resistant film and etched to form the first fine pattern.

Next, as shown in FIG. 1(h), a fourth silicon oxide film 15 is formed on the side wall of the first semiconductor layer 5 by, for example, a thermal oxidation method, and then controlled etching (for example, by wet etching using hot phosphoric acid) is performed. (etching) to form the first oxidation-resistant film 4.
Then, unnecessary portions of the second oxidation-resistant film 6 are selectively etched to form a second fine pattern 16. At this time, the portion of the first oxidation-resistant film 4 exposed by the etching of the first semiconductor layer 5 is etched, and the epitaxial layer 3 is exposed. This corresponds to the step of the present invention in which the portion of the lower oxidation-resistant film exposed by etching the upper film is etched to expose the substrate and form a second fine pattern.

Next, as shown in FIG. 1(i), after depositing polysilicon by, for example, the CVD method, unnecessary portions of the polysilicon are selectively etched by controlled etching to flatten the third semiconductor. Form layer 17.

Next, as shown in FIG. 1(j), the base extraction electrode 18, the external base region 19, and the collector contact L S
Ion implantation is performed to form II2O3.

Specifically, first, ions of B1, for example, are selectively implanted into the polysilicon portion of the base extraction electrode 18, and then,
External base regions 19 are selectively formed in epitaxial layer 3 by heat treatment.

Similarly, after selectively implanting, for example, P'' ions into the polysilicon portion of the collector lead-out electrode 31, a collector contact region 20 is selectively formed in the epitaxial layer 3 by heat treatment. Then, for example, RIE
After etching unnecessary portions of the third semiconductor layer 17 by a method, the polysilicon is oxidized by, for example, a thermal oxidation method to form a fifth silicon oxide film 21. This corresponds to the step of forming the base lead-out electrode of the present invention and forming an external base region in a portion of the substrate immediately below the base lead-out electrode.

Next, as shown in FIG. 1(k), the second fine pattern 16 is selectively etched by, for example, wet etching to form an emitter window 22.

This corresponds to the step of etching the second fine pattern of the present invention. Next, for example, B' ion implantation is performed to form the internal base region 23.

Next, as shown in FIG. 1(1), polysilicon is deposited to cover the emitter window 22 by, for example, the CVD method, and then, for example, AS' is introduced into the polysilicon by ion implantation. Next, unnecessary portions of the polysilicon are selectively etched by, for example, RIE to form a fourth semiconductor layer 24, and then an emitter region 25 is formed by heat treatment.

This and the process explained with reference to FIG. 1(k) correspond to the step of forming the internal base region and emitter region of the present invention.

Next, after forming the base electrode window 26 and the collector electrode window 27 and depositing /l by, for example, sputtering,
The unnecessary portions of Aβ are etched to form the base extraction electrode 18, the fourth semiconductor layer 24, and the collector extraction electrode 3.
By forming a wiring layer 28 in contact with 1, a semiconductor device as shown in FIG. 1(2) is completed.

That is, in the above embodiment, the element isolation region by the trench groove IO is formed using one mask layer 7 using a sidewall forming technique using anisotropic etching, and the first
The base lead-out electrode 18 is formed by using pattern recession by side etching of the semiconductor layer 5, and the base region (external base region 19, internal base region 23) and emitter region 25 are formed in the remaining pattern portion. , element isolation region and base region (
The element isolation region, the base region, and the emitter region 19 and the internal base region 23) and the emitter region 25 are arranged without providing alignment margins for misalignment between the base region 19 and the internal base region 23) and the emitter region 25.

It is possible to make the distance between the electrode region 25 sufficiently narrow, and it is possible to realize element miniaturization and speeding up (specifically, the collector sub capacitance and collector base capacitance can be reduced). The base region and emitter region 25 can be formed in self-alignment with respect to the region.

In the above embodiment, as shown in FIG. 1(r), after filling the trench groove 10 with the second semiconductor Jii 12,
Although the case has been described in which the upper surface of the substrate 1 is insulated by filling the grooves 8a and 8b with different widths with the third silicon oxide film 13, the present invention is not limited to this. When filling the different grooves 8a and 8b, it is sufficient that the filling is performed so that at least the upper surface of the substrate 1 is insulated. Specifically, for example, the trench groove 10 and all the grooves 8a and 8b having different widths are filled with It is also possible to insulate the upper surface of the substrate l by filling it only with an insulating material of 5 in 2.

In the above embodiment, as shown in FIG. However, the present invention is not limited thereto. Before depositing polysilicon for forming the fourth semiconductor N24, the base electrode window 26 and the collector electrode window 27 are formed, and then the fourth semiconductor N24 is formed. After depositing polysilicon to form the semiconductor layer 24 of No. 4, ion implantation of A,° to form the emitter region 25, and then depositing Al to form the wiring layer 28, /l and It is also possible to use a step of etching polysilicon to form the fourth semiconductor layer 24 and the wiring layer 28.

In the above embodiment, as shown in FIG. 1(a), the mask layer 7
Although the case where the mask layer 7 is composed of the first oxidation-resistant film 4, the first semiconductor layer 5, and the second oxidation-resistant film 6 has been described, the present invention is not limited to this. For example, as shown in FIG. 2(a), the mask layer 7 may be formed of an oxidation-resistant film 41a made of S, 3N, etc., for example, as shown in FIG. 2(a). ．．
Silicon oxide film 42a1 consisting of 0□, for example 5=zN4
The oxidation-resistant film 41b and the silicon oxide film 42b made of, for example, S and O□ may also be used.As shown in FIG. and an oxidation-resistant film 51a made of, for example, S, N4, a silicon oxide film 52 made of, for example, S, O2, and an oxidation-resistant film 51b made of, for example, Si3Na.

〔effect〕

According to the present invention, the distance between the element isolation region and the base region/emitter region can be sufficiently narrowed without providing alignment margin for misalignment between the element isolation region and the base region/emitter region. This has the effect of realizing element miniaturization and speeding up.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining one embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a diagram for explaining another embodiment of the method for manufacturing a semiconductor device according to the present invention. 1... Substrate, 2... Buried semiconductor layer, 3... Epitaxial layer, 4... First oxidation resistant film, 5...・First semiconductor layer, 6...Second oxidation-resistant film, 7...Mask layer, 8a, 8b...Groove, 9...Nth 1 silicon oxide film, 10...
・Trench groove, 11...Second silicon oxide film, 12...
...Second semiconductor layer, 13...Third silicon oxide film, 14...
...First fine pattern, 15... Fourth silicon oxide film, 16... Second fine pattern, 1
7...Third semiconductor layer, 18...Base extraction electrode, 19...
・External base region, 20... Collector contact SR region, 21...
...Fifth silicon oxide film, 22...Emitter window, 23...-Internal base region, 24...Fourth semiconductor layer, 25... ...Emitter region, 26...Base electrode window, 27...Collector electrode window, 28...Wiring layer, 31...Collection extraction electrode.叉--2 Figure Figure Figure

Claims (1)

[Claims] A step of forming at least three or more mask layers, the lower layer of which is an oxidation-resistant film, on a substrate, and selectively etching the substrate using the mask layers as a mask to form grooves of different widths. a step of forming a film made of a different material from the mask layer so as to cover the grooves of different widths; is a step of selectively performing anisotropic etching of films made of different materials, and selectively etching the substrate using the mask layer and a film made of different materials as masks. forming a trench groove at the bottom of a wide groove; removing a film made of a different material from the mask layer; and forming a silicon oxide film by selectively oxidizing the inside of the trench having different widths and the inside of the trench groove. filling the grooves of different widths and the trench grooves so as to insulate at least the upper surface of the substrate; and replacing the upper film of the mask layer with the lower oxidation-resistant film. forming a first fine pattern by selectively etching in a self-aligned state; and etching a portion of the lower oxidation-resistant film exposed by etching the upper film. forming a base extraction electrode on the exposed substrate and forming an external base region in a portion of the substrate directly below the base extraction electrode; selectively etching the second fine pattern; and forming an internal base region and an emitter region in a portion of the substrate immediately below the etched portion of the second fine pattern. A method for manufacturing a semiconductor device, characterized in that: