JPH0758194A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent dimensions of an element forming region from fluctuating in forming a wide element separation region and a narrow element separation region through combined use of trench isolation and selective oxidation separation. CONSTITUTION:The central part of a wide element separation region Iw, comprises a selective oxide separation film 5 due to the LOCOS method and its both ends comprise a trench 9b embedded in a CVD-SiOx film 10b. The narrow element separation region In comprises a trench 9a embedded in a CVD- oxide film 10a. This makes a design distance D (width of an element forming region) between both element separations regions Iw and In to be determined by a space between the trenches 9a and 9b and not subject to the effects a dimensional conversion difference due to LOCOS and mask matching discrepancy of the selective oxide separation pattern and a trench pattern. There is no need to make a pad oxide film an extremely thin film. As compared with the existing method, only a pattern change is adequate and economy and productivity will not deteriorate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of accurately performing fine element isolation in a semiconductor device manufacturing process.

[0002]

2. Description of the Related Art In order to prevent elements such as transistors and resistors from interfering with other elements through a semiconductor substrate, element isolation technology for isolating each element has become an important technology in the semiconductor manufacturing field. . It is no exaggeration to say that element isolation is the key to determining the memory cell size of a large capacity memory element.

Conventionally, the most reliable element isolation method has been established and the generally adopted method is LOCOS.
(Local oxidation of silicon) method. This is S
This is a method of forming a selective oxidation separation film by selectively oxidizing the Si substrate using the iN _x film as a mask, and many improved methods have been proposed.

By the way, 4MSR currently in mass production
Half-micron (0.5μ
m) The device has an element isolation width of about 0.6 μm. This size can be barely achieved by the LOCOS method or its improved method, but considering the influence on the process margin and the electrical characteristics even if the various conditions are optimized, the limit is about 0.5 μm. It is considered. Therefore, next generation 16MSRAM, 64M
Deep submicron (0.3 μm) such as DRAM
It is extremely difficult to achieve the element isolation width of about 0.35 μm required for the device by the LOCOS method.

The first problem in the process is the occurrence of a dimensional conversion difference. In the LOCOS method, if a SiN _x film serving as a mask is directly formed on a Si substrate, there is a great possibility of inducing crystal defects. Therefore, a thin SiO _x film (pad SiO _x film) is provided under the SiN _x film. However, for this reason, the selective oxidation isolation film penetrates under the SiN _x film to form a transition region called a bird's beak, which obscures the boundary between the element isolation region and the element formation region. It is known that such a difference in size conversion can be prevented by thinning the pad oxide film or reducing the oxide film thickness. However, conversely, crystal defects increase or MO
There arises a problem that the parasitic capacitance between the first polysilicon layer forming the gate electrode of the S-FET and the Si substrate increases, and the operating speed of the FET decreases.

On the other hand, as a problem in electrical characteristics, first, as the element isolation width is made finer, the punch-through resistance between the elements adjacent to each other with the element isolation region interposed therebetween is lowered. It is known that punch through can be prevented by increasing the impurity concentration in the vicinity of the surface of the substrate, but on the other hand, the junction capacitance increases and the operating speed decreases. In addition to this, problems such as an increase in V _TH (threshold voltage), field inversion, and an increase in junction leakage occur due to the narrow channel effect.

Therefore, it has been proposed to solve these problems by element isolation using a trench. This method is called trench isolation, and a trench is formed in a Si substrate by RIE (reactive ion etching), and the inside of the trench is typically made of Si.
This is a method of burying it flat with an O _x film. This filling is usually performed by etching back the SiO _x film deposited on the entire surface of the substrate.

According to the trench isolation, since the film thickness of the oxide film for element isolation can be arbitrarily set by controlling the depth of the trench, it becomes easy to secure the field inversion voltage and also the element isolation regions can be secured. Since the substantial distance becomes longer, punch-through resistance is also improved.

However, according to this method, IEDM 92, p.
As pointed out in Nos. 275 to 278, element isolation characteristics deteriorate when wide element isolation is attempted. In other words, since the silicon oxide film covering the trench with a wide opening has a certain conformality, even if an attempt is made to bury the trench by etching back the silicon oxide film, the central portion is dented, and it is not enough. This is because the punch-through breakdown voltage cannot be obtained.

As described above, since the miniaturization is limited only by the selective oxidation isolation film and the wide element isolation region cannot be formed only by the trench, both of them will be used together in the future LSI manufacturing, and a relatively wide element will be formed. It is considered necessary to use a selective oxidation isolation film in the isolation region and a trench in the relatively narrow element isolation region.

[0011]

However, since the selective oxidation isolation film and the trench are formed by using different masks from each other, the distance between the relatively wide element isolation region and the relatively narrow element isolation region, that is, the element isolation region. There is a problem that the width of the formation region varies greatly depending on the accuracy of mask alignment. This problem will be described with reference to FIG.

The upper part of FIG. 4 is a schematic sectional view of a part of the wafer, and the lower part is a plan view of the pattern. For example, as shown in the upper diagram of FIG. 4, a narrow element isolation region I _n (subscript n means narrow) and a wide element isolation region i _w (subscript w means wide) on the Si substrate 11. Consider the case where and are placed at a distance d. The narrow isolation region i _n are those in which the CVD-SiO _x film 14 formed by buried in the trench 12 formed on the Si substrate 11. On the other hand, the wide element isolation region i _w is LOC
The selective oxidation separation film 13 is formed by selectively oxidizing the surface of the Si substrate 11 by the OS method.

Here, the distance d corresponds to the width of the element forming region, but it is generated by adding the mask alignment error e to the distance D from the original design position B. Contrary to the illustrated example, the alignment error e may be subtracted from the design dimension D. This is trench 1
Since the formation of 2 and the formation of the selective oxidation separation film 13 are performed based on different mask patterns, this is an unavoidable problem to some extent. If the above design dimension D is 0.25 μ
When the minimum processing size of m is applied, when patterning is performed using a stepper (reduction projection exposure apparatus) with a mask alignment accuracy of 0.08 μm on the wafer, the alignment error e alone reaches 32% of the designed distance D. Become.

In practice, the above-mentioned mask alignment error is affected by LO.
The dimension conversion difference in the COS method is added, and the width of the element formation region is changed. Such a variation causes an uncertain factor in device design, such as making it difficult to predict the drain current value of the MOS-FET formed in this region. Therefore, the present invention is capable of accurately defining the width of an element isolation region of a semiconductor device in which a relatively narrow element isolation region and a relatively wide element isolation region coexist, and is capable of achieving excellent device characteristics. An object is to provide a method for manufacturing a device.

[0015]

A method of manufacturing a semiconductor device according to the present invention is proposed in order to achieve the above-mentioned object, and includes a relatively narrow first element isolation region and a relatively wide second element isolation region. When manufacturing a semiconductor device having an element isolation region of the above, the first element isolation region is formed by a trench, and the second element isolation region is a trench having both ends defining the width thereof. The regions sandwiched by are formed by selective oxidation separation films.

At this time, after forming the selective oxidation isolation film in the second element isolation region, trenches may be collectively formed in both the second element isolation region and the first element isolation region. It is possible.

[0017]

In the present invention, the distance between the relatively narrow first element isolation region and the relatively wide second element isolation region, that is, the element that defines the width of the element formation region is between the trenches. It becomes the distance. The trench is formed anisotropically by processing the substrate by RIE, and even if the trench is processed into a taper shape for reasons of device characteristics, the position of the opening end is almost unchanged. That is, the trench is L
It has almost no uncertainty in the lateral dimension unlike the selective oxidation separation film by the OCOS method.

Further, in the second element isolation region, the region sandwiched by the trenches at both ends is constituted by a selective oxidation isolation film based on another mask as in the conventional case. However, at this time, all the mask alignment error and the dimension conversion difference are absorbed inside the second element isolation region and have no influence on the distance to the first element isolation region. Therefore, according to the present invention, the width of the element isolation region can be accurately defined.

Although the above is the merit in the process, such a constitution also has the merit in the electric characteristics. That is,
Since the narrow first element isolation region is formed by trench isolation, punch-through resistance is improved, and narrow channel effect, field inversion, junction leak, etc. can be suppressed.

In order to obtain such a structure, after forming a selective oxidation isolation film in the second element isolation region, trenches are collectively formed in both the second element isolation region and the first element isolation region. It is extremely convenient to form. That is, since the trenches in both regions are formed by transferring one mask pattern, it can be dealt with only by changing the conventional mask pattern, and the number of steps does not increase.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to FIGS. In the present embodiment, first, the selective oxidation isolation film of the large element isolation region I _W is formed by LOCOS.
Formed by law, followed by both ends of the selective oxidation separation membrane, and in both narrow isolation region I _n which is formed at a distance D on the design and this, in the example collectively form a total of three trenches is there.

First, as shown in FIG. 1 (a), Si
A pad SiO _x film 2 having a thickness of about 10 nm is formed on the surface of the substrate 1 by thermal oxidation, and plasma CV is formed on the pad SiO _x film 2.
A SiN _x film 3 having a thickness of about 100 nm was deposited by the D method, and patterning was performed to use this SiN _x film 3 as a mask for selective oxidation to form the opening 4. Although the opening 4 is opened substantially at the center of the large element isolation region I _W , a slight mask alignment error may occur.

Next, as an example, a normal wafer at 950 ° C.
And then oxidize it to form the opening as shown in FIG. 1 (b).
A selective oxidation separation film having a thickness of about 600 nm inside the portion 4
5 was formed. At this time, both ends of the selective oxidation separation membrane 5 are burred.
Become beak and SiN _xCrawl under the membrane 3,
Pad SiO_xThere is a slight dimensional conversion difference depending on the thickness of the film 2.
Occur.

Next, the SiN _x film 3 and the pad SiO _x film 2 were removed by etching as shown in FIG. 1 (c). This etching is performed by first etching Si during wet oxidation.
A SiO _x film (not shown) formed on the surface of the N _x film 3.
After being removed under the condition that the selection ratio to SiO _x is low, S is removed under the condition that the selection ratio to the underlying pad SiO _x film 2 is high.
The iN _x film 3 was removed, and the pad SiO _x film 2 was removed by wet etching using a dilute hydrofluoric acid solution, so that the Si substrate 1 was not damaged.

Next, as shown in FIG. 1D, thermal oxidation is performed again to form SiO 2 with a thickness of about 10 nm on the entire surface of the wafer.
_{The x} film 2a was formed, and then, as an example, a polysilicon layer 6 was deposited to a thickness of about 60 nm by a CVD method, and a resist mask 7 which became a mask for trench etching in the next step was formed by photolithography. here,
The polysilicon layer 6 is a CVD-SiO _x film 10 that fills a trench in a later step [see FIG. 2 (f)]. ] Is used as an etching stop layer when etching back.

The resist mask 7 is provided with an opening 8a corresponding to the narrow element isolation region I _n and openings 8b corresponding to both ends of the wide element isolation region I _W.
Since the openings 8a and 8b are patterned by a common mask, the absolute positions on the wafer may slightly deviate from the limit of the mask alignment accuracy as a whole, but the mutual positions of the openings 8a and 8b. The relationship will not be broken. Therefore, the design dimension D of the element forming region defined by the distance between the opening 8a and the opening 8b on the left side in the drawing is not affected by the misalignment of the mask.

Next, the polysilicon layer 6, the SiO _x film 2a, and the Si substrate 1 exposed in the openings 8a and 8b are sequentially dry-etched to form the openings as shown in FIG. 2 (e). Depth of about 0.3μ corresponding to 8a and 8b respectively
m trenches 9a and 9b were formed. Here, when the Si substrate 1 is dry-etched, for example, Cl ₂ / N ₂ mixed gas is used to effectively perform sidewall protection by deposits, trenches 9a and 9b having a forward tapered cross-sectional shape as shown in the drawing are formed. Can be formed. Trench 9a,
The shape of 9b is obtained by the CVD-SiO _x film 10 in a later step.
This is advantageous not only for facilitating the embedding by means of, but also for relaxing the electric field at the end of the element formation region and preventing field inversion on the side wall surface.

Next, as shown in FIG. 2F, as an example, O which is excellent in step coverage (step coverage)
₂ / TEOS-based plasma CVD method CVD-SiO
_{The x} film 10 was deposited on the entire surface of the wafer to a thickness of about 400 nm, and the trenches 9a and 9b were buried almost flatly.

Subsequently, the CVD-SiO _x film 10 is RI
Etch back with E, and as shown in FIG. 2 (g), CVD-Si is formed inside the trenches 9a and 9b, respectively.
The O _x films 10a and 10b are left. This etch back is
For example, it was carried out while monitoring the emission spectrum, and after the polysilicon layer 6 was exposed on the entire surface of the wafer, it was finished as early as possible. This is a CVD-SiO _x film 10
This is to ensure that the protrusion heights of a and 10b from the surface of the Si substrate 1 are as large as possible. Such a projecting shape is effective from the viewpoint of securing a long effective element separation distance, relaxing the electric field at the channel end portion of the MOS-FET, and suppressing field inversion at the side wall portion.

Next, as shown in FIG. 2 (h), RI
The polysilicon layer 6 is removed by E, and the channel
As an example, B (boron) is used as an ion accelerating voltage of 150 keV and a dose of 4 × 1 in order to introduce impurities for stopping.
Ions were implanted under the condition of 0 ¹² / cm ² .

Further, the SiO _x film 2a was removed by wet etching using a dilute hydrofluoric acid solution, and element isolation as shown in the schematic sectional view of FIG. 3 and its top view was completed. As described above, according to the present invention, the large element isolation region I _w is formed by CVD-SiO _x embedded in the selective oxidation isolation film 5 and the two trenches 9b, 9b arranged on both sides thereof.
It is composed of the membrane 10b.

The state shown here is a case where the selective oxidation separation film 5 is displaced to the right by the alignment error E from the design position A indicated by the alternate long and short dash line. Alternatively, on the contrary, it may be considered that the trenches 9b and 9b are displaced to the left side. In any case, however, the misalignment of the masks of the selective oxidation isolation pattern and the trench pattern, or the dimensional conversion difference generated in the process of forming the selective oxidation isolation film 5 by the LOCOS method is absorbed in the wide element isolation region. To be done. Therefore, due to these factors, the width (distance d) of the element isolation region as in the conventional example shown in FIG.
There is no risk of fluctuations in

It should be noted that the present invention is not limited to the above-mentioned embodiment, and various changes can be made in the details of the process. For example, the formation of the trenches 9a and 9b and the filling of the trenches 9a and 9b with the CVD-SiO _x films 10a and 10b are described in IEDM 92, p. As described in Nos. 275 to 278, it can also be performed after forming the first polysilicon layer for forming the gate electrode.

If the surface of the CVD-SiO _x film 10 is once flattened by using a flattening film such as a BPSG film and then etched back, the CVD-SiO _x films 10a, 10b filled in the trenches 9a, 9b are etched. The surface of 10b can be flattened. Furthermore, if the timing of ion implantation for channel stop is set immediately after forming the trenches 9a and 9b, the impurities can be introduced into a deeper region in the Si substrate 1.

[0035]

As is apparent from the above description, when the present invention is applied, it is necessary to use a trench and a selective oxide isolation film together to form a wide element isolation region and a narrow element isolation region. In the manufacturing of, the size of the element formation region can be accurately defined without depending on the size conversion difference of the selective oxidation separation film and the mask alignment accuracy. Further, as described above, since the dimensional conversion difference in the ROSOS method can be absorbed inside the wide element isolation region, it is not necessary to pursue the thinning of the pad SiO _x film so highly. As a result, it is possible to reduce the parasitic capacitance between the Si substrate and the first polysilicon layer for forming the gate electrode formed in the subsequent step, and improve the operating speed of the FET formed in the element formation region. It will be possible.

Since the present invention can be carried out only by changing the mask pattern of the conventional selective oxidation separation film and trench, it does not involve any additional steps and is extremely excellent in productivity and economy.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a process example to which the present invention is applied in the order of steps, (a) showing a state in which a pad SiO _x film and a SiN _x film are sequentially formed on a Si substrate, (b). Is a state in which the selective oxidation separation film is formed using the SiN _x film as a mask, and (c) is the SiN _x film and the pad SiO _x.
The state where the film is removed, and (d) shows the state where the polysilicon layer is entirely deposited and the resist mask is formed.

FIG. 2 is a schematic cross-sectional view showing the continuation of the process of FIG. 1, in which (e) shows a state in which a trench is formed by RIE,
(F) is a state where the CVD-SiO _x film is entirely deposited,
(G) is a state in which the CVD-SiO _x film is etched back,
(H) shows the state where the polysilicon layer is removed.

FIG. 3 is a schematic cross-sectional view showing a completed state of element isolation and a plan view of the pattern.

FIG. 4 is a schematic cross-sectional view showing a conventional element isolation state and a plan view of the pattern.

[Explanation of symbols]

1 ... Si substrate 2 ... pad SiO _x film 2a ... SiO _x film 3 ... SiN _x film 4 ... opening 5 ... selective oxide separation film 6 ... polysilicon layer 7・ ・ ・ Resist masks 8a, 8b ・ ・ ・ Openings 9a, 9b ・ ・ ・ Trenchs 10, 10a, 10b ・ ・ ・ CVD-SiO _x film I _n・ ・ ・ Narrow element isolation region I _w・ ・ ・ Wide element Isolation area D ... Design distance (between element isolation areas)

Claims (2)

[Claims] 1. A semiconductor device manufacturing method for manufacturing a semiconductor device having a relatively narrow first element isolation region and a relatively wide second element isolation region, wherein the first element isolation region is a trench. The method for forming a semiconductor device is characterized in that the second element isolation region is configured such that both ends defining the width thereof are trenches and regions sandwiched by the trenches are selectively oxidized isolation films. . 2. A selective oxidation isolation film is formed in the second element isolation region, and then a trench is collectively formed in both the second element isolation region and the first element isolation region. The method for manufacturing a semiconductor device according to claim 1.