JPS63129709A - Counter - Google Patents

Abstract

PURPOSE:To attain stable count by detecting whether or not a reset signal is close to a predetermined edge of a clock signal and starting the count from the edge of the next clock signal sequentially. CONSTITUTION:A leading (trailing) close detection circuit 13 (12) outputs a pulse output 13a (12a) rising with a delay of a predetermined time (t) from the trailing of a reset signal when the trailing of the reset signal 7 is close before and after the leading (trailing) of the clock signal 1a and descending at the leading of the next clock signal. An output 15a rising by the leading of the output 13a and descending at the leading of the output 12a is obtained from a flip-flop 15. The output 15a is fed to a changeover circuit 16 as a control signal, and a signal 10a is selected when the output 15a is at a high level and an output 16a is selected from a signal 11a when the output 15a is at a low level. The output 16a is fed to a counter 7 as a reset to count the clock signal 6.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a counter device that sequentially counts clock pulses in response to the arrival of a reset signal.

2. Description of the Related Art In recent years, counter devices have been used in various fields such as computers and image memories.

FIG. 6 shows an example of the use of a counter device in an image memory device, in which 1 is a clock signal generator, and its output, a clock signal 1a, is applied to a counter 2. In FIG.

Reference numeral 3 denotes a horizontal and vertical synchronizing signal generating circuit, whose output horizontal and vertical synchronizing signals are applied to a monitor television receiver 4 to control its deflection system.

Further, a signal phase-synchronized with the horizontal and vertical synchronization signals is applied to the counter 2 as a reset signal 7, and the counter 2
is configured to newly start counting the clock signal upon arrival of the reset signal.

The count value of counter 2 is stored in the image memory (R
OM) 5, the image information of the address corresponding to the count value is outputted, and is displayed on the monitor television receiver 4.

Problems to be Solved by the Invention In the above configuration, when counting the number of pulses of the clock signal 1a using the reset signal 7 as shown in the waveform diagram of FIG. A method is adopted in which the number of rises of the clock signal 1a is counted from the bottom.

However, if the reset pulse 7 shown in FIG. 6 falls just before the rising edge of the clock signal 1a, as in the first pulse aa, the counter 2 counts from the rising edge of the clock signal 1a immediately after that. However, when the clock signal falls immediately after the rising edge of the clock signal, like the second pulse 7b of the reset signal 7, the counter 2 starts counting from the rising edge of the next clock signal. I will do it.

That is, the count output e due to the reset pulses 7a and 7b
A time delay of approximately one clock pulse occurs.

Generally, the reset signal and the clock signal are input through different paths, so there is a slight phase difference between them due to differences in the temperature characteristics of each element in the previous stage circuit, and as described above, the reset signal and clock signal are input through different paths. There may be repeated instances where a signal immediately precedes or immediately follows a clock pulse.

When this occurs in the image memory device shown in FIG. 6, there is a problem in that flickering occurs in the reproduced image.

In view of this problem, the present invention provides a counter device that does not cause flickering in reproduced images.

Means for Solving the Problems The counter device of the present invention, when sequentially counting one predetermined rising edge or falling edge of a clock signal in response to the arrival of a reset signal, is configured to detect whether or not the clock signal is close to a predetermined edge of the clock signal, and if so, to start counting sequentially from the edge of the next clock signal. .

According to the above configuration, when starting counting, it is detected whether or not a counting error is likely to occur, that is, a state in which the reset signal is close to the edge of the clock signal to be counted. In this case, counting is started from the next clock signal, so even if a slight phase change occurs between the reset signal and the clock signal, the count value will not change.

Embodiment An embodiment of the counter device of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a counter device of the present invention.

In FIG. 1, 8.9 are input terminals for the reset signal 7 and the clock signal 1a, respectively, and the reset signal 7 input to the input terminal 8 is input to the first and second D-type 7 lip-flop circuits 10.11. The voltage is applied to each of the terminals 1 and 2 to the approach detection circuit 12 on the falling edge and the approach detection circuit 13 on the rising edge.

Further, the clock signal 1a input to the input terminal 9 is
The rising edge of the CK terminal of the D-type flip-flop circuit 11 is applied to the approach detection circuit 13, and the inverter 1
CK of the first D-type flip 70 tube circuit 1o through 4
A terminal and a falling edge are applied to the approach detection circuit 12.

The rising edge approach detection circuit 13 has a configuration as described below, and when the falling edge of the reset signal 7 is close to the rising edge of the clock signal 1a as shown in FIG. The pulse output 13a rises after a predetermined time t (approximately % of the clock signal period) after the falling edge of the signal, and falls at the rising edge of the next clock signal. With a similar configuration, when the falling edge of the reset signal 7 is close to the falling edge of the clock signal 1a, the falling edge of the reset signal 7 is delayed by a predetermined time t from the rising edge of the clock signal 1a. , the pulse output 12a falls at the next rising edge of the clock signal.
This outputs the following.

Further, from the first D-type flip-flop circuit 10, the reset signal 7 falls at the fall of the clock signal 1a after the reset signal 7 (Low level), and the clock signal 7 falls after the reset signal rises (H4gh level). An output 10a that rises at the rising of 1a is created, and the second
The reset signal 7 is output from the D-type flip-flop circuit 11 of
An output 11a is output which rises at the rising edge of the clock signal after the falling edge of the reset signal and rising edge of the clock signal at the falling edge of the clock signal after the rising edge of the reset signal.

The respective outputs 12a and 13a of the rain detection circuit 12.13 are applied to the flip 70 knob 16, and an output 15a is obtained, which rises when the output 13a rises and falls when the output 12a rises.

This output 15a is applied to the switching circuit 16 as a control signal, and during the period when the output 15a is at the NO level, the signal 10a is
During the low level period, the signal 11a is selected as the output 16a, and this output 16a is used as the reset signal to control the counter 1.
7 to count the clock signal 6.

That is, as shown in FIG. 2, when the falling edge of the reset signal 7 is close to the rising edge of the clock signal 1a, the next falling edge of the clock signal 1a will rise in synchronization with the rising edge of the clock signal 1a. Create pulse 10a and apply this pulse 1
Since 0a is used as the reset signal 16a, even if the falling edge of the reset signal 7 shifts back and forth relative to the rising edge of the clock signal 1a, counting always starts from the rising edge of the next clock signal. This means that stable counting can be expected.

FIG. 3 is a block diagram showing an embodiment of the approach detection circuit 13 shown in FIG.
and is applied to the third D-type 7-lip-flop circuit 19 as a signal 7a delayed by a predetermined time t (approximately % of the clock signal period) by the first delay circuit 18.

Further, the clock signal 1a applied to the input terminal 9 is applied to the third flip-flop circuit 19, and
Signal 1 delayed by time t) by second delay circuit 21
A signal b is applied to the CK terminal of the fourth two-nine-fifth-one-fifth circuit 2o.

The Q output 19a of the third D-type flip-flop circuit 19 is connected to the first and second AND gate circuits 22, 24 and NO.
The Q output 20a of the fourth D-type flip-flop circuit 2o is applied to the R gate circuit 23, the Q output is applied to the first AND gate circuit 22 and the NOR gate circuit 23, and the Q output is applied to the second
is applied to the AND gate circuit 24.

The output 22a of the first AND gate circuit 22 is applied as a signal 22b to the SET terminal of the flip-flop circuit 26 via the third delay circuit 26, and the output 23a of the NOR gate circuit 23 is applied to the RESET terminal of the flip-flop circuit 26. has been done.

The output 24a of the second AND gate circuit 24 and the output 26a of the flip-flop circuit 26 are
is applied to the gate circuit 27, and the signal 13a is applied as its output.
is obtained.

In the embodiments described above, the rise of the clock signal is counted successively by the reset signal, but it is also possible to count the fall of the clock signal in a similar manner.

Effects of the Invention As described above, according to the present invention, stable counting can be expected even when the phase relationship between the reset signal and the clock signal varies slightly over time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the counter device of the present invention, FIG. 2 is a waveform diagram showing the same operation, FIG. 3 is a block diagram of the main part, and FIG. 4 is a block diagram showing the operation of the same main part. Waveform diagram shown, No. 5
The figure is a block diagram of a conventional image memory device, and FIG. 6 is a waveform diagram of the same operation. 7... Counter, 8... Reset signal input terminal, 9... Clock signal input terminal, 10.
11...D type flip 70 tube circuit, 12...
... Rising approach detection circuit, 13... Falling approach detection circuit, 15... Flip-flop, 16... Switching circuit.

Claims (1)

[Claims] When sequentially counting one predetermined edge of the rising or falling edge of the clock signal from the arrival of the reset signal, it is detected whether the reset signal is close to the predetermined edge of the clock signal. 1. A counter device comprising a detection means, and starts counting from the edge of the next clock signal when the two clock signals are close to each other.