JPS63129635A - Substrate with bump - Google Patents
Substrate with bumpInfo
- Publication number
- JPS63129635A JPS63129635A JP61277488A JP27748886A JPS63129635A JP S63129635 A JPS63129635 A JP S63129635A JP 61277488 A JP61277488 A JP 61277488A JP 27748886 A JP27748886 A JP 27748886A JP S63129635 A JPS63129635 A JP S63129635A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- plating
- substrate
- roughness
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 18
- 238000007747 plating Methods 0.000 claims abstract description 24
- 230000003746 surface roughness Effects 0.000 claims abstract description 23
- 229910052782 aluminium Inorganic materials 0.000 claims description 15
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 6
- 239000011889 copper foil Substances 0.000 abstract description 6
- 239000000463 material Substances 0.000 abstract description 4
- 239000004020 conductor Substances 0.000 abstract description 3
- 238000009713 electroplating Methods 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 8
- 229910052737 gold Inorganic materials 0.000 description 8
- 239000010931 gold Substances 0.000 description 8
- 229910052759 nickel Inorganic materials 0.000 description 6
- 229910000831 Steel Inorganic materials 0.000 description 5
- 239000010959 steel Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 239000011888 foil Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- LCPVQAHEFVXVKT-UHFFFAOYSA-N 2-(2,4-difluorophenoxy)pyridin-3-amine Chemical compound NC1=CC=CN=C1OC1=CC=C(F)C=C1F LCPVQAHEFVXVKT-UHFFFAOYSA-N 0.000 description 1
- 208000025174 PANDAS Diseases 0.000 description 1
- 208000021155 Paediatric autoimmune neuropsychiatric disorders associated with streptococcal infection Diseases 0.000 description 1
- 240000000220 Panda oleosa Species 0.000 description 1
- 235000016496 Panda oleosa Nutrition 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- CHQMHPLRPQMAMX-UHFFFAOYSA-L sodium persulfate Substances [Na+].[Na+].[O-]S(=O)(=O)OOS([O-])(=O)=O CHQMHPLRPQMAMX-UHFFFAOYSA-L 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子（以下工Ｃチップという）のアルミ
パッドに直接接合するためのパンダをフィンガー上に有
するバンプ付基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bumped substrate having a panda on a finger for direct bonding to an aluminum pad of a semiconductor element (hereinafter referred to as a C-chip).
従来のバンプ付基板は、特公昭５・８−２６８２８や特
公昭５９−１７９８０のごとく、フィンガーの先端部に
メブキによりバンプを形成したり、フィンガーの中程を
八−７エツチングすることによりその先端にバンプを形
成することが知られていた。第３図はその一例であるが
、フィンガー４の先端にバンプ５が形成されており、ま
た前記引用例では言及されて−ないが、通常バンプ５の
表面は平滑な状態であった。Conventional boards with bumps are made by forming bumps on the tips of the fingers with a mesh plate, or by etching the middle part of the fingers, as in Japanese Patent Publication No. 5.8-26828 and Japanese Patent Publication No. 59-17980. was known to form bumps. As shown in FIG. 3, a bump 5 is formed at the tip of the finger 4, and although it is not mentioned in the cited example, the surface of the bump 5 is usually smooth.
しかしながら、前述の従来技術では、ＩＣチップ（７）
フルミパッドとフィンガーのバンプとを熱圧層もしくは
超音波を併用した熱圧着により接合しようとしても、ア
ルミパッドと接触するバンク表面が平滑なためアルミパ
ッド表面に形成されている酸化膜を破壊除去することが
できず、接合が不安定で接合強度が確保できないという
問題点を有していた。However, in the above-mentioned conventional technology, the IC chip (7)
Even if an attempt is made to bond the Fulmi pad and the finger bump by thermocompression bonding using a thermocompression layer or ultrasonic waves, the oxide film formed on the aluminum pad surface will be destroyed and removed because the bank surface in contact with the aluminum pad is smooth. However, there were problems in that the bonding was unstable and the bonding strength could not be ensured.
そこで本発明はこのような問題点を解決するもので、そ
の目的とするところは工Ｃチップのアルミパッドと安定
して接合可能なバンク付基板を提供するところにある。The present invention is intended to solve these problems, and its purpose is to provide a banked substrate that can be stably bonded to aluminum pads of engineered C chips.
本発明のバンプ付基板は、牛導体素子のアルミパッドに
直ＦＩ！接合するためのバンクをフィンガー上に有する
バンプ付基板において、前記バンプの表面の面粗度をメ
ッキによって拡大増長させたことを特徴とする。The bumped board of the present invention can be directly attached to the aluminum pad of the conductor element! A substrate with bumps having banks for bonding on fingers is characterized in that the surface roughness of the bumps is enlarged and increased by plating.
第１図は本発明の実施例におけるバンク付基板の断面図
であり、１は＆ ＩＪイミドやガラエ〆等の基板、２は
接着剤、３は導体パターン、４はフィンガー、５はバン
プである。バンプ５はフィンガー４の中程をハーフエツ
チングすることにより形成されており、またバンク５０
表面は下層にニッケル、上層に金メッキを施し、下地の
面粗度を拡大増長している。ところで、ＩＣチップのア
ルミパッドとバンクとを接合する際、基板のバンプ表面
の粗い凸部がアルミパッド表面にくい込みつつ変形する
ことにより、アルミパッド表面の酸化膜を破壊し、アル
ミパッド内部の清浄な金属面と基板バンプ金属とが合金
を形成し、強固な接合を得ることができる。従ってバン
プ５の表面の面粗度が、接合強度に大きく影響し、面粗
度が適度に粗い方が接合強度は大きく、後述するように
最大表面粗さく以下Ｒｍ５ＬＸという）が５〜２０μｍ
であることが望ましい、尚このときのバンプの表面状態
は梨地状でもすじ目状でもかまわない０本実施例におい
て下地の導体パターン３が形成される導体には電解銅箔
な用いており、バンプ表面となる銅箔裏面は接着剤２を
介して基材１との密層性を上げるため、銅箔製造時に電
解鋼メッキの析出粒子により粗化されて面粗度はＲｍａ
ｗ ５〜１２μ隅程度となっている。しかるにこれが表
面処理、エツチング等のバンプ付基板製造工程を経るこ
とによりＲｍ＆１３〜８μｍ目度に減“少する。ここで
尖端部に電流が集中することを利用し、１！Ｌ気メツキ
により下層にニッケル、上層に金をメッキを施すことに
より、バンプ表面の微小な凸部を増長させる。８ｇ２図
はバンプ部分を拡大した断面図で、鋼箔６の表面にニッ
ケル８と金９がメッキされており、その厚みは凸部７に
電流が集中するため凸部７で厚くその周囲では薄くなっ
ており、バンプ５の表面の面粗度が大きくなっている。FIG. 1 is a cross-sectional view of a banked board according to an embodiment of the present invention, in which 1 is a substrate made of &IJ imide or glass finish, 2 is an adhesive, 3 is a conductive pattern, 4 is a finger, and 5 is a bump. . The bump 5 is formed by half-etching the middle of the finger 4, and the bank 50 is formed by half-etching the middle of the finger 4.
The surface is plated with nickel on the bottom layer and gold on the top layer to increase the roughness of the underlying surface. By the way, when bonding the aluminum pad and bank of an IC chip, the rough convex portions on the bump surface of the substrate deform while digging into the surface of the aluminum pad, destroying the oxide film on the surface of the aluminum pad and preventing the inside of the aluminum pad from being cleaned. The metal surface and the substrate bump metal form an alloy, and a strong bond can be obtained. Therefore, the surface roughness of the bump 5 has a large effect on the bonding strength, and the rougher the surface roughness, the greater the bonding strength, and as described later, the maximum surface roughness (hereinafter referred to as Rm5LX) is 5 to 20 μm.
It is desirable that the surface condition of the bump at this time be satin-like or streaky. The back surface of the copper foil, which will become the front surface, is roughened by precipitated particles of electrolytic steel plating during copper foil manufacturing to increase the layer density with the base material 1 via the adhesive 2, and the surface roughness is Rma.
w The corner is approximately 5 to 12μ. However, this is reduced to about Rm & 13~8μm by going through the manufacturing process of the bumped board such as surface treatment and etching.Here, by utilizing the fact that the current concentrates at the tip, 1!L plating is applied to the lower layer. By plating nickel and gold on the upper layer, the minute protrusions on the bump surface are increased. Figure 8g2 is an enlarged cross-sectional view of the bump part, and the surface of the steel foil 6 is plated with nickel 8 and gold 9. Since the current is concentrated on the bump 7, the thickness is thick at the bump 7 and thinner around the bump 7, and the surface roughness of the bump 5 is increased.
この現象はメッキ条件における電流密度が高くなる程顕
著となるため、メッキャナが出ない範囲でできるだけ高
くする１本実施例のバンプ付基板ではニッケルをα５〜
１μ虚に薄メッキした後、金を電流密度２．５Ａ／一時
間１分でメッキすることにより、平均金メッキ厚１．５
μ肩、バンプ表面ではＲｍ＆！にｉｓ−で２〜６μｍの
面粗度拡大を得ている。尚上記のメッキ装置やメッキ液
により異なるもので、同じメッキ厚を得るためには許容
電流密度の上限近くで、時間を短かくしてメッキすれば
大きな面粗度を得ることが可能である。This phenomenon becomes more pronounced as the current density increases under plating conditions, so the current density should be as high as possible without causing plating.In the bumped board of this embodiment, nickel is
After plating thinly to 1 μm, the average gold plating thickness was 1.5 μm by plating at a current density of 2.5 A/hour and 1 minute.
μ shoulder, Rm&! on the bump surface! The surface roughness was enlarged by 2 to 6 μm in IS-. Note that this varies depending on the plating apparatus and plating solution mentioned above, but in order to obtain the same plating thickness, it is possible to obtain a large surface roughness by plating near the upper limit of the allowable current density and plating for a short time.
第１表は４水準の面粗度（Ｒｍａｗ ）を有する鋼箔に
平均金メッキ厚１．５μ島を施す各金メツキ条件（電流
密度）におけるバンプトータル面粗度（Ｒｍａｘ ）と
接合強度、接合歩留シのデータを示したものである。Table 1 shows the bump total surface roughness (Rmax), bonding strength, and bonding step under each gold plating condition (current density) when applying gold plating with an average thickness of 1.5μ to steel foil having four levels of surface roughness (Rmax). This shows the data for Rushi.
ここでバンプ寸法は６０μ隅角、ニッケルメッキ厚１μ
ｍ１接合強度とはフィンガー中央を垂直上方に引き上げ
接合部もしくはフィンガーが破壊するときの強度である
。第１表かられかるように、電流密度が２．５Ａ／−以
下では電流密度が高い程面粗度が大きく接合強度も高く
なっている。特にトータルの面粗度がＲｗａｘ ５μ馬
以上では安定した接合が得られており、素地の面粗度が
小さい場合、特にメッキによる面粗度の拡大増長が有効
である。一方＠箔の面粗度がＲｍ＆１１５μ馬では、鋼
箔が粗となり、フィンガー強度の低下傾向が見られる。Here, the bump dimensions are 60μ corner angle, nickel plating thickness 1μ
The m1 joint strength is the strength when the joint or finger breaks when the center of the finger is pulled vertically upward. As can be seen from Table 1, when the current density is 2.5 A/- or less, the higher the current density, the greater the surface roughness and the higher the bonding strength. In particular, stable bonding is obtained when the total surface roughness is Rwax 5 μm or more, and when the surface roughness of the substrate is small, it is particularly effective to increase the surface roughness by plating. On the other hand, when the surface roughness of @ foil is Rm & 115 μm, the steel foil becomes rough and there is a tendency for the finger strength to decrease.
金メッキ厚の適正値を考慮した場合トータルの面粗度は
Ｒｍａｘ ２０μｍ以下であることが望ましく、従って
トータルの面粗度の適正値はＲ１ａｘ５〜２０ ｐ ａ
である。When considering the appropriate value for the gold plating thickness, it is desirable that the total surface roughness is Rmax 20 μm or less, and therefore the appropriate value for the total surface roughness is R1ax 5 to 20 pa
It is.
上記の実施例はもともと面粗度の大きい電解鋼箔の裏面
にバンプを形成した場合であるが、面粗度が３μ罵以下
の電解６ｊｊ４箔の表面にバンプを形成する場合や圧延
鋼箔を用−る場合は、ブラシ研摩やサンドブラスト等の
機械的表面粗化もしくは過硫酸アンモン、過硫酸ソーダ
等の水溶液を用いた化学的表面粗化を行なりた後、メッ
キにより面粗度を拡大すれば、ｉｐｎ銅箔の裏面にバン
プを形成したと同様、接合状態の安定したバンプ付基板
を得ることが可能である。The above example is a case in which bumps are formed on the back side of electrolytic steel foil, which originally has a large surface roughness. If the surface is to be used, first roughen the surface mechanically by brush polishing or sandblasting, or chemically roughen the surface using an aqueous solution of ammonium persulfate, sodium persulfate, etc., and then expand the surface roughness by plating. For example, it is possible to obtain a bumped substrate with stable bonding, similar to when bumps are formed on the back surface of IPN copper foil.
尚、第４図は本発明のバンプ付基板１０を用いて工Ｃチ
ップ１１をボンディングした半導体装置１２の断面図で
、バンプ５とアルミパッド１５を位置合せした後、熱圧
着することにより得られる、なお、第４図の工０チップ
配置場所とは逆にして、フィンガー４のバンプ５を基材
１に対し反対向に設け、そのバンプ５に工Ｃチップのパ
ッドを接合するようにしてもよい。FIG. 4 is a cross-sectional view of a semiconductor device 12 in which a C-chip 11 is bonded using the bumped substrate 10 of the present invention, which is obtained by thermal compression bonding after aligning the bumps 5 and aluminum pads 15. Note that the bump 5 of the finger 4 may be provided in the opposite direction to the base material 1, and the pad of the chip C may be bonded to the bump 5, contrary to the location of the chip 0 shown in FIG. good.
以上述べたように本発明によれば、バンプ付基板のバン
プ表面の面粗度なメッキにより拡大増長することにより
、特に面粗度な５〜２０μｍにすればＩＯチップのアル
ミパッドとの接合において、アルミハツトの酸化膜を容
易に破壊することができ、基板のバンプと工Ｃチップの
アルミパッドとの接合強度及び安定性を著しく高めるこ
とができるという効果を有する。As described above, according to the present invention, by enlarging and increasing the surface roughness of the bump surface of the bumped board by plating the bump surface, especially when the surface roughness is made to be 5 to 20 μm, it is possible to improve the bonding with the aluminum pad of the IO chip. This has the effect of easily destroying the oxide film on the aluminum hat, and significantly increasing the bonding strength and stability between the bumps on the substrate and the aluminum pads on the C-chip.
第１図は本発明の実施例におけるバンプ付基板の断面図
、第２図は本発明の実施例におけるバンプ部の拡大断面
図、第５図は従来のバンプ付基板の断面図、第４図は本
発明の実施例におけるバンプ付基板を用いた半導体装置
の断面図である。
１・・・・・・・・・基 材
２・・・・・・・・・接着剤
５・・・・・・・・・導体ハターン
４・・・・・・・・・フィンガー
５・・・・・・・・・バンプ
６・・・・・・・・・銅 箔
７・・・・・・・・・凸 部
８・・・・・・・・・ニッケル
９・・・・・・・・・金
１０・・・・・・バンク付基板
１１・・・・・・工Ｃチップ
１２・・・・・・半導体装置
１Ｓ・・・・・・アルミパッド
以上
出願人 セイコーエブンン株式会社
第３図FIG. 1 is a sectional view of a bumped substrate according to an embodiment of the present invention, FIG. 2 is an enlarged sectional view of a bump portion in an embodiment of the present invention, FIG. 5 is a sectional view of a conventional bumped substrate, and FIG. 4 1 is a sectional view of a semiconductor device using a bumped substrate according to an embodiment of the present invention. 1...Base material 2...Adhesive 5...Conductor pattern 4...Finger 5... ......Bump 6...Copper foil 7...Convex portion 8...Nickel 9... ... Gold 10 ... Substrate with bank 11 ... Engineering C chip 12 ... Semiconductor device 1S ... Aluminum pad or more Applicant Seiko Even Co., Ltd. Figure 3
Claims (1)
をフィンガー上に有するバンプ付基板において、前記バ
ンプの表面の面粗度をメッキによって拡大増長させたこ
とを特徴とするバンプ付基板。1. A bumped substrate having bumps on fingers for direct bonding to aluminum pads of a semiconductor element, characterized in that the surface roughness of the bumps is enlarged and increased by plating.
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61277488A JPS63129635A (en) | 1986-11-20 | 1986-11-20 | Substrate with bump |
| US07/017,419 US4786545A (en) | 1986-02-28 | 1987-02-24 | Circuit substrate and method for forming bumps on the circuit substrate |
| GB8704425A GB2187331B (en) | 1986-02-28 | 1987-02-25 | Method of forming an integrated circuit assembly or part thereof |
| GB8901825A GB2211351B (en) | 1986-02-28 | 1989-01-27 | Method of forming an integrated circuit assembly or part thereof |
| SG1492A SG1492G (en) | 1986-02-28 | 1992-01-08 | Method of forming an integrated circuit assembly or part thereof |
| SG1392A SG1392G (en) | 1986-02-28 | 1992-01-08 | Method of forming an integrated circuit assembly or part thereof |
| HK35993A HK35993A (en) | 1986-02-28 | 1993-04-15 | Method of forming an integrated circuit assembly or part thereof |
| HK36093A HK36093A (en) | 1986-02-28 | 1993-04-15 | Method of forming an integrated circuit assembly or part thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61277488A JPS63129635A (en) | 1986-11-20 | 1986-11-20 | Substrate with bump |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63129635A true JPS63129635A (en) | 1988-06-02 |
| JPH0478175B2 JPH0478175B2 (en) | 1992-12-10 |
Family
ID=17584292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61277488A Granted JPS63129635A (en) | 1986-02-28 | 1986-11-20 | Substrate with bump |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63129635A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997016848A1 (en) * | 1995-10-31 | 1997-05-09 | Ibiden Co., Ltd. | Electronic part module and process for manufacturing the same |
| WO1999012197A1 (en) * | 1997-08-29 | 1999-03-11 | Hitachi, Ltd. | Compression bonded semiconductor device and power converter using the same |
| EP1014445A1 (en) * | 1998-12-24 | 2000-06-28 | Shinko Electric Industries Co. Ltd. | Carrier substrate for producing semiconductor device |
| JP2010087229A (en) * | 2008-09-30 | 2010-04-15 | Sanyo Electric Co Ltd | Semiconductor module, method of manufacturing semiconductor module, and portable device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52124865A (en) * | 1976-04-13 | 1977-10-20 | Sharp Corp | Semiconductor device |
| JPS55138864A (en) * | 1979-04-16 | 1980-10-30 | Sharp Corp | Method of fabricating semiconductor assembling substrate |
-
1986
- 1986-11-20 JP JP61277488A patent/JPS63129635A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52124865A (en) * | 1976-04-13 | 1977-10-20 | Sharp Corp | Semiconductor device |
| JPS55138864A (en) * | 1979-04-16 | 1980-10-30 | Sharp Corp | Method of fabricating semiconductor assembling substrate |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997016848A1 (en) * | 1995-10-31 | 1997-05-09 | Ibiden Co., Ltd. | Electronic part module and process for manufacturing the same |
| WO1999012197A1 (en) * | 1997-08-29 | 1999-03-11 | Hitachi, Ltd. | Compression bonded semiconductor device and power converter using the same |
| EP1014445A1 (en) * | 1998-12-24 | 2000-06-28 | Shinko Electric Industries Co. Ltd. | Carrier substrate for producing semiconductor device |
| JP2010087229A (en) * | 2008-09-30 | 2010-04-15 | Sanyo Electric Co Ltd | Semiconductor module, method of manufacturing semiconductor module, and portable device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0478175B2 (en) | 1992-12-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |