JPS6021534A - Circuit mounting structure - Google Patents

Circuit mounting structure

Info

Publication number
JPS6021534A
JPS6021534A JP58128959A JP12895983A JPS6021534A JP S6021534 A JPS6021534 A JP S6021534A JP 58128959 A JP58128959 A JP 58128959A JP 12895983 A JP12895983 A JP 12895983A JP S6021534 A JPS6021534 A JP S6021534A
Authority
JP
Japan
Prior art keywords
substrate
solder
chip
thickness
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58128959A
Other languages
Japanese (ja)
Inventor
Kunio Sakuma
佐久間 国雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP58128959A priority Critical patent/JPS6021534A/en
Publication of JPS6021534A publication Critical patent/JPS6021534A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Clocks (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To realize reduction in thickness of a wrist watch while keeping the reliability level of a circuit block thereof by face down bonding of integrated circuit element having a solder bump to a flexible circuit substrate with copper foil and keeping an interval between substrate conductor pattern surface and integrated circuit element surface to the particular range. CONSTITUTION:An IC chip with a side of 2-4mm. having a solder bump 3 comprising a nickel core 2 in the thickness of about 15mum is used and a flexible circuit substrate with copper foil is used as a substrate 5. The IC chip 1 and substrate lead is aligned in position and are heated for joining. On the occasion of such heating, the IC chip is heated from the rear surface. Thereby, the surface of nickel core 2 in the solder bump 3 and substrate lead surface are forced to join in such a condition as they are in contact and clearance between the IC chip and substrate is always kept at 10-20mum. The solder perfectly surrounds the substrate lead up to the side surface by setting amount of solder of bump to the thickness of about 40mum and the joining condition where edge short-circuit by flow of solder is not generated can be obtained.

Description

【発明の詳細な説明】 本発明は腕時計用回路ブロックの実装構造に関する。[Detailed description of the invention] The present invention relates to a mounting structure of a circuit block for a wristwatch.

一般に、腕時計においては、集積回路素子c以下ヱCチ
ップと呼ぶ)の回路基板への実装方法として、ワイヤー
ボンディング方式、及びテープキャリア方式、フェース
ダウンボンディング方式が用いられている。中でも特に
薄型・小型化指向の強Lnアナログ時計においてはテー
プキャリア方式あるいはフェースダウンボンディング方
式が主流となっている。これらの方式の実装スペースは
、たとえばICチップの大きさを一辺asaab厚み0
.3 wとした場合、テープキャリア方式の場合には、
厚み方向では基板導体パターン表面からICチップ裏面
まで約420μ、平面方向では3.2×3.2m”必要
としている。またフェースダウンボンディング方式の場
合には、厚み方向で約400力、平面方向では3×3−
必要としているのが現状である。
Generally, in wristwatches, the wire bonding method, tape carrier method, and face-down bonding method are used as methods for mounting an integrated circuit element (hereinafter referred to as "C chip") on a circuit board. Among these, the tape carrier method or the face-down bonding method is the mainstream for strong Ln analog watches that are particularly oriented toward thinness and miniaturization. The mounting space for these methods is, for example, the size of the IC chip on one side asaab and the thickness as 0.
.. In the case of 3w, in the case of tape carrier method,
In the thickness direction, approximately 420μ from the surface of the board conductor pattern to the back surface of the IC chip is required, and in the plane direction, 3.2 x 3.2m'' is required.Furthermore, in the case of the face-down bonding method, approximately 400 force is required in the thickness direction, and approximately 400μ in the plane direction. 3×3−
The current situation is what we need.

一方、近年腕時計の薄型・小型化のニーズは増2− 々高ま〕、前記の現状の実装スペースでは十分にその要
求を満足できない水準に達してきている。
On the other hand, the need for wristwatches to be thinner and more compact has been increasing in recent years, and the current mounting space has reached a level where these demands cannot be fully met.

しかるに、テープキャリア方式においては、エツジショ
ート防止の点からフィンガーリードのICチップ方向へ
の曲げ成形が約100μ程度必要なこと、及び腕時計設
計上の点から基板の銅箔側にICチップを配置しなけれ
ばならない場合が多いことなどから、辷れ以上の薄型化
は困難である。
However, in the tape carrier method, in order to prevent edge shorts, it is necessary to bend the finger leads in the direction of the IC chip by about 100μ, and from the viewpoint of wristwatch design, the IC chip must be placed on the copper foil side of the board. It is difficult to reduce the thickness beyond the width of the legs, as it is often necessary to do so.

またフェースダウンボンディング方式においても、基板
とICチップとの熱膨張係数差に基づく熱応力に対する
接合部信頼性の点から、接合後の半田量サスなわちIC
チップ表面と基板導体パターン表面との間隙は大である
ほど望ましく、一般に図2に示すように、Hは100μ
以上必要であるといわれてお)、さらに極端にその接合
厚みを減少させることは困難とされている。
Also, in the face-down bonding method, from the viewpoint of joint reliability against thermal stress due to the difference in thermal expansion coefficient between the substrate and the IC chip, the amount of solder after bonding, that is, the IC
The larger the gap between the chip surface and the substrate conductor pattern surface, the more desirable it is, and generally H is 100μ as shown in FIG.
However, it is difficult to further reduce the bonding thickness to an even greater extent.

本発明はかかる欠点を除去したもので、その目的は、腕
時計の回路ブロックとして必要な信頼性水準を保ちつつ
、IC表面と基板導体パターン表面との間隙を従来の約
1/6の15μ程度とし、約匍3− μの薄型化を可能とする改良型のフェースダウンボンデ
ィング方式を提供することである。
The present invention eliminates such drawbacks, and its purpose is to reduce the gap between the IC surface and the substrate conductor pattern surface to about 15μ, about 1/6 of the conventional one, while maintaining the reliability level required for a wristwatch circuit block. An object of the present invention is to provide an improved face-down bonding method that enables a thickness reduction of approximately 3-μ.

以下実施例に基づいて1本発明の詳細な説明する。本発
明では内部に約15μ厚のニッケル芯を持つ半田バンプ
を有する一辺2〜4間のICチップを用い、基板として
け銅箔付フレキシブル回路基板を用いる。そしてICチ
ップと基板リードとを位置合わせ後、加熱接合させる。
The present invention will be described in detail below based on examples. In the present invention, an IC chip having 2 to 4 sides on each side and having solder bumps with a nickel core of about 15 .mu.m thick inside is used, and a flexible circuit board with copper foil is used as the substrate. After aligning the IC chip and the substrate leads, they are heated and bonded.

この加熱の際に、ICチップを裏面より加圧することに
より、強制的に半田バンプ内のニッケル芯表面と基板リ
ード表面とを接触させるような状態にて接合を行なわせ
る。これにより工Cチップと基板の間隙を常に一定に保
つことができる。またバンプの半田量として厚み約40
μとすることにより図1に示すように、接合後の状態と
して、半田が基板リードの側面まで完全に包み込む状態
となり、かつ半田の流出によるエツジショートが発生し
ない接合状態とすることができる。
During this heating, the IC chip is pressurized from the back side to forcibly bring the surface of the nickel core within the solder bump into contact with the surface of the substrate lead, thereby performing the bonding. This allows the gap between the C-chip and the substrate to be kept constant. Also, the thickness of the bump is approximately 40 mm as the amount of solder.
By setting μ, as shown in FIG. 1, it is possible to achieve a state after bonding in which the solder completely wraps up to the side surfaces of the substrate leads, and a bonded state in which edge shorts due to solder outflow do not occur.

以上のような実装構造とすることにより、図1に示すI
Cチップ表面と基板導体表面との間隙H4− を約15μと極めて小さくできるとともに、腕時計とし
て十分な水準の接合信頼性を確保することができる。そ
れは次の理由による。
By adopting the above-mentioned mounting structure, the I shown in FIG.
The gap H4- between the C chip surface and the substrate conductor surface can be made extremely small to about 15 μm, and a sufficient level of bonding reliability for a wristwatch can be ensured. This is due to the following reason.

第1に、基板としてフレキシブル基板を用いるため基板
とXCチップとの熱膨張係数の差による半田接合部への
熱応力が、リジッド基板の場合よシも小さいため。
First, since a flexible board is used as the board, the thermal stress on the solder joint due to the difference in thermal expansion coefficient between the board and the XC chip is smaller than in the case of a rigid board.

第2に、アナログ式電子時計用のICチップは通常−辺
3wJ程度と小さいことから前述の熱応力の程度が比較
的小さいため。
Secondly, IC chips for analog electronic watches are usually as small as 3 wJ on a side, so the degree of thermal stress described above is relatively small.

第3に、基板とICチップの接合部において、基板導体
バタン側面にまで十分に半田をまわり込ませることによ
p1筒状の半田が、ニッケル芯と導体パターンとで形成
された径を包み込む状態にて接合する構造となるため、
ニッケル芯の15μに基板導体厚み分の35μが加算さ
れて、接合後の半田バルブ高さは約50μのものと等価
となカ、前述の熱応力が、極端には大きくならないため
Thirdly, at the joint between the board and the IC chip, by sufficiently encircling the solder to the side of the board conductor button, the p1 cylindrical solder wraps around the diameter formed by the nickel core and the conductor pattern. Since the structure is joined at
The height of the solder bulb after bonding is equivalent to approximately 50μ by adding 35μ for the thickness of the board conductor to the 15μ for the nickel core, and the aforementioned thermal stress does not become extremely large.

第4に、腕時計においては、使用するICチップはtl
とんどの場合1個のみであることから、コ5− ンヒューター等の多チップの場合に比較シて、ICチッ
プ】個あたシに要求される信頼性は比較的高くないため
Fourth, in wristwatches, the IC chip used is tl
Since in most cases there is only one IC chip, the reliability required for each IC chip is not relatively high compared to the case of multiple chips such as a computer.

以上のような要因の複合の結果、10年以上の保証ので
きる信頼性水準をもった接合が、この構造により達成す
ることができる。
As a result of the combination of the above factors, a bond with a reliability level that can be guaranteed for more than 10 years can be achieved with this structure.

具体的な実施例を以下に示す。Specific examples are shown below.

ICとしては、 チップ寸法 2*3 m X 3.Oruチップ厚 3
00μ バンプ構造 ニッケル芯 厚み15μ その上に半1)厚み40μ バンプ寸法 口180μ 厚み55μ 半田組成 10 % Bn 90 % Pb基板として
は 基材 ポリイミドテープ(厚み125μ)導体 35μ
厚銀箔 表面 金メッキ 接合部リード寸法 φ110μ 6一 モールド剤としては 軟質エポキシ樹脂 接合後の状態としては ICチップ表面と基板導体表面との 間隙 H15μ 接合部バンブ外寸法 約φ230μ なお、基板材質としては他にガフェボテープ。
As an IC, chip size is 2*3 m x 3. Oru chip thickness 3
00μ Bump structure Nickel core Thickness 15μ On top of that, half 1) Thickness 40μ Bump dimensions Mouth 180μ Thickness 55μ Solder composition 10% Bn 90% Pb Base material for substrate Polyimide tape (thickness 125μ) Conductor 35μ
Thick silver foil surface Gold plated joint lead dimensions φ110μ 6 - As a molding agent, soft epoxy resin After bonding, gap between IC chip surface and board conductor surface H15μ Joint bump outer dimension Approximately φ230μ In addition, other substrate materials are available. Gafebo tape.

及びBTレジンテープ、ポリエステルテープ等でも差し
つかえない。またバンブ芯としては銅でもよい、iた半
田組成に関しては5 % 8s9a%Pbあるいは60
 % Sn 40 tit F6など他の組成のもので
もよい、以上のように、本発明は腕時計として十分な信
頼性を保ちつつ、従来に比較して約90μの実装スペー
ス薄型化を可能にできること、さらに接合時に強制的に
圧力を加え、半田バンブを大きく変形させることにより
、表面の酸化膜を破壊できる゛ことから、フラックスを
使用することなく十分な強度の半田接合が可能であるこ
となど秀れた効果を有するものである。
Alternatively, BT resin tape, polyester tape, etc. may also be used. Copper may also be used as the bump core, and the solder composition may be 5% 8s9a%Pb or 60%.
% Sn 40 tit F6 or other compositions may be used.As described above, the present invention has the following advantages: while maintaining sufficient reliability as a wristwatch, it is possible to reduce the thickness of the mounting space by about 90μ compared to the conventional one; By forcibly applying pressure during bonding and greatly deforming the solder bump, the oxide film on the surface can be destroyed, making it possible to create solder bonds with sufficient strength without using flux. It is effective.

7−7-

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による腕時計用回路ICチップ実装構造
図、fα)は平面図、【b)は断面図。 第2図は従来の腕時計用回路ICチップ実装構造図、t
α1は平面図、1M+は断面図。 1・・工Cチップ 2・・バンブ金属芯 3・Φ本発明におけるバンブ半田部 4・参回路基板銅箔パターン 5e@フレキシブル回路基板 3−@・従来の方法のバンプ半田部 5′・・回路基板 以 上 出願人 株式会社諏訪精工舎 代理人 弁理士最 上 務 8− (α) 才2目
FIG. 1 is a diagram of a circuit IC chip mounting structure for a wristwatch according to the present invention, fα) is a plan view, and [b) is a sectional view. Figure 2 is a diagram of the conventional wristwatch circuit IC chip mounting structure.
α1 is a plan view, and 1M+ is a cross-sectional view. 1. C-chip 2. Bump metal core 3. Φ Bump solder portion 4 in the present invention. Circuit board copper foil pattern 5e@Flexible circuit board 3-@. Bump solder portion 5' in conventional method. Circuit Substrate and above Applicant Suwa Seikosha Co., Ltd. Agent Patent Attorney Mogami Tsumu 8- (α) 2nd year of age

Claims (2)

【特許請求の範囲】[Claims] (1) 回路ブロックにおいて、基板上して銅箔付きフ
レキシブル回路基板を用い、それに半田バンプを有する
集積回路素子をフェースダウンボンディングし、基板導
体パターン表面と集積回路素子表面との間隙■を10〜
20μに保ったことを特徴とする回路実装構造。
(1) In the circuit block, a flexible circuit board with copper foil is used on the board, an integrated circuit element having solder bumps is bonded face-down to it, and the gap between the surface of the board conductor pattern and the surface of the integrated circuit element is set to 10~10.
A circuit mounting structure characterized by keeping the thickness to 20μ.
(2)接合部の構造として、半田バンブ内に設けた厚み
10〜20μのニッケルあるいは銅の金属芯と、回路基
板の厚み18〜35μの銅箔パターンとが接し、かつ、
その金属芯及び導体パターンの外周部側面を、半田か筒
状に包み込む形状にて接合されている特許請求の範囲第
1項記載の回路実装構造。 −】−
(2) The structure of the joint is such that a nickel or copper metal core with a thickness of 10 to 20 μm provided in the solder bump is in contact with a copper foil pattern of 18 to 35 μm in thickness on the circuit board, and
The circuit mounting structure according to claim 1, wherein the metal core and the outer peripheral side surface of the conductor pattern are joined by solder or in a cylindrical shape. −】−
JP58128959A 1983-07-15 1983-07-15 Circuit mounting structure Pending JPS6021534A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58128959A JPS6021534A (en) 1983-07-15 1983-07-15 Circuit mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58128959A JPS6021534A (en) 1983-07-15 1983-07-15 Circuit mounting structure

Publications (1)

Publication Number Publication Date
JPS6021534A true JPS6021534A (en) 1985-02-02

Family

ID=14997639

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58128959A Pending JPS6021534A (en) 1983-07-15 1983-07-15 Circuit mounting structure

Country Status (1)

Country Link
JP (1) JPS6021534A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0489045A (en) * 1990-07-30 1992-03-23 Agency Of Ind Science & Technol Sterilizing/cleaning method for intra-body insertion medical apparatus
JPH0766242A (en) * 1993-08-20 1995-03-10 Internatl Business Mach Corp <Ibm> Electronic element assembly, and reprocessing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5023977A (en) * 1973-07-04 1975-03-14
JPS5660025A (en) * 1979-10-19 1981-05-23 Sharp Corp Bonding method for semiconductor element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5023977A (en) * 1973-07-04 1975-03-14
JPS5660025A (en) * 1979-10-19 1981-05-23 Sharp Corp Bonding method for semiconductor element

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0489045A (en) * 1990-07-30 1992-03-23 Agency Of Ind Science & Technol Sterilizing/cleaning method for intra-body insertion medical apparatus
JPH064077B2 (en) * 1990-07-30 1994-01-19 工業技術院長 Method for sterilizing and cleaning medical instruments inserted into the body
JPH0766242A (en) * 1993-08-20 1995-03-10 Internatl Business Mach Corp <Ibm> Electronic element assembly, and reprocessing method thereof

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