JPH11288954A - Junction structure and method of semiconductor element and semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the thermal effects of solder balls due to heated thermal stress of a semiconductor element of circuit substrate on a film substrate which is loaded with the semiconductor element. SOLUTION: In a semiconductor element fixed circuit substrate on a substrate with a wiring part, when a junction structure using solder balls is adopted, a through-hole is made in the substrate to provide the wiring part (electrical connecting part) on the substrate on the stopping up position of the through-hole for connecting the wiring part (electrical connecting part) to the semiconductor element 6, so that a buffer member of thermal stress is arranged between the wiring part (electrical connecting pat) and the semiconductor element 6 so as to absorb the thermal stress as between the substrate and the semiconductor element 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bonding structure of a semiconductor element fixed on a substrate with a resin material or the like.

In particular, a semiconductor element is resin-sealed on a substrate,
In a bonding structure in which a wiring portion (electric connection portion) on a substrate is bonded and connected, a thermal stress caused by heat generated when the semiconductor element and the substrate and the substrate are soldered to another substrate by energization of an electric / electronic circuit. The present invention relates to a technique for solving the problem of solder joints caused by the above.

[0003]

2. Description of the Related Art An integrated circuit in which high-density elements such as ICs and LSIs are integrated has a structure in which a semiconductor element is bonded to a wiring portion on a substrate and the whole is sealed with a resin material.

A circuit board including these semiconductor elements is used as a semiconductor package as a BGA (Ball Grid Array),
It is called by a name such as FP (quad Flat Package).

[0005] USP is a precedent for the BGA system.
3,333,393 and the like.

In the BGA, a semiconductor element (IC chip) is mounted on one surface of a substrate, and a wiring portion provided on the surface of the mounted substrate is connected to an electrode portion of the semiconductor device by wire bonding. The element and the wire are sealed with a resin material, and a solder ball is melted in a wiring portion provided on the other surface side of the substrate to form a wiring portion or an electrode portion with the second substrate. .

US Pat. No. 5,592,025 has a wiring pattern on one side of a film, mounts a semiconductor element thereon, connects the semiconductor element to the wiring pattern on the film by wire bonding, and connects the wiring pattern from the other side of the film. There is proposed a configuration in which a hole is formed so as to expose the wiring pattern, and a solder ball is placed on the exposed wiring pattern portion as an electrode portion to form a joint with the second substrate.

[0008]

In the above-described conventional circuit structure of a semiconductor device, the strength of the connection portion is reduced due to the reduction in the area of the electrode portion for connecting the solder ball due to the demand for improvement of the mounting density. Causes a decrease in the reliability of mechanical-mechanical bonding.

Further, when the substrate on which the semiconductor element is mounted is a thin film substrate, the difference due to the difference in the thermal expansion coefficient due to the difference in the material of the semiconductor element and the film substrate as the heat source (for example, the heat of silicon of the IC chip). Expansion coefficient α = 3P
Thermal expansion coefficient of FR substrate α = 13 to 17P
Pm), the distance between the film substrate and the semiconductor element becomes extremely short, and a thermal stress is generated due to a temperature difference between the two.

[0010] The generation of the thermal stress acts on the joint portion of the solder ball in the above-mentioned semiconductor mounting of the BGA system, causing cracks and cracks in the solder ball due to thermal fatigue.
This reduces the reliability of the electromechanical bonding.

[0011]

According to the present invention, there is provided a circuit board having a semiconductor element fixed on a board provided with a wiring portion, wherein the bonding structure is adopted by using the above-mentioned solder balls. Forming a through hole, providing the wiring portion (electric connection portion) on the substrate at a position closing the through hole, connecting the wiring portion (electric connection portion) to a semiconductor element, and forming the wiring portion (electric connection portion); The present invention has been made to solve the above problem by proposing a bonding structure of a semiconductor element, wherein a member for buffering thermal stress is arranged between the semiconductor element and the semiconductor element so as to absorb the thermal stress between the substrate and the semiconductor element. Work out a solution.

Further, in the BGA type mounting form, a through hole is formed in the substrate, a wiring portion (electric connection portion) is provided on one surface side of the substrate, and an insulating member is provided on an upper surface of the wiring portion (electric connection portion). To expose a part of the wiring portion (electrical connection portion), bond the semiconductor element to the exposed wiring portion (electrical connection portion), and buffer thermal stress between the insulating member and the semiconductor element. A joint structure of a semiconductor element characterized by disposing members is proposed.

Further, as the above-mentioned embodiment, a bonding structure of a semiconductor element according to claim 1 or 2, wherein a material having a thermal expansion coefficient in a range of 3 to 20 ppm is selected for the buffer member.

Furthermore, an embodiment is proposed in which the cushioning member has a multilayer structure.

Furthermore, as another embodiment, the above-mentioned problem is solved by proposing a bonding structure of a semiconductor element, wherein the cross-sectional structure of the buffer member is formed in a substantially comb shape.

One aspect of the present invention is a manufacturing process of a method of bonding a circuit board in which a semiconductor element is fixed on a board, wherein: a) a step of forming a through-hole in the first board; Providing a wiring portion (electric connection portion) on the through hole on one surface side of the substrate; c) coating an insulating film on the wiring portion; and d) providing a thermal stress buffer member on the insulating film. E) placing a semiconductor element on the buffer member and electrically connecting the wiring section (electric connection section); and f) sealing the semiconductor element on the substrate with a resin material. And g) including a step of forming a bonding portion with the second substrate by a solder ball on the other surface side of the through hole of the substrate, to propose a bonding structure of a semiconductor element which can solve the above problem. .

Still another aspect of the present invention is a semiconductor package in which a semiconductor element is fixed on a substrate having a wiring portion (electric connection portion), wherein a through hole is formed in the first substrate, and the through hole is formed. The wiring portion (electric connection portion) is provided on one surface side of the first substrate at a closing position, and the wiring portion (electric connection portion) is connected to a semiconductor element, and the wiring portion (electric connection portion) and the semiconductor element are connected. A member for buffering thermal stress is disposed between, the semiconductor element is resin-sealed on the first substrate, and a connection portion with a second substrate by a solder ball is provided on the other surface side of the first substrate,
A semiconductor package is provided, wherein an electrical connection between the electrode portion of the second substrate and the semiconductor element is achieved via the solder ball.

[0018] It is proposed that the cushioning member of the semiconductor package is made of a material having a coefficient of thermal expansion in the range of 3 to 20 ppm.

Further, a mode is proposed in which the buffer member of the semiconductor package has a multilayer structure.

Further, one aspect of the present invention is a semiconductor package in which an electrode portion of a semiconductor device is wire-bonded to an electrical connection portion on a film substrate and the semiconductor device is resin-sealed on the film substrate. A semiconductor package is proposed wherein a material having an intermediate value of thermal expansion coefficient is interposed between the film and the electrical connection portion on the film substrate.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment A first embodiment will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a main part of a junction structure of a semiconductor device to which the present invention is applied.

In FIG. 1, reference numeral 1 denotes a first substrate. In this embodiment, a film made of a resin material in a sheet shape is used.

As a material of the film 1, an electrically insulating resin material such as a polyimide resin, an epoxy resin, a BT resin, and an aramid resin is used in the form of a sheet.

The thickness of the resin material used is 20 to 1
A range of 00 μm is preferable. In this example, a 60 μm polyimide resin material was used.

1a is a through hole formed in the film 1.

Reference numeral 2 denotes a wiring portion (electric connection portion) made of a copper material wired on the film 1.

Reference numeral 4 denotes an insulating film which covers the copper wiring portion 2 on the film.

A part of the wiring section 2 is exposed 2a, 2a at a part of the insulating film at a part to be wire-bonded 8 with an electrode part of the semiconductor element 6 described later.

Numeral 10 is a member provided on the insulating film for the purpose of relieving thermal stress, and is made of a polyimide resin as a material having a thickness of 0.1 to 0.3 mm on the insulating film.

The thermal expansion coefficient of the buffer member polyimide resin is 12 to 15 ppm.

Reference numeral 12 denotes a bonding paste for fixing the semiconductor element 6 on the film 1, and 14 denotes a resin sealing material.

Reference numeral 16 denotes a solder ball.

Next, the manufacturing process of this embodiment will be described.

A polyimide material having a thickness of 0.05 mm is prepared as a sheet material 1 cut into a predetermined circuit area, and a hole 1a having a hole diameter of 0.20 mm is formed at a position where a wiring electrode is to be formed.

Next, a copper foil film is bonded to one side of the film 1 with a polyimide-based adhesive, a resist is applied on the copper foil, and a wiring pattern to be formed is exposed.
After development, etch the copper foil with an etchant,
The resist is peeled off to form a wiring portion (electric connection portion) 2.

Then, an insulating film 4 as a protective resist made of a polyimide resin material is applied on the wiring portion (electric connection portion) 2. At this time, portions 2a, 2a for wire bonding for electrical connection between the wiring portion 2 and the electrode portion of the semiconductor element expose part of the wiring portion.

Next, a thermal stress buffering member 10 is applied on the insulating film 4.

The thickness of the thermal stress buffer member 10 is 0.2 mm
Set to.

Thereafter, in order to perform Au plating on the exposed surfaces of the wiring portions 2a and 2a, the underlying Ni plating is performed to a thickness of about 3 to 8 μm, and then the Au plating is applied to a thickness of 0.1 to 8 μm.
Perform 1-2 μm.

Through the above steps, a manufacturing process of the electric connection portion on the film substrate 1 can be performed.

Thereafter, a bonding paste 12 is applied on the thermal buffer member 10 to a thickness of 10 to 30 μm, the semiconductor element 6 is placed on the paste 2, and the bonding paste is applied at a temperature of about 150 to 200 ° C. Heat and cure.

After the semiconductor element 6 is fixed, the electrical connection portions 2a, 2a of the film substrate and the electrode portions of the semiconductor element are wire-bonded to each other by an Au wire 8, and as shown in FIG. Is sealed with a resin so as to entirely cover the semiconductor element mounting side with a resin material. FIG.

Thereafter, the through-hole 1a of the film substrate 1 is formed.
The adhesive flux was transferred to the back side of the substrate, and the diameter was 0.2 to 0.1 mm.
A 6 mm solder ball is placed on the hole 1a and passes through a solder reflow process.

With the passage of the reflow process, the solder balls are melted, and the melted solder comes into contact with the copper foil electrical connection portion 2 located at a position to close the bottom surface in the hole 1a and alloys with the copper foil. The free end side of the ball has a substantially spherical shape at the tip end side as shown in FIG. 2 due to surface tension in a molten state.

By cooling after passing through the reflow process, the solder ball and the electrical connection portion 2 of the copper foil become integral with each other to form a connection portion 16 with a second circuit board described later. FIG.

The package structure of the film substrate on which the semiconductor element 6 is mounted is completed by the steps shown in FIG.

Next, a method of connecting the first substrate A manufactured in the steps up to FIG. 2 to the second circuit substrate B will be described with reference to FIG.
This will be described with reference to FIG.

In FIG. 3, reference numeral 20 denotes a second circuit board, on which a copper foil portion 22 of a circuit wiring portion is printed.

Reference numeral 24 denotes an insulating protective film.

The wiring portion 22 of the prepared second circuit board is configured so as to correspond to the arrangement position of the solder balls 16 of the first substrate A in FIG.

When the front ends of the solder balls of the first substrate are aligned with the wiring portions 22 of the second substrate B to fix the substrates A and B, and when the solder is reflowed, the substrates A
Is melted on the wiring portion 22 on the substrate B side and fused with the copper foil, and after the reflow, the wiring portion 2 of the first substrate A and the wiring portion 22 of the second substrate B are melted. Are electrically and mechanically connected via the solder ball portion 16,
An electric circuit is constituted by the semiconductor element on the first substrate side and the circuit components (not shown) on the second substrate side.

The solder ball used in this example is Pb-
Binary Sn alloy, Pb-Sn-Ag, Pb-Sn-B
Use a ternary system of i-alloy.

As described above, in this example, the wiring section 2
Circuit board A in which a semiconductor element 6 is fixed on a substrate 1 provided with
, A through hole 2 is formed in the circuit board, and the wiring portion 2 (electric connection portion) is formed on the substrate at a position to close the through hole.
The wiring part 2 (electric connection part) is connected to the semiconductor element 6, and a member 10 for buffering thermal stress is provided between the wiring part (electric connection part) and the semiconductor element. , Solder ball 1 for bonding with another circuit board B
6, the generation of thermal stress due to the difference in the coefficient of thermal expansion between the film material of the substrate and the surrounding materials such as the resin material due to heat generation from the semiconductor element can be slightly suppressed. As a result, the influence of heat on the solder ball portion was avoided, and the reliability of the electrical and mechanical bonding was secured.

Further, according to the present invention, the buffer member has a thermal expansion coefficient of 3 to 20 ppm by adopting the structure as in the above embodiment.
, And a versatile configuration could be obtained.

Further, the present invention provides a method for joining a circuit board having a semiconductor element fixed on the board as the following steps: a) a step of forming a through hole in the first board; Providing a wiring portion (electric connection portion) on the through hole; c) coating an insulating film on the wiring portion (electric connection portion); and d) providing a thermal stress buffer member on the insulation film. E) placing a semiconductor element on the buffer member and electrically connecting the wiring section (electric connection section); and f) sealing the semiconductor element on the substrate with a resin material. And g) a method of forming a bonding portion with the second substrate by a solder ball on the other surface side of the through hole of the substrate. Manufactured successfully.

Further, in the above embodiment, a through hole is formed in the first substrate in the semiconductor package in which the semiconductor element 6 is fixed on the substrate 1 provided with the wiring portion 2 (electric connection portion).
The wiring portion (electric connection portion) is provided on one surface side of the first substrate at a position to close the through hole, and the wiring portion (electric connection portion)
And a semiconductor element, and a member 10 for buffering thermal stress is arranged between the wiring part (electrical connection part) and the semiconductor element, and the semiconductor element is resin-sealed on a first substrate. The semiconductor package shown in FIG. 3 in which a connection portion with a second substrate by a solder ball is provided on the other surface side of the substrate, and an electrical connection between an electrode portion of the second substrate and the semiconductor element is achieved through the solder ball. I got it.

Description of Second Embodiment FIG. 4 is a sectional view of a main part of a semiconductor package according to a second embodiment of the present invention.

In FIG. 4, reference numeral 30 denotes a first substrate. In this embodiment, a film made of a resin material in a sheet shape is used.

As a material of the film 30, an electrically insulating resin material such as a polyimide resin, an epoxy resin, a BT resin, and an aramid resin is used in the form of a sheet.

The thickness of the resin material used is 20 to 1
A range of 00 μm is preferable. In this example, a polyimide resin material of 70 μm was used.

Reference numeral 30a denotes a through hole formed in the film 1.

Reference numeral 32 denotes a wiring portion (electric connection portion) made of a copper material and wired on the film 1.

Reference numeral 34 denotes a copper wiring portion 32 on the film.
An insulating film coated on the top.

A part of the wiring portion 32 is exposed 32a, 32a at a part of the insulating film where a wire bonding 38 is formed with an electrode portion of the semiconductor element 36 described later.

Reference numeral 40 denotes a ceramic member provided on the insulating film for the purpose of relieving thermal stress. Alumina is formed on the insulating film as a material and has a thickness of 0.1 to 0.2 mm.
Is bonded with a bonding paste 42.

The thermal expansion coefficient of the buffer member alumina is 6 to 6.
9 ppm.

Reference numeral 44 denotes a resin sealing material.

Reference numeral 46 denotes a solder ball.

Next, the manufacturing process of this embodiment will be described.

A polyimide material having a thickness of 0.05 mm is prepared as a sheet material 30 cut into a predetermined circuit area, and a hole 30a having a hole diameter of 0.20 mm is formed at a position where a wiring electrode is to be formed.

Next, a copper foil film is bonded to one side of the film 30 with a polyimide-based adhesive, a resist is applied on the copper foil, and a wiring pattern to be formed is exposed and developed. The copper foil is subjected to an etching treatment, the resist is peeled off, and a wiring portion (electric connection portion) 32 is formed.
To form

Then, an insulating film 34 as a protective resist made of a polyimide resin material is applied on the wiring portion (electric connection portion) 32. At this time, portions 32a, 32a for wire bonding for electrical connection between the wiring portion 32 and the electrode portion of the semiconductor element 36 expose part of the wiring portion.

Thereafter, the exposed wiring portions 32a, 32
In order to perform Au plating on the surface of a, Ni plating as a base is performed in a thickness of about 3 to 8 μm, and Au plating is further performed thereon in a thickness of 0.1 to 2 μm.

Through the above steps, the manufacturing process of the electrical connection portion on the film substrate 30 is completed.

Thereafter, a bonding paste 42 is applied on the thermal buffer member 40 to a thickness of 10 to 30 μm.
The semiconductor element 36 is placed on the paste 42, and the bonding paste is heated and cured at a temperature of about 150 to 200 ° C.

After the semiconductor element 36 is fixed, the electrical connection portions 32a, 32a of the film substrate and the electrode part of the semiconductor element are wire-bonded to each other by an Au wire 38, and then, as shown in FIG. Is sealed with a resin so as to entirely cover the semiconductor element mounting side with a resin material.

Thereafter, the through holes 3 in the film substrate 30 are formed.
Transfer the adhesive flux to the back side of Oa
A 0.6 mm solder ball is placed on the hole 30a and passes through a solder reflow process.

With the passage of the reflow process, the solder balls are melted, and the melted solder comes into contact with the copper foil electrical connection portion 32 located at a position closing the bottom surface in the hole 30a to be alloyed with the copper foil. The free end side of the ball has a substantially spherical shape at the free end side as shown in FIG. 4 due to surface tension in a molten state.

The circuit structure manufactured by the above steps is prepared by preparing the second circuit board B of the first embodiment shown in FIG.
As described above, the wiring portion of the second circuit board B is aligned with the solder ball 46 of the present example in FIG. 4 and the reflow soldering process is performed, whereby each of the first board and the second circuit board in FIG. By electrically connecting the circuit elements, a semiconductor circuit structure as a whole can be obtained.

Thereafter, in order to perform Au plating on the exposed surfaces of the wiring portions 2a and 2a, the underlying Ni plating is performed to a thickness of about 3 to 8 μm, and the Au plating is further applied thereon to a thickness of 0.1 μm.
２2 μm.

Through the above steps, a manufacturing process of the electrical connection portion on the film substrate 1 can be performed.

Thereafter, a bonding paste 12 is applied on the thermal buffer member 10 to a thickness of 10 to 30 μm.
The semiconductor element 6 is placed on the paste 2 and the bonding paste is heated and cured at a temperature of about 150 to 200 ° C.

After the semiconductor element 6 is fixed, the electrical connection portions 2a, 2a of the film substrate and the electrode portions of the semiconductor element are wire-bonded to each other by an Au wire 8, and as shown in FIG. Is sealed with a resin so as to entirely cover the semiconductor element mounting side with a resin material. FIG.

Thereafter, the through-hole 1a of the film substrate 1 is formed.
The adhesive flux was transferred to the back side of the substrate, and the diameter was 0.2 to 0.1 mm.
A 6 mm solder ball is placed on the hole 1a and passes through a solder reflow process.

As the solder ball passes through the reflow process, the solder ball is melted, and the melted solder contacts the copper foil electrical connection portion 2 located at a position closing the bottom surface in the hole 1a to alloy with the copper foil. The free end side of the ball has a substantially spherical shape at the tip end side as shown in FIG. 2 due to surface tension in a molten state.

Description of Third Embodiment In this embodiment, the thermal stress buffering member interposed between the semiconductor element and the film substrate has a multi-layer structure, and the flatness tolerance of the substrate on which the semiconductor element is mounted is allowed. This is an embodiment aiming at reducing the influence of the thermal stress on the solder ball portion by allowing the substrate to be deformed by the thermal stress by increasing the stress.

Hereinafter, description will be made with reference to FIG.

In FIG. 5, reference numeral 50 denotes a first substrate. In this embodiment, a film made of a resin material in a sheet shape is used.

As a material of the film 50, an electrically insulating resin material such as a polyimide resin, an epoxy resin, a BT resin, and an aramid resin is used in the form of a sheet.

The thickness of the resin material used is 20 to 1
A range of 00 μm is preferable. In this example, a polyimide resin material of 70 μm was used.

Reference numeral 50a denotes a through hole formed in the film 1.

Reference numeral 52 denotes a wiring portion (electric connection portion) made of a copper material and wired on the film 1.

Reference numeral 54 denotes a copper wiring portion 52 on the film.
An insulating film coated on the top.

A part of the wiring portion 52 is exposed 52a, 52a to a portion of the insulating film where a wire bonding 58 is formed with an electrode portion of a semiconductor element 56 described later.

Reference numeral 60 denotes a multilayer member provided on the insulating film for the purpose of relaxing thermal stress. The first member 60A is made of alumina having a thickness of 0.1 mm or less, and the second member 60B is made of a thickness of 0.1 mm or less. A polyimide film of 0.1 mm or more was used.

The thermal expansion coefficient of the buffer member alumina 60A is 6 to 9 ppm, and the thermal expansion coefficient of the polyimide film 60B is 13 to 18 ppm.

When a multi-layer structure is employed as the cushioning member 60 of this embodiment, the relationship between the Young's modulus of the material forming each layer and the thickness of the layer is such that the thickness of the member having a high Young's modulus is the thickness of the member having a low Young's modulus. It is set to be smaller than the thickness of the layer.

With this configuration, the rigidity of the entire composite material is reduced, and the tolerance of deformation by heat is increased.

Reference numeral 64 denotes a resin sealing material.

Reference numeral 66 denotes a solder ball.

Next, the manufacturing process of this example will be described.

A polyimide material having a thickness of 0.05 mm is prepared as a sheet material 50 cut into a predetermined circuit area, and a hole 50a having a hole diameter of 0.20 mm is formed at a position where a wiring electrode is to be formed.

Next, a copper foil film is adhered to one side of the film 50 with a polyimide-based adhesive, a resist is applied on the copper foil, a wiring pattern to be formed is exposed and developed, and then an etching solution is used. The copper foil is subjected to an etching treatment, the resist is peeled off, and a wiring portion (electric connection portion) 52 is formed.
To form

Then, an insulating film 54 as a protective resist made of a polyimide resin material is applied on the wiring portion (electric connection portion) 52. At this time, portions 52a, 52a for wire bonding for electrical connection between the wiring portion 52 and the electrode portion of the semiconductor element 56 expose a part of the wiring portion.

Thereafter, the exposed wiring portions 52a, 52
In order to perform Au plating on the surface of a, Ni plating as a base is performed in a thickness of about 3 to 8 μm, and Au plating is further performed thereon in a thickness of 0.1 to 2 μm.

Through the above steps, a process for manufacturing the electrical connection portion on the film substrate 50 can be performed.

Thereafter, a bonding paste 62 is applied on the thermal buffer member 60 to a thickness of 10 to 30 μm, a semiconductor element 56 is mounted on the paste 62, and the bonding paste is applied at a temperature of about 150 to 200 ° C. Heat and cure.

After the semiconductor element 56 is fixed, the electrical connection portions 52a, 52a of the film substrate and the electrode portions of the semiconductor element are wire-bonded to each other by an Au wire 58, and then, as shown in FIG. Is sealed with a resin so as to entirely cover the semiconductor element mounting side with a resin material.

Thereafter, the through holes 5 of the film substrate 50 are formed.
Transfer the adhesive flux to the back side of Oa
A 0.6 mm solder ball is placed on the hole 50a and passes through a solder reflow process.

As the solder ball passes through the reflow process, the solder ball is melted, and the melted solder contacts the copper foil electrical connection portion 52 located at a position closing the bottom surface in the hole 50a to alloy with the copper foil. The free end side of the ball has a substantially spherical shape at the free end side due to surface tension in a molten state as shown in FIG.

Description of the Fourth Embodiment In this embodiment, the cushioning member inserted between the semiconductor element and the film substrate on which the element is mounted has a flexible shape so that the semiconductor element and the film substrate This is an invention that suppresses the influence of thermal stress due to the difference in the coefficient of thermal expansion from the above.

Hereinafter, description will be made with reference to FIG.

In FIG. 6, reference numeral 70 denotes a first substrate. In this embodiment, a film made of a resin material in a sheet shape is used.

As a material of the film 70, an electrically insulating resin material such as a polyimide resin, an epoxy resin, a BT resin, and an aramid resin is used in the form of a sheet.

The thickness of the resin material used is 20 to 1
A range of 00 μm is preferable, and in this example, a polyimide resin material of 70 μm was used.

Reference numeral 70a denotes a through hole formed in the film 70.

Reference numeral 72 denotes a wiring portion (electric connection portion) made of a copper material and wired on the film 1.

Reference numeral 74 denotes a copper wiring portion 72 on the film.
An insulating film coated on the top.

A part of the wiring portion 72 is exposed 72a, 72a at a portion of the insulating film where a wire bonding 78 is formed with an electrode portion of the semiconductor element 76 described later.

Numeral 80 is a cushioning member made of polyimide resin provided on the insulating film for the purpose of relaxing thermal stress. The member 80 has irregularities 80a formed on the surface on the semiconductor element side.

The thickness of the polyimide member 80 itself is 0.1 to
The thickness was 0.2 mm, and the depth of the uneven portion was １ ／ of the thickness.

Further, the duty ratio of the unevenness was set to 50%.

Numeral 84 is a resin sealing material.

Reference numeral 86 denotes a solder ball.

Next, the manufacturing process of this example will be described.

A polyimide material having a thickness of 0.05 mm is prepared as a sheet material 70 cut into a predetermined circuit area, and a hole 70a having a hole diameter of 0.20 mm is formed at a position where a wiring electrode is to be formed.

Next, a copper foil film is adhered to one side of the film 70 with a polyimide-based adhesive, a resist is applied on the copper foil, a wiring pattern to be formed is exposed and developed, and then an etching solution is used. The copper foil is subjected to an etching treatment, the resist is peeled off, and a wiring portion (electric connection portion) 72 is formed.
To form

Then, an insulating film 74 as a protective resist made of a polyimide resin material is applied on the wiring portion (electric connection portion) 72. At this time, portions 72a, 72a for wire bonding for electrical connection between the wiring portion 72 and the electrode portion of the semiconductor element 76 expose a part of the wiring portion.

Thereafter, the exposed wiring portions 72a, 72
In order to perform Au plating on the surface of a, Ni plating as a base is performed in a thickness of about 3 to 8 μm, and Au plating is further performed thereon in a thickness of 0.1 to 2 μm.

Through the above steps, a manufacturing process of the electric connection portion on the film substrate 70 can be performed.

Thereafter, a bonding paste 82 is applied on the heat buffer member 80, the semiconductor element 56 is placed on the paste 62, and the bonding paste is applied for about 15 minutes.
Heat and cure at a temperature of 0 to 200 ° C.

After the semiconductor element 76 is fixed, the electrical connection portions 72a, 72a of the film substrate and the electrode portions of the semiconductor element are wire-bonded to each other by an Au wire 78, and then, as shown in FIG. Is sealed with a resin so as to entirely cover the semiconductor element mounting side with a resin material.

Thereafter, the through holes 7 of the film substrate 70 are formed.
Transfer the adhesive flux to the back side of Oa
A 0.6 mm solder ball is placed on the hole 70a and passes through a solder reflow process.

With the passage of the reflow process, the solder balls are melted, and the melted solder comes into contact with the copper foil electrical connection portion 72 located at a position closing the bottom surface in the hole 70a to be alloyed with the copper foil. The free end side of the ball was in a molten state, and a circuit configuration of a semiconductor element having a substantially spherical tip end as shown in FIG. 6 was obtained by surface tension.

Description of Modification FIG. 7 shows a modification of the embodiment of the present invention.

In this embodiment, the buffer member interposed between the semiconductor element and the film substrate on which the semiconductor element is mounted has a multi-layer structure, and a part of the multi-layer has a concave and convex shape to form a thermal stress. Thus, the ease of the deformation caused by the deformation is improved.

Hereinafter, description will be made with reference to FIG.

In FIG. 7, reference numeral 90 denotes a first substrate. In this embodiment, a film made of a resin material in a sheet shape is used.

As the material of the film 90, an electrically insulating resin material such as a polyimide resin, an epoxy resin, a BT resin, and an aramid resin is used in the form of a sheet.

The thickness of the resin material used is 20 to 1
A range of 00 μm is preferable, and in this example, a polyimide resin material of 70 μm was used.

Reference numeral 90a denotes a through hole formed in the film 90.

Reference numeral 92 denotes a wiring portion (electric connection portion) made of a copper material and wired on the film 1.

Reference numeral 94 denotes a copper wiring portion 92 on the film.
An insulating film coated on the top.

A part of the wiring part 92 is exposed 92a, 92a at a part of the insulating film where a wire bonding 98 is formed with an electrode part of a semiconductor element 96 described later.

Reference numeral 100 denotes a buffer member having a multi-layer structure provided on the insulating film 94 for the purpose of relaxing thermal stress. The buffer member 100 is a first layer 100A made of a ceramic material.
And a second layer 100B made of a resin material, and alumina is selected as the ceramic material.
An irregularity 100a is formed on one side surface of 0A, and a polyimide resin material is embedded in the concave part of the irregularity.

The overall thickness of the cushioning member 100 is 0.1 to
0.2 mm, and the thickness of the alumina portion is 0.1 to
The depth of the unevenness was set to 0.15 mm and the depth of the unevenness was set to 0.05 to 0.10 mm.

Reference numeral 102 denotes a resin sealing material.

Reference numeral 104 denotes a solder ball.

Next, the manufacturing process of this example will be described.

A polyimide material having a thickness of 0.05 mm is prepared as a sheet material 90 cut into a predetermined circuit area, and a hole 90a having a hole diameter of 0.20 mm is formed at a position where a wiring electrode is to be formed.

Next, a copper foil film is adhered to one side of the film 90 with a polyimide-based adhesive, a resist is applied on the copper foil, a wiring pattern to be formed is exposed and developed, and then an etching solution is used. The copper foil is subjected to an etching treatment, the resist is peeled off, and a wiring portion (electric connection portion) 92
To form

Then, an insulating film 94 as a protective resist made of a polyimide resin material is applied on the wiring portion (electric connection portion) 92. At this time, portions 92a, 92a for wire bonding for electrical connection between the wiring portion 92 and the electrode portion of the semiconductor element 96 expose a part of the wiring portion.

Thereafter, the exposed wiring portions 92a, 92
In order to perform Au plating on the surface of a, Ni plating as a base is performed in a thickness of about 3 to 8 μm, and Au plating is further performed thereon in a thickness of 0.1 to 2 μm.

Through the above steps, the manufacturing process of the electrical connection portion on the film substrate 90 is completed.

After that, a bonding paste 102 is applied on the thermal stress buffering member 100,
The semiconductor element 96 is mounted on the substrate 2, and the bonding paste is heated and cured at a temperature of about 150 to 200 ° C.

After the semiconductor element 96 is fixed, the electrical connection portions 92a, 92a of the film substrate and the electrode portions of the semiconductor element are wire-bonded to each other by an Au wire 98, and then, as shown in FIG. Is sealed with a resin so as to entirely cover the semiconductor element mounting side with a resin material.

Thereafter, the through holes 9 in the film substrate 90 are formed.
Transfer the adhesive flux to the back side of Oa
A 0.6 mm solder ball is placed on the hole 90a and passes through a solder reflow process.

With the passage of the reflow process, the solder balls are melted, and the melted solder comes into contact with the copper foil electrical connection portion 92 located at a position closing the bottom surface in the hole 90a to be alloyed with the copper foil. As shown in FIG. 7, the free end side of the ball was in a molten state, and a circuit configuration of a semiconductor element having a substantially spherical end was obtained by surface tension.

[0160]

As described above, the present invention relates to a case where a bonding structure is adopted by using the above-mentioned solder balls in a circuit board in which a semiconductor element is fixed on a board having a wiring portion.
Forming a through hole in the circuit board, providing the wiring portion (electric connection portion) on the substrate at a position closing the through hole, connecting the wiring portion (electric connection portion) to a semiconductor element, To provide a connection structure for a semiconductor element, wherein a member for buffering thermal stress is arranged between the (electric connection part) and the semiconductor element to absorb the thermal stress between the substrate and the semiconductor element. As a result, the reliability of the electrical and mechanical joining of the solder ball portion could be improved.

In the BGA type mounting form, a through hole is formed in the substrate, a wiring portion (electric connection portion) is provided on one surface side of the substrate, and an insulating member is provided on the upper surface of the wiring portion (electric connection portion). To expose a part of the wiring portion (electric connection portion), bond the semiconductor element to the exposed wiring portion (electric connection portion), and buffer thermal stress between the insulating member and the semiconductor element. By arranging the members, it was possible to obtain a semiconductor circuit component in which the influence of thermal stress could be avoided.

[Brief description of the drawings]

FIG. 1 is an explanatory view of a manufacturing process according to a first embodiment of the present invention, and is a cross-sectional view of a main part of a circuit structure in which a semiconductor element is mounted on a film substrate.

FIG. 2 is an explanatory view of a manufacturing process of the first embodiment of the present invention, and is a cross-sectional view of a main part in which solder balls are connected to the film substrate of FIG.

FIG. 3 is an explanatory view of a manufacturing process according to the first embodiment of the present invention, and is an explanatory view of a bonding state between a first substrate and a second substrate.

FIG. 4 is an explanatory diagram of the second embodiment.

FIG. 5 is an explanatory view of a third embodiment.

FIG. 6 is an explanatory view of a fourth embodiment.

FIG. 7 is an explanatory view of a modification.

[Explanation of symbols]

1, 30, 50, 70, 90 First substrate (film substrate) 1a, 30a, 50a, 70a, 90a Through hole in first substrate 10, 40, 60, 80, 100 Buffer member 6, 36, 56, 76 , 96 Semiconductor device 16, 46, 66, 86, 104 Solder ball 20 Second substrate

Claims (10)

[Claims] 1. A circuit board in which a semiconductor element is fixed on a board having a wiring section, wherein a through hole is formed in the circuit board, and the wiring section is provided on the board at a position to close the through hole. A connection structure for a semiconductor element, wherein a wiring part and a semiconductor element are connected, and a member for buffering thermal stress is arranged between the wiring part and the semiconductor element. 2. A through hole is formed in a substrate, a wiring portion is provided on one surface side of the substrate, an insulating member is covered on an upper surface of the wiring portion, a part of the wiring is exposed, and a semiconductor element is provided on the exposed wiring portion. Characterized in that a member for buffering thermal stress is disposed between the insulating member and the semiconductor element. 3. The cushioning member has a coefficient of thermal expansion of 3 to 20.
3. The junction structure according to claim 1, wherein a material in the range of PPm is selected. 4. The structure according to claim 1, wherein the buffer member has a multilayer structure. 5. The semiconductor element bonding structure according to claim 1, wherein said buffer member has a substantially comb-shaped cross-sectional structure. 6. A method for bonding a circuit board having a semiconductor element fixed on a substrate includes the following steps: a) forming a through hole in a first substrate; and b) forming a through hole in the first substrate. Providing a wiring portion on the through hole on one surface side; c) coating an insulating film on the wiring portion; d) coating a thermal stress buffer member on the insulating film; e). Placing a semiconductor element on the buffer member and electrically connecting the semiconductor element to the wiring portion; f) sealing the semiconductor element on the substrate with a resin material; and g) forming a through hole in the substrate. A step of forming a joint portion with the second substrate by a solder ball on the other surface side. 7. In a semiconductor package in which a semiconductor element is fixed on a substrate provided with a wiring portion (electric connection portion), a through hole is formed in the first substrate, and the first substrate is located at a position to close the through hole. Providing the wiring portion on one surface side, connecting the wiring portion to the semiconductor element, disposing a member for buffering thermal stress between the wiring portion and the semiconductor element, and placing the semiconductor element on a first substrate by resin. Sealing, providing a connection portion with the second substrate by a solder ball on the other surface side of the first substrate, to achieve an electrical connection between the electrode portion of the second substrate and the semiconductor element via the solder ball. Semiconductor package characterized by the following. 8. The cushioning member has a coefficient of thermal expansion of 3 to 20.
8. The semiconductor package according to claim 7, wherein a material in a range of ppm is selected. 9. The semiconductor package according to claim 8, wherein said buffer member has a multilayer structure. 10. A semiconductor package in which an electrode portion of a semiconductor device is wire-bonded to an electrical connection portion on a film substrate and the semiconductor device is resin-sealed on the film substrate. A semiconductor package, wherein a material having an intermediate value of thermal expansion coefficient is interposed between the semiconductor package and a connection portion.