JP2001156095A - Electrode, semiconductor device and method for manufacture thereof - Google Patents

Electrode, semiconductor device and method for manufacture thereof

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Publication number
JP2001156095A
JP2001156095A JP33679499A JP33679499A JP2001156095A JP 2001156095 A JP2001156095 A JP 2001156095A JP 33679499 A JP33679499 A JP 33679499A JP 33679499 A JP33679499 A JP 33679499A JP 2001156095 A JP2001156095 A JP 2001156095A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor chip
memory alloy
shape memory
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33679499A
Other languages
Japanese (ja)
Inventor
Naoki Tanaka
直樹 田中
Takashi Saito
隆 斎藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP33679499A priority Critical patent/JP2001156095A/en
Publication of JP2001156095A publication Critical patent/JP2001156095A/en
Pending legal-status Critical Current

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an electrode capable of manufacturing it with a simple process, reducing a manufacturing cost, improving a yield, and enhancing reliabil ity in connection by relaxing distortion by stress caused in difference of coeffi cient of thermal expansion between a semiconductor chip and a mounting sub strate without sealing with resin therebetween, and to provide a semiconductor device equipped with the electrode and its manufacturing method. SOLUTION: The electrode 16 is formed in connection to an electrode circuit pattern on a semiconductor chip 10 on which the electrode circuit pattern is formed. The electrode 16 is also constituted of a shape memory alloy with at least a portion of its phase shift temperature existing between a martensite phase and an austenite phase, higher than an ambient temperature, and preferably specified substantially not lower than the maximal operating temperature of the semiconductor chip. Or, the semiconductor device 1a should be equipped with the electrode 16. The electrode 16 is formed on the semiconductor chip 10 by means of transcription or wire bonding of a ball bump using the shape memory alloy.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は電極、半導体装置お
よびその製造方法に関し、特に、小型化および高密度化
された半導体装置を実装するために前記半導体装置に備
えられる電極と、当該電極を備えた半導体装置およびそ
の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode, a semiconductor device, and a method of manufacturing the same, and more particularly, to an electrode provided in the semiconductor device for mounting a miniaturized and high-density semiconductor device, and an electrode provided with the electrode. And a method of manufacturing the same.

【０００２】[0002]

【従来の技術】デジタルビデオカメラ、デジタル携帯電
話、あるいはノートパソコンなど、携帯用電子機器の小
型化、薄型化、軽量化に対する要求は強くなる一方であ
り、これに応えるために近年のＶＬＳＩなどの半導体装
置においては３年で７割の縮小化を実現してきた一方
で、実装基板上の部品実装密度をいかに向上させるかが
重要な課題として研究および開発がなされてきた。2. Description of the Related Art The demand for smaller, thinner, and lighter portable electronic devices, such as digital video cameras, digital mobile phones, and notebook computers, is increasing. While semiconductor devices have been reduced by 70% in three years, research and development have been made as an important issue how to increase the component mounting density on a mounting board.

【０００３】従来、半導体装置のパッケージ形態として
は、ＤＩＰ（Dual Inline Package）あるいはＰＧＡ（P
in Grid Array）などのプリント基板に設けたスルーホ
ールにリード線を挿入して実装するリード挿入型（ＴＨ
Ｄ：Through Hall Mount Device ）や、ＱＦＰ（Quad F
lat Package ）あるいはＴＣＰ（Tape Carrier Packag
e）などのリード線を基板の表面にハンダ付けして実装
する表面実装型（ＳＭＤ：Surface Mount Device）が用
いられてきた。小型化および高密度化を進めるために、
パッケージサイズを半導体チップの大きさに限りなく近
づけたチップサイズパッケージ（ＣＳＰ：Chip Size Pa
ckage）とも呼ばれる）と呼ばれるパッケージ形態へ移
行してきている。さらなる小型化および高密度化のため
に、パッド電極に接続するように突起電極（バンプ）を
設けた半導体チップを、ベアチップ状態で、半導体チッ
プのバンプ形成面側から実装基板に向けて実装する方法
（フリップチップ実装）が注目を集めており、現在まで
に活発に研究がなされ、多くの提案が示されている。上
記の突起電極としては、はんだなどのボールバンプや金
などのスタッドバンプが用いられ、熱溶着あるいは異方
性導電膜などを用いた圧着などにより接続されている。Conventionally, as a package form of a semiconductor device, a DIP (Dual Inline Package) or PGA (P
Lead insertion type (TH) that inserts lead wires into through holes provided in a printed circuit board such as an in Grid Array
D: Through Hall Mount Device), QFP (Quad F
lat Package) or TCP (Tape Carrier Packag)
e) A surface mount device (SMD) in which lead wires such as those described above are soldered and mounted on the surface of a substrate has been used. To promote miniaturization and high density,
Chip size package (CSP: Chip Size Pa) with package size as close as possible to the size of a semiconductor chip
ckage)). A method of mounting a semiconductor chip provided with protruding electrodes (bumps) to be connected to pad electrodes in a bare chip state from a bump forming surface side of the semiconductor chip to a mounting substrate for further miniaturization and higher density. (Flip-chip mounting) has been attracting attention, and active research has been conducted to date, and many proposals have been presented. As the protruding electrodes, ball bumps such as solder and stud bumps such as gold are used, and are connected by heat welding or pressure bonding using an anisotropic conductive film or the like.

【０００４】上記の従来のベアチップ状態で実装する半
導体装置およびその実装形態について図面を参照して説
明する。図９（ａ）は上記の半導体装置の概略断面図で
あり、図９（ｂ）は図９（ａ）中のＡ部の拡大断面図で
ある。半導体チップ１０のアルミニウムなどからなるパ
ッド電極１１上に、例えば銅やアルミニウムなどからな
る配線層１２が形成されており、パッド電極１１および
配線層１２上に、例えば窒化シリコン膜からなる保護膜
１３が被覆して形成されている。バンプ形成領域におい
て、保護膜１３に対して配線層１２を露出させる開口部
が形成されている。この開口部において、例えばクロ
ム、銅、金の積層膜などからなるＢＬＭ（Ball Limitti
ng Metal）膜と呼ばれる導電膜１４が形成されており、
その上層に、例えばはんだボールなどからなるバンプ１
６が形成されている。以上のようにＣＳＰ形態の半導体
装置１００ａが構成されている。A conventional semiconductor device mounted in a bare chip state and a mounting form thereof will be described with reference to the drawings. FIG. 9A is a schematic sectional view of the above semiconductor device, and FIG. 9B is an enlarged sectional view of a portion A in FIG. 9A. A wiring layer 12 made of, for example, copper or aluminum is formed on a pad electrode 11 made of aluminum or the like of the semiconductor chip 10, and a protective film 13 made of, for example, a silicon nitride film is formed on the pad electrode 11 and the wiring layer 12. It is formed by coating. An opening for exposing the wiring layer 12 to the protective film 13 is formed in the bump formation region. In this opening, for example, a BLM (Ball Limitti) made of a laminated film of chromium, copper, gold, etc.
ng Metal) film is formed.
A bump 1 made of, for example, a solder ball or the like
6 are formed. The CSP type semiconductor device 100a is configured as described above.

【０００５】次に、上記の半導体装置１００ａを実装基
板に実装した電子回路装置について説明する。図１０は
上記の電子回路装置の断面図である。実装基板２は、例
えばガラスエポキシ系材料よりなる基板２０の上面にお
いて、実装する半導体装置１００ａのバンプ１６の形成
位置に対応する位置に形成された銅などからなるランド
（電極）２１と、ランド２１に接続して、基板２０の表
面上、裏面上および基板２０内部などに形成されている
プリント配線部（不図示）を有している。ランド２１部
分を除く基板２０表面はソルダーレジスト（不図示）に
より被覆されている。Next, an electronic circuit device in which the semiconductor device 100a is mounted on a mounting board will be described. FIG. 10 is a sectional view of the electronic circuit device. The mounting substrate 2 includes a land (electrode) 21 made of copper or the like formed at a position corresponding to the formation position of the bump 16 of the semiconductor device 100 a to be mounted on the upper surface of the substrate 20 made of, for example, a glass epoxy material, and a land 21. And a printed wiring portion (not shown) formed on the front surface, the rear surface, the inside of the substrate 20, and the like of the substrate 20. The surface of the substrate 20 excluding the lands 21 is covered with a solder resist (not shown).

【０００６】上記のＣＳＰ形態の半導体装置１００ａは
バンプ１６とランド２１を対応させて実装基板２上にマ
ウントされており、接合用のはんだ２２あるいはバンプ
１６がはんだボールからなる場合はバンプ１６自身によ
り、ランド２１と機械的、電気的に接続されている。The CSP type semiconductor device 100a is mounted on the mounting substrate 2 with the bumps 16 and the lands 21 corresponding to each other. When the bonding solder 22 or the bumps 16 are formed of solder balls, the bumps 16 themselves are used. , And the land 21 are mechanically and electrically connected.

【０００７】上記の電子回路装置は、図４（ａ）に示す
ように、実装工程において接合用のはんだ２２あるいは
バンプ１６がはんだボールからなる場合はバンプ１６自
身を溶融するために２００〜２５０℃に加温されるが、
シリコンの熱膨張率が３．４ｐｐｍ／℃であるのに対し
て、一般的に広く用いられているガラスエポキシ系の実
装基板の熱膨張率は約１５ｐｐｍ／℃と大きいことか
ら、図４（ｂ）に示すように、常温（〜２０℃）程度に
まで温度が下がると１８０℃前後で固化したバンプ１６
は大きな応力を受けることになる。さらに、図４（ｃ）
に示すように、半導体チップ１０は通電される度に加熱
されて１００℃以上となるため、バンプ１６はチップの
オン／オフにより生じる温度差によって繰り返し応力を
受けることになる。上記の応力歪により、図１１に示す
ように、半導体チップ１０の電極１０ａと実装基板の基
板２０に形成されたランド２１とを接続するはんだボー
ルからなるバンプ１６の根本にクラックＣが発生し、接
続不良を起こしやすいという問題がある。As shown in FIG. 4A, when the bonding solder 22 or the bump 16 is formed of a solder ball in the mounting process, the electronic circuit device is melted at 200 to 250.degree. Is heated to
Since the thermal expansion coefficient of silicon is 3.4 ppm / ° C., while the thermal expansion coefficient of a glass epoxy-based mounting board which is generally widely used is as large as about 15 ppm / ° C., FIG. As shown in ()), when the temperature is lowered to about room temperature (about 20 ° C.), the bump 16 solidified at about 180 ° C.
Will be subjected to large stress. Further, FIG.
As shown in (1), the semiconductor chip 10 is heated to 100 ° C. or more every time the power is supplied, and thus the bumps 16 are repeatedly subjected to stress due to a temperature difference generated by turning on / off the chip. Due to the above-described stress strain, as shown in FIG. 11, cracks C are generated at the roots of the bumps 16 made of solder balls connecting the electrodes 10a of the semiconductor chip 10 and the lands 21 formed on the substrate 20 of the mounting substrate. There is a problem that connection failure is likely to occur.

【０００８】上記の接続不良の問題を解決する手段とし
て、実装基板材料として、半導体チップの熱膨張率に近
い材料を用いる方法があるが、この場合には材料が限定
されてしまい、かつ、そのような材料は一般に高価であ
るという欠点がある。As a means for solving the above-described problem of poor connection, there is a method of using a material having a coefficient of thermal expansion close to that of a semiconductor chip as a material of a mounting board. However, in this case, the material is limited and the material is limited. Such materials have the disadvantage that they are generally expensive.

【０００９】このため、バンプの根本を補強してクラッ
クが発生するのを防止する目的で、図１０に示すよう
に、ＣＳＰ形態の半導体装置１００ａと実装基板２の間
隙部をエポキシ樹脂などからなる封止樹脂３により封止
することが一般に行われている。For this reason, as shown in FIG. 10, the gap between the CSP-type semiconductor device 100a and the mounting board 2 is made of epoxy resin or the like for the purpose of reinforcing the roots of the bumps and preventing the occurrence of cracks. Sealing with a sealing resin 3 is generally performed.

【００１０】しかしながら、上記のような半導体装置と
実装基板の間隙部が封止樹脂により固められた実装形態
においては、半導体チップに不良が生じた場合には半導
体チップが実装された実装基板全体を丸ごと廃棄する
か、あるいは基板へのダメージを承知の上で化学的・機
械的な外力を加えて半導体チップを無理やりはぎ取る方
法しかなく、不良部品の交換（リワーク）作業が困難で
あった。However, in the above-described mounting mode in which the gap between the semiconductor device and the mounting substrate is solidified by a sealing resin, if a defect occurs in the semiconductor chip, the entire mounting substrate on which the semiconductor chip is mounted is removed. There has been no alternative but to discard the whole semiconductor chip or forcibly peel off the semiconductor chip by applying a chemical or mechanical external force while being aware of the damage to the substrate, and it has been difficult to replace defective parts (rework).

【００１１】上記の半導体装置に対して、不良部品の交
換（リワーク）作業を容易にするために、はんだバンプ
を２段重ねとし、下層側のバンプの間隙部のみを樹脂で
封止した形態の半導体装置およびその実装形態について
図面を参照して説明する。図１２（ａ）は上記の半導体
装置の概略断面図であり、図１２（ｂ）は図１２（ａ）
中のＡ部の拡大断面図である。半導体チップ１０のアル
ミニウムなどからなるパッド電極１１上に、例えば銅や
アルミニウムなどからなる配線層１２が形成されてお
り、パッド電極１１および配線層１２上に、例えば窒化
シリコン膜からなる保護膜１３が被覆して形成されてい
る。バンプ形成領域において、保護膜１３に対して配線
層１２を露出させる開口部が形成されている。この開口
部において、例えばクロム、銅、金の積層膜などからな
る導電膜１４が形成されており、その上層に、例えばは
んだボールなどからなる第１バンプ１６ａが形成されて
いる。ここで、第１バンプ１６ａを埋め込む程度の膜厚
の樹脂被膜３０により、第１バンプ１６ａの間隙部が封
止されている。さらに、第１バンプ１６ａの頂点近傍部
分が露出するように樹脂被膜３０の上面から研磨されて
おり、この露出した部分の第１バンプ１６ａに接続する
ように、例えばはんだボールなどからなる第２バンプ１
６が形成されている。以上のようにＣＳＰ形態の半導体
装置１００ｂが構成されている。In order to facilitate the work of replacing (reworking) defective components with the above semiconductor device, solder bumps are stacked in two stages and only the gaps between the lower bumps are sealed with resin. A semiconductor device and its mounting form will be described with reference to the drawings. FIG. 12A is a schematic cross-sectional view of the above-described semiconductor device, and FIG.
It is an expanded sectional view of the A section in the inside. A wiring layer 12 made of, for example, copper or aluminum is formed on a pad electrode 11 made of aluminum or the like of the semiconductor chip 10, and a protective film 13 made of, for example, a silicon nitride film is formed on the pad electrode 11 and the wiring layer 12. It is formed by coating. An opening for exposing the wiring layer 12 to the protective film 13 is formed in the bump formation region. In this opening, a conductive film 14 made of a laminated film of, for example, chromium, copper, or gold is formed, and a first bump 16a made of, for example, a solder ball is formed on the conductive film 14. Here, the gap between the first bumps 16a is sealed by the resin film 30 having a thickness enough to bury the first bumps 16a. Furthermore, the first bump 16a is polished from the upper surface of the resin film 30 so that the vicinity of the vertex is exposed, and the second bump made of, for example, a solder ball or the like is connected to the exposed portion of the first bump 16a. 1
6 are formed. As described above, the CSP type semiconductor device 100b is configured.

【００１２】次に、上記の半導体装置１００ｂを実装基
板に実装した電子回路装置について説明する。図１３は
上記の電子回路装置の断面図である。実装基板２は、図
１０に示す実装基板と同様であり、例えばガラスエポキ
シ系材料よりなる基板２０の上面において、実装する半
導体装置１００ｂの第２バンプ１６の形成位置に対応す
る位置に形成された銅などからなるランド（電極）２１
と、ランド２１に接続して、基板２０の表面上、裏面上
および基板２０内部などに形成されているプリント配線
部（不図示）を有している。ランド２１部分を除く基板
２０表面はソルダーレジスト（不図示）により被覆され
ている。Next, an electronic circuit device in which the semiconductor device 100b is mounted on a mounting board will be described. FIG. 13 is a sectional view of the electronic circuit device. The mounting substrate 2 is similar to the mounting substrate shown in FIG. 10, and is formed on the upper surface of the substrate 20 made of, for example, a glass epoxy material at a position corresponding to the formation position of the second bump 16 of the semiconductor device 100b to be mounted. Land (electrode) 21 made of copper or the like
And a printed wiring portion (not shown) formed on the front surface, the back surface, the inside of the substrate 20, and the like, connected to the land 21. The surface of the substrate 20 excluding the lands 21 is covered with a solder resist (not shown).

【００１３】上記のＣＳＰ形態の半導体装置１００ｂは
第２バンプ１６とランド２１を対応させて実装基板２上
にマウントされており、接合用のはんだ２２あるいは第
２バンプ１６がはんだボールからなる場合は第２バンプ
１６自身により、ランド２１と機械的、電気的に接続さ
れている。The CSP type semiconductor device 100b is mounted on the mounting substrate 2 so that the second bumps 16 and the lands 21 correspond to each other. When the bonding solder 22 or the second bump 16 is formed of a solder ball, The second bump 16 itself is mechanically and electrically connected to the land 21.

【００１４】上記の半導体装置においては、第１バンプ
の間隙部は樹脂で封止されているので、応力の集中する
バンプの根本の部分が補強されている。一方、第１バン
プと第２バンプの接合強度は十分強いので、実装基板に
実装したときに半導体装置の第２バンプと実装基板の間
隙部を樹脂で封止する必要はない。従って、半導体装置
を容易に取り外すことが可能となっており、デバイスチ
ップに不良が生じた場合においても、不良半導体装置の
交換作業を容易に行うことができる。In the above-described semiconductor device, since the gap between the first bumps is sealed with resin, the root portions of the bumps where stress is concentrated are reinforced. On the other hand, since the bonding strength between the first bump and the second bump is sufficiently high, it is not necessary to seal the gap between the second bump of the semiconductor device and the mounting substrate with a resin when mounted on the mounting substrate. Therefore, the semiconductor device can be easily removed, and even when a defect occurs in the device chip, the work of replacing the defective semiconductor device can be easily performed.

【００１５】[0015]

【発明が解決しようとする課題】しかしながら、上記の
図１２に示す半導体装置は、はんだバンプを２段重ねと
するために製造工程が複雑であり、製造コストが高く、
歩留りが低下しやすいという問題点を有している。However, in the semiconductor device shown in FIG. 12, the manufacturing process is complicated because the solder bumps are stacked in two stages, and the manufacturing cost is high.
There is a problem that the yield tends to decrease.

【００１６】バンプ接続の信頼性を向上させる方法につ
いて、バンプ材料に形状記憶合金を用い、その形状変化
による圧力を利用して接触向上を図る発明が特開昭６３
−２１０２２６号公報および特開平８−２６１８３１号
公報に開示されている。しかし、上記の方法では、樹脂
で固定すること、あるいは別法により事前に加圧してお
くことを前提としており、半導体チップに常時応力がか
かるという欠点がある。As a method of improving the reliability of bump connection, an invention is proposed in which a shape memory alloy is used as a bump material and contact is improved by utilizing a pressure due to a change in the shape.
Japanese Patent Application Laid-Open No. 210226/1996 and Japanese Patent Application Laid-Open No. Hei 8-261831. However, the above-described method is based on the premise that the semiconductor chip is fixed with a resin or is preliminarily pressurized by another method, and has a disadvantage that a stress is constantly applied to the semiconductor chip.

【００１７】また、特開平１−２７２９９号公報には、
形状記憶合金の超弾性の効果に着目し、溶融した超弾性
合金に半導体素子を浸潤させてバンプを形成する方法が
開示されている。しかし、上記の方法ではバンプの高さ
を一定に制御することが困難であり、さらにバンプの高
さを高くできないという欠点を有している。Also, Japanese Patent Application Laid-Open No. 1-227299 discloses that
Focusing on the superelastic effect of a shape memory alloy, a method of forming a bump by infiltrating a semiconductor element into a molten superelastic alloy is disclosed. However, the above-described method has a drawback that it is difficult to control the height of the bumps to be constant, and that the height of the bumps cannot be increased.

【００１８】また、特開平７−２８０７７７号公報に
は、上記と同様に形状記憶合金の超弾性の効果に着目
し、バンプを受ける実装基板側の電極のバリアメタルに
形状記憶合金を用いる方法が開示されている。しかし、
上記の方法では熱による反りや樹脂の収縮応力に対して
十分な効果を発揮できないという欠点を有している。Japanese Patent Application Laid-Open No. 7-280777 discloses a method in which the shape memory alloy is used as a barrier metal of an electrode on a mounting substrate receiving bumps, focusing on the superelastic effect of the shape memory alloy as described above. It has been disclosed. But,
The above method has a disadvantage that it cannot exert a sufficient effect on warpage due to heat or shrinkage stress of the resin.

【００１９】本発明は上記の問題に鑑みてなされたもの
であり、従って本発明の目的は、簡単な工程で製造で
き、製造コストの抑制と歩留りの向上が可能であり、チ
ップの交換作業が容易となるように半導体チップと実装
基板の間隙部を樹脂封止せずに、半導体チップと実装基
板の熱膨張率差に起因する応力歪を緩和して接続信頼性
を向上できるように半導体装置に形成される電極と、当
該電極を備えた半導体装置、および、半導体装置の製造
方法を提供することである。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and accordingly, it is an object of the present invention to make it possible to manufacture a semiconductor device by a simple process, to reduce the manufacturing cost and to improve the yield, and to perform a chip replacement operation. In order to improve the connection reliability by relaxing the stress distortion caused by the difference in the coefficient of thermal expansion between the semiconductor chip and the mounting board without resin sealing the gap between the semiconductor chip and the mounting board to facilitate the connection, An object of the present invention is to provide an electrode to be formed, a semiconductor device including the electrode, and a method for manufacturing the semiconductor device.

【００２０】[0020]

【課題を解決するための手段】上記の目的を達成するた
め、本発明の電極は、電子回路パターンが形成された半
導体チップ上に、前記電子回路パターンに接続するよう
に形成された電極であって、少なくとも一部がマルテン
サイト相とオーステナイト相との間の相転移温度が常温
よりも高く設定されている形状記憶合金からなる。In order to achieve the above object, an electrode according to the present invention is an electrode formed on a semiconductor chip having an electronic circuit pattern formed thereon so as to be connected to the electronic circuit pattern. In addition, at least a portion is formed of a shape memory alloy in which the phase transition temperature between the martensite phase and the austenite phase is set higher than room temperature.

【００２１】上記の本発明の電極は、好適には、前記マ
ルテンサイト相とオーステナイト相との間の相転移温度
が前記半導体チップの動作時の最高温度程度以上であ
る。In the above-mentioned electrode of the present invention, preferably, the phase transition temperature between the martensite phase and the austenite phase is about the maximum temperature during operation of the semiconductor chip.

【００２２】上記の本発明の電極は、好適には、前記オ
ーステナイト相における縦弾性係数が８０００ｋｇｆ／
ｍｍ2 以下であり、前記マルテンサイト相における縦弾
性係数が１６００ｋｇｆ／ｍｍ2 以下である。あるいは
好適には、前記オーステナイト相における横弾性係数が
２５００ｋｇｆ／ｍｍ2 以下であり、前記マルテンサイ
ト相における横弾性係数が５００ｋｇｆ／ｍｍ2 以下で
ある。The above-mentioned electrode of the present invention preferably has a longitudinal elastic modulus in the austenite phase of 8000 kgf /
and mm 2 or less, the longitudinal elastic modulus in the martensite phase is 1600 kgf / mm 2 or less. Alternatively, preferably, the transverse elastic coefficient in the austenite phase is 2500 kgf / mm 2 or less, and the transverse elastic coefficient in the martensite phase is 500 kgf / mm 2 or less.

【００２３】上記の本発明の電極は、好適には、前記半
導体チップ上に、前記半導体チップ表面から突起した形
状を有する。さらに好適には、前記半導体チップ上に前
記形状記憶合金からなるボールバンプが転写されて形成
されたバンプである。あるいは、さらに好適には、前記
半導体チップ上に形成された前記形状記憶合金からなる
スタッドバンプである。また、好適には、表面がニッケ
ル膜で被覆されている。The above-mentioned electrode of the present invention preferably has a shape projecting from the surface of the semiconductor chip on the semiconductor chip. More preferably, it is a bump formed by transferring a ball bump made of the shape memory alloy on the semiconductor chip. Or more preferably, it is a stud bump made of the shape memory alloy formed on the semiconductor chip. Preferably, the surface is covered with a nickel film.

【００２４】上記の本発明の電極は、電子回路パターン
が形成された半導体チップ上に、電子回路パターンに接
続するように形成された電極であって、少なくとも一部
がマルテンサイト相とオーステナイト相との間の相転移
温度が常温よりも高く、さらには相転移温度が前記半導
体チップの動作時の最高温度程度以上であり、オーステ
ナイト相における縦弾性係数が８０００ｋｇｆ／ｍｍ2
以下、横弾性係数が２５００ｋｇｆ／ｍｍ2 以下であ
り、マルテンサイト相における縦弾性係数が１６００ｋ
ｇｆ／ｍｍ2 以下、横弾性係数が５００ｋｇｆ／ｍｍ2
以下であるような弾性係数が小さい形状記憶合金からな
るので、常温などの低温領域においては電極を構成する
形状記憶合金の弾性係数が小さいために半導体チップと
実装基板の熱膨張率差に起因する応力歪を緩和すること
ができ、また、温度が高くなるに従って電極を構成する
形状記憶合金の弾性係数が大きくなってくるが、電極に
かかる応力歪が小さくなってくる。上記の電極は、上記
の材料を用いることで、簡単な工程で製造でき、製造コ
ストの抑制と歩留りの向上が可能である。また、チップ
の交換作業が容易となるように半導体チップと実装基板
の間隙部を樹脂封止せずに、半導体チップと実装基板の
熱膨張率差に起因する応力歪を緩和して接続信頼性を向
上できる。The above-mentioned electrode of the present invention is an electrode formed on a semiconductor chip on which an electronic circuit pattern is formed so as to be connected to the electronic circuit pattern, at least a part of which has a martensite phase and an austenite phase. Is higher than room temperature, the phase transition temperature is about the highest temperature during operation of the semiconductor chip or more, and the longitudinal elastic modulus in the austenite phase is 8000 kgf / mm 2.
Hereinafter, the transverse elastic modulus is 2500 kgf / mm 2 or less, and the longitudinal elastic modulus in the martensite phase is 1600 kF.
gf / mm 2 or less, transverse modulus of elasticity is 500 kgf / mm 2
It is made of a shape memory alloy having a small elastic coefficient as described below. In a low temperature region such as a normal temperature, the elastic coefficient of the shape memory alloy constituting the electrode is small, which is caused by a difference in thermal expansion coefficient between the semiconductor chip and the mounting substrate. The stress strain can be alleviated, and the elastic modulus of the shape memory alloy constituting the electrode increases as the temperature increases, but the stress strain applied to the electrode decreases. The above-mentioned electrode can be manufactured by a simple process by using the above-mentioned material, and thus, the manufacturing cost can be suppressed and the yield can be improved. In addition, the gap between the semiconductor chip and the mounting board is not resin-sealed to facilitate the chip replacement work, but the stress distortion caused by the difference in the coefficient of thermal expansion between the semiconductor chip and the mounting board is alleviated to improve the connection reliability. Can be improved.

【００２５】また、上記の目的を達成するため、本発明
の半導体装置は、電子回路パターンが形成された半導体
チップと、前記半導体チップ上に、前記電子回路パター
ンに接続するように形成され、少なくとも一部がマルテ
ンサイト相とオーステナイト相との間の相転移温度が常
温よりも高く設定されている形状記憶合金からなる電極
とを有する。In order to achieve the above object, a semiconductor device according to the present invention comprises: a semiconductor chip having an electronic circuit pattern formed thereon; and a semiconductor chip formed on the semiconductor chip so as to be connected to the electronic circuit pattern. Some have electrodes made of a shape memory alloy in which the phase transition temperature between the martensite phase and the austenite phase is set higher than room temperature.

【００２６】上記の本発明の半導体装置は、好適には、
前記形状記憶合金の前記マルテンサイト相とオーステナ
イト相との間の相転移温度が前記半導体チップの動作時
の最高温度程度以上である。The above semiconductor device of the present invention is preferably
A phase transition temperature between the martensite phase and the austenite phase of the shape memory alloy is equal to or higher than a maximum temperature during operation of the semiconductor chip.

【００２７】上記の本発明の半導体装置は、好適には、
前記形状記憶合金の前記オーステナイト相における縦弾
性係数が８０００ｋｇｆ／ｍｍ2 以下であり、前記マル
テンサイト相における縦弾性係数が１６００ｋｇｆ／ｍ
ｍ2 以下である。あるいは好適には、前記形状記憶合金
の前記オーステナイト相における横弾性係数が２５００
ｋｇｆ／ｍｍ2 以下であり、前記マルテンサイト相にお
ける横弾性係数が５００ｋｇｆ／ｍｍ2 以下である。The semiconductor device of the present invention described above preferably comprises
The longitudinal elastic modulus of the shape memory alloy in the austenite phase is 8000 kgf / mm 2 or less, and the longitudinal elastic modulus in the martensite phase is 1600 kgf / m.
m 2 or less. Alternatively, preferably, the transverse elastic modulus of the shape memory alloy in the austenite phase is 2500.
kgf / mm 2 or less, and the transverse elastic modulus in the martensite phase is 500 kgf / mm 2 or less.

【００２８】上記の本発明の半導体装置は、好適には、
前記電極が、前記半導体チップ表面から突起した形状を
有する。さらに好適には、前記電極が、前記半導体チッ
プ上に前記形状記憶合金からなるボールバンプが転写さ
れて形成されたバンプである。あるいは、さらに好適に
は、前記電極が、前記半導体チップ上に形成された前記
形状記憶合金からなるスタッドバンプである。また、好
適には、前記電極の表面がニッケル膜で被覆されてい
る。The semiconductor device of the present invention is preferably
The electrode has a shape protruding from the surface of the semiconductor chip. More preferably, the electrode is a bump formed by transferring a ball bump made of the shape memory alloy on the semiconductor chip. Alternatively, more preferably, the electrode is a stud bump made of the shape memory alloy formed on the semiconductor chip. Preferably, the surface of the electrode is covered with a nickel film.

【００２９】上記の本発明の半導体装置は、電子回路パ
ターンが形成された半導体チップと、前記半導体チップ
上に、前記電子回路パターンに接続するように形成さ
れ、少なくとも一部がマルテンサイト相とオーステナイ
ト相との間の相転移温度が常温よりも高く、さらには相
転移温度が前記半導体チップの動作時の最高温度程度以
上であり、オーステナイト相における縦弾性係数が８０
００ｋｇｆ／ｍｍ2 以下、横弾性係数が２５００ｋｇｆ
／ｍｍ2 以下であり、マルテンサイト相における縦弾性
係数が１６００ｋｇｆ／ｍｍ2 以下、横弾性係数が５０
０ｋｇｆ／ｍｍ2以下であるような弾性係数が小さい形
状記憶合金からなる電極とを有するので、常温などの低
温領域においては電極を構成する形状記憶合金の弾性係
数が小さいために半導体チップと実装基板の熱膨張率差
に起因する応力歪を緩和することができ、また、温度が
高くなるに従って電極を構成する形状記憶合金の弾性係
数が大きくなってくるが、電極にかかる応力歪が小さく
なってくる。上記の半導体装置の電極としては、上記の
材料を用いることで、簡単な工程で製造でき、製造コス
トの抑制と歩留りの向上が可能である。また、チップの
交換作業が容易となるように半導体チップと実装基板の
間隙部を樹脂封止せずに、半導体チップと実装基板の熱
膨張率差に起因する応力歪を緩和して接続信頼性を向上
できる。The semiconductor device according to the present invention has a semiconductor chip on which an electronic circuit pattern is formed, and is formed on the semiconductor chip so as to be connected to the electronic circuit pattern, and at least a part of the semiconductor chip has a martensitic phase and an austenitic phase. The phase transition temperature between the phase and the phase is higher than the normal temperature, the phase transition temperature is about the highest temperature during operation of the semiconductor chip or more, and the longitudinal elastic modulus in the austenite phase is 80%.
00 kgf / mm 2 or less, transverse elastic modulus 2500 kgf
/ Mm 2 or less, the longitudinal elastic modulus in the martensite phase is 1600 kgf / mm 2 or less, and the lateral elastic modulus is 50 or less.
Since it has an electrode made of a shape memory alloy having a small elastic coefficient of 0 kgf / mm 2 or less, the semiconductor chip and the mounting substrate are small in a low-temperature region such as room temperature because the shape memory alloy constituting the electrode has a small elastic coefficient. The stress strain caused by the difference in the coefficient of thermal expansion can be reduced, and the elastic modulus of the shape memory alloy constituting the electrode increases as the temperature increases, but the stress strain applied to the electrode decreases. come. By using the above-described materials for the electrodes of the semiconductor device, the electrodes can be manufactured in a simple process, so that the manufacturing cost can be suppressed and the yield can be improved. In addition, the gap between the semiconductor chip and the mounting board is not resin-sealed to facilitate the chip replacement work, but the stress distortion caused by the difference in the coefficient of thermal expansion between the semiconductor chip and the mounting board is alleviated to improve the connection reliability. Can be improved.

【００３０】また、上記の目的を達成するため、本発明
の半導体装置の製造方法は、電子回路パターンが形成さ
れた半導体チップ上に、前記電子回路パターンに接続す
るように、少なくとも一部がマルテンサイト相とオース
テナイト相との間の相転移温度が常温よりも高く設定さ
れている形状記憶合金からなる電極を形成する工程を有
する。According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a semiconductor chip on a semiconductor chip having an electronic circuit pattern formed thereon; A step of forming an electrode made of a shape memory alloy in which a phase transition temperature between a site phase and an austenite phase is set higher than room temperature.

【００３１】上記の本発明の半導体装置の製造方法は、
好適には、前記形状記憶合金として、前記マルテンサイ
ト相とオーステナイト相との間の相転移温度が前記半導
体チップの動作時の最高温度程度以上である形状記憶合
金を用いる。The method of manufacturing a semiconductor device according to the present invention described above
Preferably, as the shape memory alloy, a shape memory alloy whose phase transition temperature between the martensite phase and the austenite phase is about the highest temperature during operation of the semiconductor chip or more is used.

【００３２】上記の本発明の半導体装置は、好適には、
前記形状記憶合金として、前記オーステナイト相におけ
る縦弾性係数が８０００ｋｇｆ／ｍｍ2 以下であり、前
記マルテンサイト相における縦弾性係数が１６００ｋｇ
ｆ／ｍｍ2 以下である形状記憶合金を用いる。あるいは
好適には、前記形状記憶合金として、前記オーステナイ
ト相における横弾性係数が２５００ｋｇｆ／ｍｍ2 以下
であり、前記マルテンサイト相における横弾性係数が５
００ｋｇｆ／ｍｍ2 以下である形状記憶合金を用いる。The semiconductor device of the present invention is preferably
As the shape memory alloy, the longitudinal elastic modulus in the austenite phase is 8000 kgf / mm 2 or less, and the longitudinal elastic modulus in the martensite phase is 1600 kg.
A shape memory alloy having an f / mm 2 or less is used. Alternatively, preferably, the shape memory alloy has a transverse elastic modulus of 2500 kgf / mm 2 or less in the austenite phase and a transverse elastic modulus of 5 in the martensite phase.
A shape memory alloy having a weight of 00 kgf / mm 2 or less is used.

【００３３】上記の本発明の半導体装置は、好適には、
前記電極として、前記半導体チップ表面から突起した形
状となるように形成する。さらに好適には、前記電極と
して、前記半導体チップ上に前記形状記憶合金からなる
ボールバンプを転写して形成する。あるいは、さらに好
適には、前記電極として、前記形状記憶合金からなるワ
イヤを用いたワイヤボンディング法により、前記半導体
チップ上に前記形状記憶合金からなるスタッドバンプを
形成する。また、好適には、前記電極の表面をニッケル
膜で被覆する工程をさらに有する。The above-described semiconductor device of the present invention is preferably
The electrode is formed so as to have a shape protruding from the surface of the semiconductor chip. More preferably, the electrode is formed by transferring a ball bump made of the shape memory alloy on the semiconductor chip. Alternatively, more preferably, a stud bump made of the shape memory alloy is formed on the semiconductor chip by a wire bonding method using a wire made of the shape memory alloy as the electrode. Preferably, the method further includes a step of coating the surface of the electrode with a nickel film.

【００３４】上記の本発明の半導体装置の製造方法は、
電子回路パターンが形成された半導体チップ上に、前記
電子回路パターンに接続するように、少なくとも一部が
マルテンサイト相とオーステナイト相との間の相転移温
度が常温よりも高く、さらには相転移温度が前記半導体
チップの動作時の最高温度程度以上であり、オーステナ
イト相における縦弾性係数が８０００ｋｇｆ／ｍｍ2 以
下、横弾性係数が２５００ｋｇｆ／ｍｍ2 以下であり、
マルテンサイト相における縦弾性係数が１６００ｋｇｆ
／ｍｍ2 以下、横弾性係数が５００ｋｇｆ／ｍｍ2 以下
であるような弾性係数が小さい形状記憶合金からなる電
極を形成するので、常温などの低温領域においては電極
を構成する形状記憶合金の弾性係数が小さいために半導
体チップと実装基板の熱膨張率差に起因する応力歪を緩
和することができ、また、温度が高くなるに従って電極
を構成する形状記憶合金の弾性係数が大きくなってくる
が、電極にかかる応力歪が小さくなってくる。上記の半
導体装置の電極は、形状記憶合金からなるボールバンプ
の転写あるいは形状記憶合金からなるワイヤを用いたワ
イヤボンディング法を用いたスタッドバンプの形成な
ど、簡単な工程で製造でき、製造コストの抑制と歩留り
の向上が可能である。また、チップの交換作業が容易と
なるように半導体チップと実装基板の間隙部を樹脂封止
せずに、半導体チップと実装基板の熱膨張率差に起因す
る応力歪を緩和して接続信頼性を向上できる。The method of manufacturing a semiconductor device according to the present invention described above
On the semiconductor chip on which the electronic circuit pattern is formed, at least a part of the phase transition temperature between the martensite phase and the austenite phase is higher than room temperature so as to be connected to the electronic circuit pattern, and further, the phase transition temperature Is not less than the maximum temperature during operation of the semiconductor chip, the longitudinal elastic coefficient in the austenite phase is 8000 kgf / mm 2 or less, and the transverse elastic coefficient is 2500 kgf / mm 2 or less;
The longitudinal elastic modulus in the martensite phase is 1600 kgf
/ Mm 2 or less, and an electrode made of a shape memory alloy having a small elastic coefficient such that the transverse elastic coefficient is 500 kgf / mm 2 or less, the elastic coefficient of the shape memory alloy constituting the electrode in a low temperature region such as normal temperature. Is small, the stress strain caused by the difference in the coefficient of thermal expansion between the semiconductor chip and the mounting board can be reduced, and the elastic coefficient of the shape memory alloy forming the electrode increases as the temperature increases. The stress strain applied to the electrode becomes smaller. The electrodes of the above semiconductor device can be manufactured by simple processes such as transfer of a ball bump made of a shape memory alloy or formation of a stud bump using a wire bonding method using a wire made of a shape memory alloy, thereby reducing the manufacturing cost. And the yield can be improved. In addition, the gap between the semiconductor chip and the mounting board is not resin-sealed to facilitate the chip replacement work, but the stress distortion caused by the difference in the coefficient of thermal expansion between the semiconductor chip and the mounting board is alleviated to improve the connection reliability. Can be improved.

【００３５】[0035]

【発明の実施の形態】以下に、本発明の電極と当該電極
を用いた半導体装置、および、この半導体装置を実装基
板に実装した電子回路装置の実施の形態について、図面
を参照して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of an electrode of the present invention, a semiconductor device using the electrode, and an electronic circuit device in which the semiconductor device is mounted on a mounting board will be described below with reference to the drawings. .

【００３６】第１実施形態 図１（ａ）は本実施形態に係る半導体装置の概略断面図
であり、図１（ｂ）は図１（ａ）中のＡ部の拡大断面図
である。半導体チップ１０のアルミニウムなどからなる
パッド電極１１上に、例えば銅やアルミニウムなどから
なる配線層１２が形成されており、パッド電極１１およ
び配線層１２上に、例えば窒化シリコン膜からなる保護
膜１３が被覆して形成されている。バンプ形成領域にお
いて、保護膜１３に対して配線層１２を露出させる開口
部が形成されている。この開口部内の配線層１２上に、
ニッケル膜および金膜などの積層導電膜などの導電膜１
４が形成されており、その上層に、例えばＳｎ−Ｐｂ系
の鉛を含有するはんだ、あるいはＳｎ−Ａｇ系はんだ、
Ｓｎ−Ｚｎ系はんだ、Ｓｎ−Ｃｕ系はんだあるいはＳｂ
−Ｂｉ系はんだなどの鉛を含有しないはんだなどのはん
だ層１５により、表面をニッケル膜で被覆したＮｉ−Ｔ
ｉ、Ｎｉ−Ｔｉ−Ｃｕ、Ｎｉ−Ｔｉ−Ｃｏ、あるいは、
Ｎｉ−Ｔｉ−Ｈｆなどの形状記憶合金からなるボールバ
ンプ１６が接合して形成されている。以上のようにＣＳ
Ｐ形態の半導体装置１ａが構成されている。 First Embodiment FIG. 1A is a schematic sectional view of a semiconductor device according to the present embodiment, and FIG. 1B is an enlarged sectional view of a portion A in FIG. 1A. A wiring layer 12 made of, for example, copper or aluminum is formed on a pad electrode 11 made of aluminum or the like of the semiconductor chip 10, and a protective film 13 made of, for example, a silicon nitride film is formed on the pad electrode 11 and the wiring layer 12. It is formed by coating. An opening for exposing the wiring layer 12 to the protective film 13 is formed in the bump formation region. On the wiring layer 12 in this opening,
Conductive film 1 such as a laminated conductive film such as a nickel film and a gold film
4 is formed thereon, and for example, Sn-Pb-based lead-containing solder or Sn-Ag-based solder,
Sn-Zn based solder, Sn-Cu based solder or Sb
Ni-T whose surface is coated with a nickel film by a solder layer 15 such as lead-free solder such as Bi-based solder
i, Ni-Ti-Cu, Ni-Ti-Co, or
A ball bump 16 made of a shape memory alloy such as Ni-Ti-Hf is joined and formed. As described above, CS
A P-type semiconductor device 1a is configured.

【００３７】次に、上記の半導体装置１ａを実装基板に
実装した電子回路装置について説明する。図２は上記の
電子回路装置の断面図である。実装基板２は、例えばガ
ラスエポキシ系材料よりなる基板２０の上面において、
実装する半導体装置１ａのバンプ１６の形成位置に対応
する位置に形成された銅などからなるランド（電極）２
１と、ランド２１に接続して、基板２０の表面上、裏面
上および基板２０内部などに形成されているプリント配
線部（不図示）を有している。ランド２１部分を除く基
板２０表面はソルダーレジスト（不図示）により被覆さ
れている。Next, an electronic circuit device in which the semiconductor device 1a is mounted on a mounting board will be described. FIG. 2 is a sectional view of the electronic circuit device. The mounting board 2 is, for example, on
Land (electrode) 2 made of copper or the like formed at a position corresponding to the formation position of bump 16 of semiconductor device 1a to be mounted
1 and a printed wiring section (not shown) connected to the land 21 and formed on the front surface, the rear surface, the inside of the substrate 20, and the like of the substrate 20. The surface of the substrate 20 excluding the lands 21 is covered with a solder resist (not shown).

【００３８】上記のＣＳＰ形態の半導体装置１ａはバン
プ１６とランド２１を対応させて実装基板２上にマウン
トされており、例えばＳｎ−Ｐｂ系の鉛を含有するはん
だ、あるいはＳｎ−Ａｇ系はんだ、Ｓｎ−Ｚｎ系はん
だ、Ｓｎ−Ｃｕ系はんだあるいはＳｂ−Ｂｉ系はんだな
どの鉛を含有しないはんだなどの接合用のはんだ層２２
により、ランド２１と機械的、電気的に接続されてい
る。上記の形状記憶合金であるＴｉ系合金ははんだの濡
れ性が低いが、ニッケル膜で被覆することで改善するこ
とができる。The semiconductor device 1a of the CSP type is mounted on the mounting substrate 2 so that the bumps 16 and the lands 21 correspond to each other. For example, a solder containing Sn-Pb-based lead, a Sn-Ag-based solder, Solder layer 22 for joining lead-free solder such as Sn-Zn based solder, Sn-Cu based solder or Sb-Bi based solder
With this, it is mechanically and electrically connected to the land 21. The Ti-based alloy, which is the above shape memory alloy, has low solder wettability, but can be improved by coating with a nickel film.

【００３９】上記の半導体装置において、バンプ１６は
形状記憶合金から形成されている。ここで、形状記憶合
金は、図３に示すように、温度により低温側のマルテン
サイト相と高温側のオーステナイト相の２種類の結晶構
造をとり、その境界の温度領域は２相領域となる。In the above-described semiconductor device, the bumps 16 are formed from a shape memory alloy. Here, as shown in FIG. 3, the shape memory alloy has two types of crystal structures, a martensite phase on a low temperature side and an austenite phase on a high temperature side, depending on the temperature, and the boundary temperature region is a two-phase region.

【００４０】上記の低温側のマルテンサイト相と高温側
のオーステナイト相の間の相転移温度（図３を参照する
と、２相領域の温度に相当する）が常温よりも高く設定
されており、特に、相転移温度が上記の電子回路装置の
使用時（半導体チップの動作時）の発熱により昇温した
ときの温度程度以上とすることが好ましい。例えば、Ｎ
ｉ−Ｔｉからなる形状記憶合金では、マルテンサイト相
と２相領域の境界を６５℃程度であり、２相領域とオー
ステナイト相の境界を８０℃程度とすることができる。
また、例えばＮｉ−Ｔｉ−Ｃｕ（４５：４５：１０）の
場合、相転移温度を１００℃程度にすることができ、ま
た、Ｎｉ−Ｔｉ−Ｈｆ（３５：３５：３０）の場合は１
５０℃程度とすることができる。The phase transition temperature between the low-temperature side martensite phase and the high-temperature side austenite phase (corresponding to the temperature in the two-phase region with reference to FIG. 3) is set higher than normal temperature. Preferably, the phase transition temperature is about the same as or higher than the temperature when the electronic circuit device is heated (during operation of the semiconductor chip) due to heat generation. For example, N
In the shape memory alloy made of i-Ti, the boundary between the martensite phase and the two-phase region can be about 65 ° C, and the boundary between the two-phase region and the austenite phase can be about 80 ° C.
Further, for example, in the case of Ni-Ti-Cu (45:45:10), the phase transition temperature can be set to about 100 ° C, and in the case of Ni-Ti-Hf (35:35:30), 1 is obtained.
It can be about 50 ° C.

【００４１】上記の形状記憶合金では、弾性係数（Ｇ）
が温度によって変化し、マルテンサイト相では小さく、
オーステナイト相では大きく、２相領域は両相の弾性係
数をつなぐように滑らかに変化する領域となる。例え
ば、オーステナイト相における縦弾性係数が８０００ｋ
ｇｆ／ｍｍ2 以下であり、マルテンサイト相における縦
弾性係数が１６００ｋｇｆ／ｍｍ2 以下である、あるい
はオーステナイト相における横弾性係数が２５００ｋｇ
ｆ／ｍｍ2以下であり、マルテンサイト相における横弾
性係数が５００ｋｇｆ／ｍｍ2 以下であることが好まし
い。In the above shape memory alloy, the elastic modulus (G)
Changes with temperature and is small in the martensitic phase,
The austenite phase is large, and the two-phase region is a region that smoothly changes so as to connect the elastic coefficients of both phases. For example, the modulus of longitudinal elasticity in the austenite phase is 8000k
gf / mm 2 or less, and the longitudinal modulus in the martensite phase is 1600 kgf / mm 2 or less, or the transverse modulus in the austenite phase is 2500 kg.
f / mm 2 or less, and the transverse elastic modulus in the martensite phase is preferably 500 kgf / mm 2 or less.

【００４２】上記の形状記憶合金を用いたバンプを用い
ることにより、半導体装置の実装時の応力歪を緩和する
ことができる。これを図４を用いて説明する。図中、説
明を簡単にするために、半導体チップ１０、実装基板２
０、形状記憶合金からなるバンプ１６およびはんだ層
（１５，２２）のみを示している。図４（ａ）に示すよ
うに、半導体装置を実装基板に実装する工程において、
はんだを溶着するために２００〜２５０℃程度に加熱処
理する。このとき、半導体チップ１０と実装基板２０の
熱膨張率の差により両者の膨張量が異なっているが、両
者を固着するためのはんだ層（１５，２２）は溶融状態
であるので、バンプ接合部に応力はかからない。By using a bump made of the above shape memory alloy, it is possible to alleviate stress distortion during mounting of the semiconductor device. This will be described with reference to FIG. In the figure, the semiconductor chip 10 and the mounting substrate 2
0, only the bump 16 made of a shape memory alloy and the solder layers (15, 22) are shown. As shown in FIG. 4A, in the step of mounting the semiconductor device on the mounting board,
Heat treatment is performed at about 200 to 250 ° C. to weld the solder. At this time, the expansion amounts of the semiconductor chip 10 and the mounting substrate 20 are different due to the difference in the coefficient of thermal expansion. However, since the solder layers (15, 22) for fixing the two are in a molten state, the bump bonding portion No stress is applied.

【００４３】上記のようにリフロー工程を経て１８０℃
前後ではんだが固化し、バンプ接合された電子回路装置
が冷却したとき、装置がオフの状態では装置の温度が常
温（２０℃程度）となる。このとき、半導体チップ１０
よりも実装基板２０の方が熱膨張率が大きかったため
に、冷却による収縮量も半導体チップ１０よりも実装基
板２０の方が大きくなる。従って、はんだにより固着さ
れたバンプ接合部に応力歪が発生してしまうが、形状記
憶合金からなるバンプ１６は常温領域で弾性係数が非常
に小さいために、上記の応力歪を緩和することができ
る。After passing through the reflow process as described above,
When the solder is solidified before and after, and the electronic circuit device to which the bump bonding is performed cools, the temperature of the device becomes normal temperature (about 20 ° C.) when the device is off. At this time, the semiconductor chip 10
Since the mounting substrate 20 has a higher coefficient of thermal expansion than the semiconductor chip 10, the mounting substrate 20 also has a larger shrinkage due to cooling. Therefore, stress distortion occurs in the bump bonding portion fixed by the solder. However, since the bump 16 made of the shape memory alloy has a very small elastic coefficient in a normal temperature region, the above-mentioned stress distortion can be reduced. .

【００４４】また、装置がオンの状態では装置の発熱に
より加熱昇温して、例えば１００℃程度となる。温度が
上昇すると、形状記憶合金の弾性係数が高くなってくる
が、半導体チップ１０よりも実装基板２０の方が熱膨張
率が大きいので、実装基板２０の方がより大きく膨張
し、これは応力歪を緩和させる方向となる。以上のよう
に、形状記憶合金からなるバンプを用いることにより、
半導体チップと実装基板の熱膨張率差に起因する応力歪
を緩和して接続信頼性を向上することができる。When the apparatus is on, the temperature of the apparatus is increased by heating due to the heat generated by the apparatus, for example, about 100.degree. When the temperature rises, the elastic modulus of the shape memory alloy increases. However, since the thermal expansion coefficient of the mounting substrate 20 is larger than that of the semiconductor chip 10, the mounting substrate 20 expands more, and this It is in the direction to alleviate the distortion. As described above, by using a bump made of a shape memory alloy,
It is possible to alleviate the stress distortion caused by the difference in the coefficient of thermal expansion between the semiconductor chip and the mounting board, thereby improving the connection reliability.

【００４５】すなわち、本発明において用いる形状記憶
合金として、電子回路装置の通常の使用温度範囲におい
ては、主としてマルテンサイト相とオーステナイト相の
間の相転移温度よりも低温側のマルテンサイト相領域を
用いるものである。また、上記の領域を主として用いる
ことから、通常の形状記憶合金に形状を記憶させるため
に行われる熱処理は、本発明において用いる形状記憶合
金には不要である。That is, in the shape memory alloy used in the present invention, a martensite phase region which is lower in temperature than a phase transition temperature between a martensite phase and an austenite phase in a normal use temperature range of an electronic circuit device is used. Things. In addition, since the above-described region is mainly used, the heat treatment performed to store the shape in the ordinary shape memory alloy is unnecessary for the shape memory alloy used in the present invention.

【００４６】上記の本実施形態の半導体装置は、はんだ
ボールとして上記の形状記憶合金を用いることにより、
従来の方法と同様にして製造することができる。すなわ
ち、例えば、半導体チップ１０のアルミニウムなどから
なるパッド電極１１上に、例えば銅やアルミニウムなど
からなる配線層１２を形成し、パッド電極１１および配
線層１２上に、例えば窒化シリコン膜からなる保護膜１
３を被覆して形成する。次に、バンプ形成領域におい
て、保護膜１３に対して配線層１２を露出させる開口部
を形成する。この開口部内の配線層１２上に、ニッケル
膜および金膜などの積層導電膜などの導電膜１４を形成
する。その上層に、例えばＳｎ−Ｐｂ系の鉛を含有する
はんだなどのはんだ層１５を形成し、表面をニッケル膜
で被覆したＮｉ−Ｔｉ、Ｎｉ−Ｔｉ−Ｃｕ、Ｎｉ−Ｔｉ
−Ｃｏ、あるいは、Ｎｉ−Ｔｉ−Ｈｆなどの形状記憶合
金からなるボールバンプ１６を転写して、図１に示す半
導体装置を製造することができる。The semiconductor device of the present embodiment uses the shape memory alloy as the solder ball,
It can be manufactured in the same manner as in the conventional method. That is, for example, a wiring layer 12 made of, for example, copper or aluminum is formed on a pad electrode 11 made of, for example, aluminum of the semiconductor chip 10, and a protective film made of, for example, a silicon nitride film is formed on the pad electrode 11 and the wiring layer 12. 1
3 is formed. Next, an opening for exposing the wiring layer 12 to the protective film 13 is formed in the bump formation region. A conductive film 14 such as a laminated conductive film such as a nickel film and a gold film is formed on the wiring layer 12 in the opening. Ni-Ti, Ni-Ti-Cu, Ni-Ti whose upper layer is formed with a solder layer 15 such as a solder containing Sn-Pb-based lead and the surface of which is coated with a nickel film.
The semiconductor device shown in FIG. 1 can be manufactured by transferring the ball bump 16 made of a shape memory alloy such as -Co or Ni-Ti-Hf.

【００４７】上記のように、本実施形態の電極および半
導体装置によれば、常温などの低温領域においては電極
（ボールバンプ）を構成する形状記憶合金の弾性係数が
小さいために半導体チップと実装基板の熱膨張率差に起
因する応力歪を緩和することができ、また、温度が高く
なるに従って電極（ボールバンプ）を構成する形状記憶
合金の弾性係数が大きくなってくるが、電極（ボールバ
ンプ）にかかる応力歪が小さくなってくる。上記の半導
体装置の電極（ボールバンプ）としては、上記の材料を
用いたボールバンプの転写など、簡単な工程で製造で
き、製造コストの抑制と歩留りの向上が可能である。ま
た、チップの交換作業が容易となるように半導体チップ
と実装基板の間隙部を樹脂封止せずに、半導体チップと
実装基板の熱膨張率差に起因する応力歪を緩和して接続
信頼性を向上できる。As described above, according to the electrode and the semiconductor device of the present embodiment, the semiconductor chip and the mounting board are small in a low-temperature region such as a normal temperature because the shape memory alloy constituting the electrode (ball bump) has a small elastic coefficient. Can reduce stress distortion caused by a difference in thermal expansion coefficient between the electrodes. Also, as the temperature increases, the elastic coefficient of the shape memory alloy constituting the electrode (ball bump) increases. , The stress strain applied to the substrate becomes smaller. The electrodes (ball bumps) of the above-described semiconductor device can be manufactured by a simple process such as the transfer of ball bumps using the above-described materials, and the manufacturing cost can be suppressed and the yield can be improved. In addition, the gap between the semiconductor chip and the mounting board is not resin-sealed to facilitate the chip replacement work, but the stress distortion caused by the difference in the coefficient of thermal expansion between the semiconductor chip and the mounting board is alleviated to improve the connection reliability. Can be improved.

【００４８】第２実施形態 図５（ａ）は本実施形態に係る半導体装置の断面図であ
る。半導体チップ１０がインタポーザなどと呼ばれる基
板１７上に固着（ダイボンド）されており、半導体チッ
プ１０のパッド電極（不図示）と基板１７の配線部（不
図示）とを金ワイヤなどのワイヤボンディング１８によ
り接続されている。さらに、半導体チップ１０とワイヤ
ボンディング１８を被覆して、エポキシ樹脂などの封止
樹脂１９により封止されている。また、基板の裏面側表
面には、基板の配線部を介して半導体チップ１０のパッ
ド電極に接続するように、例えばＳｎ−Ｐｂ系の鉛を含
有するはんだ、あるいはＳｎ−Ａｇ系はんだ、Ｓｎ−Ｚ
ｎ系はんだ、Ｓｎ−Ｃｕ系はんだあるいはＳｂ−Ｂｉ系
はんだなどの鉛を含有しないはんだなどのはんだ層（不
図示）により、表面をニッケル膜で被覆したＮｉ−Ｔ
ｉ、Ｎｉ−Ｔｉ−Ｃｕ、Ｎｉ−Ｔｉ−Ｃｏ、あるいは、
Ｎｉ−Ｔｉ−Ｈｆなどの形状記憶合金からなるバンプ１
６が接合して形成されている。以上のようにＣＳＰ形態
の半導体装置１ｂが構成されている。 Second Embodiment FIG. 5A is a sectional view of a semiconductor device according to the second embodiment . The semiconductor chip 10 is fixed (die-bonded) on a substrate 17 called an interposer or the like, and a pad electrode (not shown) of the semiconductor chip 10 and a wiring portion (not shown) of the substrate 17 are bonded by wire bonding 18 such as a gold wire. It is connected. Further, the semiconductor chip 10 and the wire bonding 18 are covered and sealed with a sealing resin 19 such as an epoxy resin. Further, on the rear surface of the substrate, for example, a solder containing Sn-Pb-based lead, Sn-Ag-based solder, or Sn-Pb-based solder is connected to a pad electrode of the semiconductor chip 10 via a wiring portion of the substrate. Z
Ni-T whose surface is coated with a nickel film by a solder layer (not shown) such as a lead-free solder such as n-based solder, Sn-Cu-based solder, or Sb-Bi-based solder
i, Ni-Ti-Cu, Ni-Ti-Co, or
Bump 1 made of a shape memory alloy such as Ni-Ti-Hf
6 are formed by bonding. The CSP type semiconductor device 1b is configured as described above.

【００４９】次に、上記の半導体装置１ｂを実装基板に
実装した電子回路装置について説明する。図５（ｂ）は
上記の電子回路装置の断面図である。実装基板２は、例
えばガラスエポキシ系材料よりなる基板２０の上面にお
いて、実装する半導体装置１ｂのバンプ１６の形成位置
に対応する位置に形成された銅などからなるランド（電
極）２１と、ランド２１に接続して、基板２０の表面
上、裏面上および基板２０内部などに形成されているプ
リント配線部（不図示）を有している。ランド２１部分
を除く基板２０表面はソルダーレジスト（不図示）によ
り被覆されている。Next, an electronic circuit device in which the semiconductor device 1b is mounted on a mounting board will be described. FIG. 5B is a cross-sectional view of the above electronic circuit device. The mounting substrate 2 includes a land (electrode) 21 made of copper or the like formed at a position corresponding to a formation position of the bump 16 of the semiconductor device 1 b to be mounted on the upper surface of the substrate 20 made of, for example, a glass epoxy material, and a land 21. And a printed wiring portion (not shown) formed on the front surface, the rear surface, the inside of the substrate 20, and the like of the substrate 20. The surface of the substrate 20 excluding the lands 21 is covered with a solder resist (not shown).

【００５０】上記のＣＳＰ形態の半導体装置１ｂはバン
プ１６とランド２１を対応させて実装基板２上にマウン
トされており、例えばＳｎ−Ｐｂ系の鉛を含有するはん
だ、あるいはＳｎ−Ａｇ系はんだ、Ｓｎ−Ｚｎ系はん
だ、Ｓｎ−Ｃｕ系はんだあるいはＳｂ−Ｂｉ系はんだな
どの鉛を含有しないはんだなどの接合用のはんだ層２２
により、ランド２１と機械的、電気的に接続されてい
る。The semiconductor device 1b of the CSP type is mounted on the mounting substrate 2 so that the bumps 16 and the lands 21 correspond to each other. For example, a solder containing Sn-Pb-based lead, a Sn-Ag-based solder, Solder layer 22 for joining lead-free solder such as Sn-Zn based solder, Sn-Cu based solder or Sb-Bi based solder
With this, it is mechanically and electrically connected to the land 21.

【００５１】上記の半導体装置において、バンプ１６
は、第１実施形態と同様に、例えばマルテンサイト相と
オーステナイト相の間の相転移温度が常温よりも高く設
定されており、好ましくは相転移温度が上記の電子回路
装置の使用時（半導体チップの動作時）の発熱により昇
温したときの温度程度以上である形状記憶合金から形成
されている。従って、実装基板とインタポーザと呼ばれ
る基板を構成する材料がそれぞれガラスエポキシ系材料
とセラミックである場合など、熱膨張率が異なる材料に
より構成される場合に、常温などの低温領域においては
電極（ボールバンプ）を構成する形状記憶合金の弾性係
数が小さいためにインタポーザと実装基板の熱膨張率差
に起因する応力歪を緩和することができ、また、温度が
高くなるに従って電極（ボールバンプ）を構成する形状
記憶合金の弾性係数が大きくなってくるが、電極（ボー
ルバンプ）にかかる応力歪が小さくなってくる。上記の
半導体装置の電極（ボールバンプ）としては、上記の材
料を用いたボールバンプの転写など、簡単な工程で製造
でき、製造コストの抑制と歩留りの向上が可能である。
また、チップの交換作業が容易となるように半導体チッ
プと実装基板の間隙部を樹脂封止せずに、半導体チップ
と実装基板の熱膨張率差に起因する応力歪を緩和して接
続信頼性を向上できる。In the above semiconductor device, the bump 16
In the same manner as in the first embodiment, for example, the phase transition temperature between the martensite phase and the austenite phase is set higher than room temperature, and preferably the phase transition temperature is set when the above-described electronic circuit device is used (semiconductor chip). ) Is formed from a shape memory alloy whose temperature is about equal to or higher than the temperature when the temperature is increased by the heat generated during the operation of (2). Therefore, when the mounting substrate and the substrate called an interposer are made of materials having different coefficients of thermal expansion, such as a case where the materials constituting the interposer are a glass epoxy material and a ceramic, respectively, electrodes (ball bumps) are used in a low temperature region such as room temperature. ) Can reduce stress distortion caused by a difference in thermal expansion coefficient between the interposer and the mounting substrate because the elastic modulus of the shape memory alloy is small. Also, the electrodes (ball bumps) are configured as the temperature increases. Although the elastic modulus of the shape memory alloy increases, the stress strain applied to the electrodes (ball bumps) decreases. The electrodes (ball bumps) of the above-described semiconductor device can be manufactured by a simple process such as the transfer of ball bumps using the above-described materials, and the manufacturing cost can be suppressed and the yield can be improved.
In addition, the gap between the semiconductor chip and the mounting board is not resin-sealed to facilitate the chip replacement work, but the stress distortion caused by the difference in the coefficient of thermal expansion between the semiconductor chip and the mounting board is alleviated to improve the connection reliability. Can be improved.

【００５２】第３実施形態 図６（ａ）は本実施形態に係る半導体装置１ｃの断面図
である。実質的に第１実施形態と同様であるが、バンプ
１６が、ワイヤボンディング法により形状記憶合金ワイ
ヤを半導体チップの電極部に固着し、先端部を残して切
断することで形成するスタッドバンプとなっていること
が異なる。 Third Embodiment FIG. 6A is a sectional view of a semiconductor device 1c according to the third embodiment . Substantially the same as in the first embodiment, but the bump 16 is a stud bump formed by fixing a shape memory alloy wire to an electrode portion of a semiconductor chip by a wire bonding method and cutting off the tip end portion. Is different.

【００５３】次に、上記の半導体装置１ｃを実装基板に
実装した電子回路装置について説明する。図６（ｂ）は
上記の電子回路装置の断面図である。例えばガラスエポ
キシ系材料よりなる基板２０の上面において、実装する
半導体装置１ｃのバンプ１６の形成位置に対応する位置
に形成されたランド（電極）２１と不図示のプリント配
線部を有する実装基板上に、半導体装置１ｃがバンプ１
６とランド２１を対応させてマウントされており、例え
ばＳｎ−Ａｇ系はんだなどの鉛を含有しないはんだなど
の接合用のはんだ層２２により、ランド２１と機械的、
電気的に接続されている。Next, an electronic circuit device in which the semiconductor device 1c is mounted on a mounting board will be described. FIG. 6B is a cross-sectional view of the electronic circuit device. For example, on a mounting board having a land (electrode) 21 formed at a position corresponding to the formation position of the bump 16 of the semiconductor device 1c to be mounted and a printed wiring portion (not shown) on the upper surface of the substrate 20 made of a glass epoxy material, for example. , The semiconductor device 1c is the bump 1
6 and the land 21 are mounted so as to correspond to each other. For example, the land 21 is mechanically and mechanically connected to the land 21 by a bonding solder layer 22 such as a lead-free solder such as Sn-Ag solder.
It is electrically connected.

【００５４】上記の半導体装置において、バンプ１６
は、第１実施形態と同様に、例えばマルテンサイト相と
オーステナイト相の間の相転移温度が常温よりも高く設
定されており、好ましくは相転移温度が上記の電子回路
装置の使用時（半導体チップの動作時）の発熱により昇
温したときの温度程度以上である形状記憶合金から形成
されている。従って、常温などの低温領域においては電
極（スタッドバンプ）を構成する形状記憶合金の弾性係
数が小さいために半導体チップと実装基板の熱膨張率差
に起因する応力歪を緩和することができ、また、温度が
高くなるに従って電極（スタッドバンプ）を構成する形
状記憶合金の弾性係数が大きくなってくるが、電極（ス
タッドバンプ）にかかる応力歪が小さくなってくる。上
記の半導体装置の電極（スタッドバンプ）としては、上
記の材料を用いたワイヤによるワイヤボンディング法な
どにより、簡単な工程で製造でき、製造コストの抑制と
歩留りの向上が可能である。また、チップの交換作業が
容易となるように半導体チップと実装基板の間隙部を樹
脂封止せずに、半導体チップと実装基板の熱膨張率差に
起因する応力歪を緩和して接続信頼性を向上できる。In the above semiconductor device, the bump 16
In the same manner as in the first embodiment, for example, the phase transition temperature between the martensite phase and the austenite phase is set higher than room temperature, and preferably the phase transition temperature is set when the above-described electronic circuit device is used (semiconductor chip). ) Is formed from a shape memory alloy whose temperature is about equal to or higher than the temperature when the temperature is increased by the heat generated during the operation of (2). Therefore, in a low-temperature region such as room temperature, since the elastic modulus of the shape memory alloy constituting the electrode (stud bump) is small, stress distortion caused by a difference in thermal expansion coefficient between the semiconductor chip and the mounting substrate can be reduced. As the temperature increases, the elastic modulus of the shape memory alloy forming the electrode (stud bump) increases, but the stress strain applied to the electrode (stud bump) decreases. The electrodes (stud bumps) of the semiconductor device can be manufactured in a simple process by a wire bonding method using a wire using the above-described material, so that the manufacturing cost can be suppressed and the yield can be improved. In addition, the gap between the semiconductor chip and the mounting board is not resin-sealed to facilitate the chip replacement work, but the stress distortion caused by the difference in the coefficient of thermal expansion between the semiconductor chip and the mounting board is alleviated to improve the connection reliability. Can be improved.

【００５５】第４実施形態 図７（ａ）は本実施形態に係る半導体装置１ｄの断面図
である。実質的に第２実施形態と同様であるが、バンプ
１６が、ワイヤボンディング法により形状記憶合金ワイ
ヤを半導体チップの電極部に固着し、先端部を残して切
断することで形成するスタッドバンプとなっていること
が異なる。 Fourth Embodiment FIG. 7A is a sectional view of a semiconductor device 1d according to the present embodiment. Although substantially the same as the second embodiment, the bump 16 is a stud bump formed by fixing the shape memory alloy wire to the electrode portion of the semiconductor chip by the wire bonding method and cutting the tip portion while leaving the tip portion. Is different.

【００５６】次に、上記の半導体装置１ｄを実装基板に
実装した電子回路装置について説明する。図７（ｂ）は
上記の電子回路装置の断面図である。例えばガラスエポ
キシ系材料よりなる基板２０の上面において、実装する
半導体装置１ｄのバンプ１６の形成位置に対応する位置
に形成されたランド（電極）２１と不図示のプリント配
線部を有する実装基板上に、半導体装置１ｄがバンプ１
６とランド２１を対応させてマウントされており、例え
ばＳｎ−Ａｇ系はんだなどの鉛を含有しないはんだなど
の接合用のはんだ層２２により、ランド２１と機械的、
電気的に接続されている。Next, an electronic circuit device in which the semiconductor device 1d is mounted on a mounting board will be described. FIG. 7B is a cross-sectional view of the above electronic circuit device. For example, on a mounting board having a land (electrode) 21 formed at a position corresponding to the formation position of the bump 16 of the semiconductor device 1d to be mounted and a printed wiring portion (not shown) on the upper surface of the substrate 20 made of, for example, a glass epoxy material. The semiconductor device 1d is the bump 1
6 and the land 21 are mounted so as to correspond to each other. For example, the land 21 is mechanically and mechanically connected to the land 21 by a bonding solder layer 22 such as a lead-free solder such as Sn-Ag solder.
It is electrically connected.

【００５７】上記の半導体装置において、バンプ１６
は、第１実施形態と同様に、例えばマルテンサイト相と
オーステナイト相の間の相転移温度が常温よりも高く設
定されており、好ましくは相転移温度が上記の電子回路
装置の使用時（半導体チップの動作時）の発熱により昇
温したときの温度程度以上である形状記憶合金から形成
されている。従って、実装基板とインタポーザと呼ばれ
る基板を構成する材料がそれぞれガラスエポキシ系材料
とセラミックである場合など、熱膨張率が異なる材料に
より構成される場合に、常温などの低温領域においては
電極（スタッドバンプ）を構成する形状記憶合金の弾性
係数が小さいためにインタポーザと実装基板の熱膨張率
差に起因する応力歪を緩和することができ、また、温度
が高くなるに従って電極（スタッドバンプ）を構成する
形状記憶合金の弾性係数が大きくなってくるが、電極
（スタッドバンプ）にかかる応力歪が小さくなってく
る。上記の半導体装置の電極（スタッドバンプ）として
は、上記の材料を用いたワイヤによるワイヤボンディン
グ法などにより、簡単な工程で製造でき、製造コストの
抑制と歩留りの向上が可能である。また、チップの交換
作業が容易となるように半導体チップと実装基板の間隙
部を樹脂封止せずに、半導体チップと実装基板の熱膨張
率差に起因する応力歪を緩和して接続信頼性を向上でき
る。In the above semiconductor device, the bump 16
In the same manner as in the first embodiment, for example, the phase transition temperature between the martensite phase and the austenite phase is set higher than room temperature, and preferably the phase transition temperature is set when the above-described electronic circuit device is used (semiconductor chip). ) Is formed from a shape memory alloy whose temperature is about equal to or higher than the temperature when the temperature is increased by the heat generated during the operation of (2). Therefore, when the mounting substrate and the substrate, which is called an interposer, are made of materials having different coefficients of thermal expansion such as a glass epoxy material and a ceramic, respectively, electrodes (stud bumps) are used in a low temperature region such as room temperature. ) Can reduce stress distortion caused by a difference in thermal expansion coefficient between the interposer and the mounting board, and also forms electrodes (stud bumps) as the temperature increases. Although the elastic modulus of the shape memory alloy increases, the stress strain applied to the electrodes (stud bumps) decreases. The electrodes (stud bumps) of the semiconductor device can be manufactured in a simple process by a wire bonding method using a wire using the above-described material, so that the manufacturing cost can be suppressed and the yield can be improved. In addition, the gap between the semiconductor chip and the mounting board is not resin-sealed to facilitate the chip replacement work, but the stress distortion caused by the difference in the coefficient of thermal expansion between the semiconductor chip and the mounting board is alleviated to improve the connection reliability. Can be improved.

【００５８】第５実施形態 図８（ａ）は本実施形態に係る半導体装置１ｅの断面図
である。実質的に第３実施形態と同様であるが、スタッ
ドバンプ形状を有するバンプ１６に、テール部Ｔが形成
されていることが異なる。また、図８（ｂ）は上記の半
導体装置１ｅを実装基板に実装した電子回路装置の断面
図である。例えばガラスエポキシ系材料よりなる基板２
０の上面に、実装する半導体装置１ｅのバンプ１６の形
成位置に対応する位置に形成されたランド（電極）２１
を有する実装基板上に、半導体装置１ｄがバンプ１６と
ランド２１を対応させてマウントされており、例えばＳ
ｎ−Ａｇ系はんだなどの鉛を含有しないはんだなどの接
合用のはんだ層２２により、ランド２１と機械的、電気
的に接続されている。 Fifth Embodiment FIG. 8A is a sectional view of a semiconductor device 1e according to the fifth embodiment . The third embodiment is substantially the same as the third embodiment, except that a tail portion T is formed on a bump 16 having a stud bump shape. FIG. 8B is a cross-sectional view of an electronic circuit device in which the semiconductor device 1e is mounted on a mounting board. For example, a substrate 2 made of a glass epoxy material
Land (electrode) 21 formed at a position corresponding to the formation position of the bump 16 of the semiconductor device 1e to be mounted on the upper surface of the semiconductor device 1e
The semiconductor device 1d is mounted on the mounting substrate having the bumps 16 and the lands 21 in correspondence with each other.
The lands 21 are mechanically and electrically connected to each other by a solder layer 22 for bonding such as a lead-free solder such as an n-Ag solder.

【００５９】上記の半導体装置において、バンプ１６
は、第１実施形態と同様に、例えばマルテンサイト相と
オーステナイト相の間の相転移温度が常温よりも高く設
定されており、好ましくは相転移温度が上記の電子回路
装置の使用時（半導体チップの動作時）の発熱により昇
温したときの温度程度以上である形状記憶合金から形成
されている。従って、常温などの低温領域においては電
極（スタッドバンプ）を構成する形状記憶合金の弾性係
数が小さいために半導体チップと実装基板の熱膨張率差
に起因する応力歪を緩和することができ、また、温度が
高くなるに従って電極（スタッドバンプ）を構成する形
状記憶合金の弾性係数が大きくなってくるが、電極（ス
タッドバンプ）にかかる応力歪が小さくなってくる。上
記の半導体装置の電極（スタッドバンプ）としては、上
記の材料を用いたワイヤによるワイヤボンディング法な
どにより、簡単な工程で製造でき、製造コストの抑制と
歩留りの向上が可能である。また、チップの交換作業が
容易となるように半導体チップと実装基板の間隙部を樹
脂封止せずに、半導体チップと実装基板の熱膨張率差に
起因する応力歪を緩和して接続信頼性を向上できる。In the above semiconductor device, the bump 16
In the same manner as in the first embodiment, for example, the phase transition temperature between the martensite phase and the austenite phase is set higher than room temperature, and preferably the phase transition temperature is set when the above-described electronic circuit device is used (semiconductor chip). ) Is formed from a shape memory alloy whose temperature is about equal to or higher than the temperature when the temperature is increased by the heat generated during the operation of (2). Therefore, in a low-temperature region such as room temperature, since the elastic modulus of the shape memory alloy constituting the electrode (stud bump) is small, stress distortion caused by a difference in thermal expansion coefficient between the semiconductor chip and the mounting substrate can be reduced. As the temperature increases, the elastic modulus of the shape memory alloy forming the electrode (stud bump) increases, but the stress strain applied to the electrode (stud bump) decreases. The electrodes (stud bumps) of the semiconductor device can be manufactured in a simple process by a wire bonding method using a wire using the above-described material, so that the manufacturing cost can be suppressed and the yield can be improved. In addition, the gap between the semiconductor chip and the mounting board is not resin-sealed to facilitate the chip replacement work, but the stress distortion caused by the difference in the coefficient of thermal expansion between the semiconductor chip and the mounting board is alleviated to improve the connection reliability. Can be improved.

【００６０】本発明の電極を形成する半導体装置として
は、ＭＯＳトランジスタ系半導体装置、バイポーラ系半
導体装置、ＢｉＣＭＯＳ系半導体装置、ロジックとメモ
リを搭載した半導体装置など、半導体装置であれば何に
でも適用可能である。The semiconductor device for forming the electrode of the present invention is applicable to any semiconductor device such as a MOS transistor semiconductor device, a bipolar semiconductor device, a BiCMOS semiconductor device, and a semiconductor device having a logic and a memory. It is possible.

【００６１】本発明の電極および半導体装置は上記の実
施の形態に限定されない。例えば、形状記憶合金の組成
としては、上記で示した以外のものを用いることが可能
である。また、パッド電極上にバンプをはんだ接合する
構成などとすることも可能である。その他、本発明の要
旨を逸脱しない範囲で種々の変更が可能である。The electrodes and the semiconductor device of the present invention are not limited to the above embodiment. For example, the composition of the shape memory alloy can be other than the above. Further, it is also possible to adopt a configuration in which a bump is soldered on a pad electrode. In addition, various changes can be made without departing from the gist of the present invention.

【００６２】[0062]

【発明の効果】上記のように、本発明によれば、簡単な
工程で製造でき、製造コストの抑制と歩留りの向上が可
能であり、チップの交換作業が容易となるように半導体
チップと実装基板の間隙部を樹脂封止せずに、半導体チ
ップと実装基板の熱膨張率差に起因する応力歪を緩和し
て接続信頼性を向上できる電極と、それを備えた半導体
装置およびその製造方法を提供できる。As described above, according to the present invention, the semiconductor device can be manufactured by a simple process, the manufacturing cost can be reduced, the yield can be improved, and the semiconductor chip can be easily mounted. An electrode capable of improving connection reliability by relieving stress distortion caused by a difference in thermal expansion coefficient between a semiconductor chip and a mounting substrate without resin sealing a gap portion of a substrate, a semiconductor device including the same, and a method of manufacturing the same. Can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図１】図１（ａ）は本実施形態に係る半導体装置の概
略断面図であり、図１（ｂ）は図１（ａ）中のＡ部の拡
大断面図である。FIG. 1A is a schematic cross-sectional view of a semiconductor device according to the present embodiment, and FIG. 1B is an enlarged cross-sectional view of a portion A in FIG. 1A.

【図２】図２は第１実施形態に係る電子回路装置の断面
図である。FIG. 2 is a cross-sectional view of the electronic circuit device according to the first embodiment.

【図３】図３は形状記憶合金の弾性係数の温度依存性を
示すグラフである。FIG. 3 is a graph showing the temperature dependence of the elastic modulus of a shape memory alloy.

【図４】図４（ａ）〜（ｃ）はバンプとして形状記憶合
金を用いたときの応力を緩和する機構を説明するための
模式的断面図である。FIGS. 4A to 4C are schematic cross-sectional views illustrating a mechanism for relaxing stress when a shape memory alloy is used as a bump.

【図５】図５（ａ）は第２実施形態に係る半導体装置の
断面図であり、図５（ｂ）は第２実施形態に係る電子回
路装置の断面図である。FIG. 5A is a cross-sectional view of a semiconductor device according to a second embodiment, and FIG. 5B is a cross-sectional view of an electronic circuit device according to the second embodiment.

【図６】図６（ａ）は第３実施形態に係る半導体装置の
断面図であり、図６（ｂ）は第３実施形態に係る電子回
路装置の断面図である。FIG. 6A is a sectional view of a semiconductor device according to a third embodiment, and FIG. 6B is a sectional view of an electronic circuit device according to the third embodiment.

【図７】図７（ａ）は第４実施形態に係る半導体装置の
断面図であり、図７（ｂ）は第４実施形態に係る電子回
路装置の断面図である。FIG. 7A is a sectional view of a semiconductor device according to a fourth embodiment, and FIG. 7B is a sectional view of an electronic circuit device according to the fourth embodiment.

【図８】図８（ａ）は第５実施形態に係る半導体装置の
断面図であり、図８（ｂ）は第５実施形態に係る電子回
路装置の断面図である。FIG. 8A is a cross-sectional view of a semiconductor device according to a fifth embodiment, and FIG. 8B is a cross-sectional view of an electronic circuit device according to the fifth embodiment.

【図９】図９（ａ）は第１従来例に係る半導体装置の概
略断面図であり、図９（ｂ）は図９（ａ）中のＡ部の拡
大断面図である。9A is a schematic cross-sectional view of a semiconductor device according to a first conventional example, and FIG. 9B is an enlarged cross-sectional view of a portion A in FIG. 9A.

【図１０】図１０は第１従来例に係る電子回路装置の断
面図である。FIG. 10 is a sectional view of an electronic circuit device according to a first conventional example.

【図１１】図１１ははんだバンプ接合部にクラックが形
成された状態を示す断面図である。FIG. 11 is a cross-sectional view showing a state where a crack is formed at a solder bump joint.

【図１２】図１２（ａ）は第２従来例に係る半導体装置
の概略断面図であり、図１２（ｂ）は図１２（ａ）中の
Ａ部の拡大断面図である。12A is a schematic sectional view of a semiconductor device according to a second conventional example, and FIG. 12B is an enlarged sectional view of a portion A in FIG. 12A.

【図１３】図１３は第２従来例に係る電子回路装置の断
面図である。FIG. 13 is a sectional view of an electronic circuit device according to a second conventional example.

【符号の説明】[Explanation of symbols]

１ａ，１ｂ，１ｃ，１ｄ，１ｅ，１００ａ，１００ｂ…
半導体装置、２…実装基板、３…封止樹脂、１０…半導
体チップ、１１…パッド電極、１２…配線層、１３…保
護膜、１４…導電膜、１５，２２…はんだ層、１６…
（第２）バンプ、１６ａ…第１ハンプ、１７…樹脂被
膜、２０…基板、２１…ランド、３０…樹脂被膜。1a, 1b, 1c, 1d, 1e, 100a, 100b ...
Semiconductor device, 2 mounting board, 3 sealing resin, 10 semiconductor chip, 11 pad electrode, 12 wiring layer, 13 protective film, 14 conductive film, 15, 22 solder layer, 16
(Second) Bump, 16a: First hump, 17: Resin coating, 20: Substrate, 21: Land, 30: Resin coating.

Claims (25)

【特許請求の範囲】[Claims] 【請求項１】電子回路パターンが形成された半導体チッ
プ上に、前記電子回路パターンに接続するように形成さ
れた電極であって、 少なくとも一部がマルテンサイト相とオーステナイト相
との間の相転移温度が常温よりも高く設定されている形
状記憶合金からなる電極。An electrode formed on a semiconductor chip on which an electronic circuit pattern is formed so as to be connected to the electronic circuit pattern, at least a part of which is a phase transition between a martensite phase and an austenite phase. An electrode made of a shape memory alloy whose temperature is set higher than normal temperature. 【請求項２】前記マルテンサイト相とオーステナイト相
との間の相転移温度が前記半導体チップの動作時の最高
温度程度以上である請求項１記載の電極。2. The electrode according to claim 1, wherein a phase transition temperature between the martensite phase and the austenite phase is about the highest temperature during operation of the semiconductor chip. 【請求項３】前記オーステナイト相における縦弾性係数
が８０００ｋｇｆ／ｍｍ2 以下であり、前記マルテンサ
イト相における縦弾性係数が１６００ｋｇｆ／ｍｍ2 以
下である請求項１記載の電極。3. The electrode according to claim 1, wherein the modulus of longitudinal elasticity in the austenite phase is 8000 kgf / mm 2 or less, and the modulus of longitudinal elasticity in the martensite phase is 1600 kgf / mm 2 or less. 【請求項４】前記オーステナイト相における横弾性係数
が２５００ｋｇｆ／ｍｍ2 以下であり、前記マルテンサ
イト相における横弾性係数が５００ｋｇｆ／ｍｍ2 以下
である請求項１記載の電極。4. The electrode according to claim 1, wherein a transverse elastic modulus in said austenite phase is 2500 kgf / mm 2 or less, and a transverse elastic modulus in said martensite phase is 500 kgf / mm 2 or less. 【請求項５】前記半導体チップ上に、前記半導体チップ
表面から突起した形状を有する請求項１記載の電極。5. The electrode according to claim 1, wherein the electrode has a shape projecting from the surface of the semiconductor chip on the semiconductor chip. 【請求項６】前記半導体チップ上に前記形状記憶合金か
らなるボールバンプが転写されて形成されたバンプであ
る請求項５記載の電極。6. The electrode according to claim 5, wherein the bump is formed by transferring a ball bump made of the shape memory alloy onto the semiconductor chip. 【請求項７】前記半導体チップ上に形成された前記形状
記憶合金からなるスタッドバンプである請求項５記載の
電極。7. The electrode according to claim 5, wherein said electrode is a stud bump made of said shape memory alloy formed on said semiconductor chip. 【請求項８】表面がニッケル膜で被覆されている請求項
１記載の電極。8. The electrode according to claim 1, wherein the surface is covered with a nickel film. 【請求項９】電子回路パターンが形成された半導体チッ
プと、 前記半導体チップ上に、前記電子回路パターンに接続す
るように形成され、少なくとも一部がマルテンサイト相
とオーステナイト相との間の相転移温度が常温よりも高
く設定されている形状記憶合金からなる電極とを有する
半導体装置。9. A semiconductor chip on which an electronic circuit pattern is formed, and a phase transition between the martensite phase and the austenite phase formed on the semiconductor chip so as to be connected to the electronic circuit pattern. An electrode made of a shape memory alloy whose temperature is set higher than room temperature. 【請求項１０】前記形状記憶合金の前記マルテンサイト
相とオーステナイト相との間の相転移温度が前記半導体
チップの動作時の最高温度程度以上である請求項９記載
の半導体装置。10. The semiconductor device according to claim 9, wherein a phase transition temperature between the martensite phase and the austenite phase of the shape memory alloy is about the maximum temperature during operation of the semiconductor chip. 【請求項１１】前記形状記憶合金の前記オーステナイト
相における縦弾性係数が８０００ｋｇｆ／ｍｍ2 以下で
あり、前記マルテンサイト相における縦弾性係数が１６
００ｋｇｆ／ｍｍ2 以下である請求項９記載の半導体装
置。11. A longitudinal elastic modulus of the shape memory alloy in the austenite phase is 8000 kgf / mm 2 or less, and a longitudinal elastic modulus in the martensite phase is 16 kgf / mm 2.
The semiconductor device according to claim 9, wherein the pressure is not more than 00 kgf / mm 2 . 【請求項１２】前記形状記憶合金の前記オーステナイト
相における横弾性係数が２５００ｋｇｆ／ｍｍ2 以下で
あり、前記マルテンサイト相における横弾性係数が５０
０ｋｇｆ／ｍｍ2 以下である請求項９記載の半導体装
置。12. A transverse elastic modulus of the shape memory alloy in the austenite phase is 2500 kgf / mm 2 or less, and a transverse elastic modulus in the martensite phase is 50 or less.
The semiconductor device according to claim 9, wherein the pressure is 0 kgf / mm 2 or less. 【請求項１３】前記電極が、前記半導体チップ表面から
突起した形状を有する請求項９記載の半導体装置。13. The semiconductor device according to claim 9, wherein said electrode has a shape protruding from a surface of said semiconductor chip. 【請求項１４】前記電極が、前記半導体チップ上に前記
形状記憶合金からなるボールバンプが転写されて形成さ
れたバンプである請求項１３記載の半導体装置。14. The semiconductor device according to claim 13, wherein said electrode is a bump formed by transferring a ball bump made of said shape memory alloy on said semiconductor chip. 【請求項１５】前記電極が、前記半導体チップ上に形成
された前記形状記憶合金からなるスタッドバンプである
請求項１３記載の半導体装置。15. The semiconductor device according to claim 13, wherein said electrode is a stud bump made of said shape memory alloy formed on said semiconductor chip. 【請求項１６】前記電極の表面がニッケル膜で被覆され
ている請求項９記載の半導体装置。16. The semiconductor device according to claim 9, wherein a surface of said electrode is covered with a nickel film. 【請求項１７】電子回路パターンが形成された半導体チ
ップ上に、前記電子回路パターンに接続するように、少
なくとも一部がマルテンサイト相とオーステナイト相と
の間の相転移温度が常温よりも高く設定されている形状
記憶合金からなる電極を形成する工程を有する半導体装
置の製造方法。17. A phase transition temperature between a martensite phase and an austenite phase is set at least partially higher than a normal temperature on a semiconductor chip on which an electronic circuit pattern is formed so as to be connected to the electronic circuit pattern. A method of manufacturing a semiconductor device, the method including a step of forming an electrode made of a shape memory alloy. 【請求項１８】前記形状記憶合金として、前記マルテン
サイト相とオーステナイト相との間の相転移温度が前記
半導体チップの動作時の最高温度程度以上である形状記
憶合金を用いる請求項１７記載の半導体装置の製造方
法。18. The semiconductor according to claim 17, wherein the shape memory alloy is a shape memory alloy having a phase transition temperature between the martensite phase and the austenite phase which is equal to or higher than the maximum temperature during operation of the semiconductor chip. Device manufacturing method. 【請求項１９】前記形状記憶合金として、前記オーステ
ナイト相における縦弾性係数が８０００ｋｇｆ／ｍｍ2
以下であり、前記マルテンサイト相における縦弾性係数
が１６００ｋｇｆ／ｍｍ2 以下である形状記憶合金を用
いる請求項１７記載の半導体装置の製造方法。19. The shape memory alloy, wherein the austenitic phase has a modulus of longitudinal elasticity of 8000 kgf / mm 2.
18. The method of manufacturing a semiconductor device according to claim 17, wherein a shape memory alloy having a longitudinal elastic modulus of not more than 1600 kgf / mm 2 in the martensite phase is used. 【請求項２０】前記形状記憶合金として、前記オーステ
ナイト相における横弾性係数が２５００ｋｇｆ／ｍｍ2
以下であり、前記マルテンサイト相における横弾性係数
が５００ｋｇｆ／ｍｍ2 以下である形状記憶合金を用い
る請求項１７記載の半導体装置の製造方法。20. The shape memory alloy, wherein the austenite phase has a transverse elastic modulus of 2500 kgf / mm 2.
18. The method for manufacturing a semiconductor device according to claim 17, wherein a shape memory alloy having a transverse elastic modulus of 500 kgf / mm 2 or less in the martensite phase is used. 【請求項２１】前記電極として、前記半導体チップ表面
から突起した形状となるように形成する請求項１７記載
の半導体装置の製造方法。21. The method according to claim 17, wherein the electrode is formed so as to have a shape protruding from the surface of the semiconductor chip. 【請求項２２】前記電極として、前記半導体チップ上に
前記形状記憶合金からなるボールバンプを転写して形成
する請求項２１記載の半導体装置の製造方法。22. The method according to claim 21, wherein the electrode is formed by transferring a ball bump made of the shape memory alloy on the semiconductor chip. 【請求項２３】前記電極として、前記半導体チップ上に
前記形状記憶合金からなるスタッドバンプを形成する請
求項２１記載の半導体装置の製造方法。23. The method according to claim 21, wherein a stud bump made of the shape memory alloy is formed on the semiconductor chip as the electrode. 【請求項２４】前記電極として、前記形状記憶合金から
なるワイヤを用いたワイヤボンディング法により、前記
スタッドバンプを形成する請求項２３記載の半導体装置
の製造方法。24. The method according to claim 23, wherein the stud bump is formed by a wire bonding method using a wire made of the shape memory alloy as the electrode. 【請求項２５】前記電極の表面をニッケル膜で被覆する
工程をさらに有する請求項１７記載の半導体装置の製造
方法。25. The method of manufacturing a semiconductor device according to claim 17, further comprising a step of coating a surface of said electrode with a nickel film.
JP33679499A 1999-11-26 1999-11-26 Electrode, semiconductor device and method for manufacture thereof Pending JP2001156095A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7800210B2 (en) 2005-03-18 2010-09-21 Fujitsu Semiconductor Limited Semiconductor device
KR101242272B1 (en) * 2011-02-15 2013-03-11 주식회사 케이씨텍 Unit to Supply Cathode Voltage and Apparatus to Plate Substrate Having the Same
CN110290451A (en) * 2019-06-26 2019-09-27 维沃移动通信有限公司 A kind of package assembling and microphone mould group
CN111244076A (en) * 2018-11-29 2020-06-05 株式会社辉元 Transparent LED panel

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7800210B2 (en) 2005-03-18 2010-09-21 Fujitsu Semiconductor Limited Semiconductor device
KR101242272B1 (en) * 2011-02-15 2013-03-11 주식회사 케이씨텍 Unit to Supply Cathode Voltage and Apparatus to Plate Substrate Having the Same
CN111244076A (en) * 2018-11-29 2020-06-05 株式会社辉元 Transparent LED panel
CN110290451A (en) * 2019-06-26 2019-09-27 维沃移动通信有限公司 A kind of package assembling and microphone mould group

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