JPS63129450A - Command transfer system - Google Patents

Abstract

PURPOSE:To eliminate the need of a command establishing signal and to start an operation immediately at the time of receiving a command, by operating an external circuit by using the data housing pulse of the command. CONSTITUTION:A command sending means 1 which sends a control command and data attached on the control command, and a control means 2 which fetches the data from the command sending means 1 and also performs control corresponding to the control command at the time of adding the control command, are provided. The command sending means 1 adds the data required for the control by the control means 2 on the control means 2. And after those data are sent, the command is added on the command control means 2. The data is the one attached on the command, and the control means 2 starts a control operation corresponding to the command with an inputted data at the time of adding the command. Since the control means 2 starts the operation when the command is added, it is possible to eliminate the need of a conventional command establishing signal.

Description

[Detailed Description of the Invention] C Overview] In an information processing device, data and a command are received, and the processing is delayed because the information processing device operates according to a command establishment signal that is added afterwards. The present invention starts an operation with a command added after data, and the present invention enables a command transfer method that does not require a command establishment signal and further allows a faster start of response processing to a command.

[Industrial application field]

The present invention relates to an information processing device, and particularly to a command transfer method for a device that operates based on a command and data accompanying the command.

[Conventional technology]

2. Description of the Related Art Information processing devices and control devices are connected to devices such as host computers that enable these devices to perform desired operations.

Generally, an interface circuit is provided between the above-mentioned host computer and various devices to send and receive commands and a plurality of data accompanying them, and one device that receives them is further provided with a register to store the commands and data. ing.

For example, when controlling these devices from a host computer and making them perform the desired operation, the host computer adds commands and data (not necessarily data, but may also be subcommands, etc.) to the control device, etc. The command and data were first stored in the registers of the device.

After that, a command establishment signal is added to start the processing operation corresponding to the data and command stored in the register mentioned above.

FIG. 4 is a block diagram of the conventional system, and FIG. 5 is a timing chart of the conventional system.

The processor (CPU) 10 uses the register address line ADH.
, a data line DA, and a command establishment signal line C.

When operating, for example, an external device 11 from the processor (CPU) 10, data output processing is performed to store data in a target register. First, data to be stored in the target register is output to the data line DA. Then, the register address corresponding to the target register is output to the register address line ADR. The register address line ADH is connected to the decoder 13 of the control circuit 12,
Decoder 13 decodes the added register address. The decoded output of the decoder 13 is in registers 14 to 16.
, and outputs a storage signal to the registers 14 to 16 in accordance with the added register address.

Data input terminals of the registers 14 to 16 are connected to a data line DA, and data output from the processor (CPU) 10 is added to the input. When a storage signal is applied from the decoder described above, the corresponding register takes in the data.

The processor circuit sequentially sends data and commands to registers intended for the operations described above. For example, if the register 14 is a command register, as shown in FIG. 5, command data CR is stored in the register 14, and then data DPI and DR2 are stored in registers 15 and 16. After storing the target data and commands in the registers 14 to 16, the processor (CPU) 10 outputs a command establishment signal C8 to the command establishment signal line C.

The outputs of the registers 14 to 16 and the command establishment signal line C are connected to terminals 1+ to X3, op of the external device 11, and when the command establishment signal C8 is applied, the external device 11 receives the command and data at the fall of the signal. perform the corresponding action. For example, if the external device is a power supply, the upper and lower limits of the output voltage are stored in registers 15 and 16, and upper and lower limit value setting commands are sent to register 14. Then, when the command establishment signal CS is applied, the upper and lower limits of the power supply are set. When the upper and lower limit values are exceeded, an alarm signal is added to a line (not shown), and information such as power supply abnormality is sent to the processor CPU.

The above-described operation is for setting upper and lower limit values, but this operation is also similar for commands such as setting output voltage.

As described above, the conventional circuit controls the external device 11 by applying the command establishment signal CS to the external device after setting the registers during section A (between points a and b) in FIG.

Note that in the above-described operation, the order in which commands and data are stored in the registers is not limited, and the external device 11 operates based on the data and commands stored in the registers 14 to 16 when the command establishment signal is applied. do.

[Problem that the invention seeks to solve]

In the above-mentioned operation, the method of adding a command establishment signal after storing data, commands, etc. in the target register is as follows.
This requires processing to output the command establishment signal, which poses a problem in that the start of the entire processing operation is delayed.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional drawbacks, it is an object of the present invention to provide a command transfer method that does not require a command establishment signal and starts operation immediately upon reception of a command.

[Means for solving problems]

FIG. 1 is a functional block diagram of the present invention. 1 is a command sending means for sending a control command and data accompanying the control command; 2 is a means for receiving the data from the command sending means, and when the control command is added, performs control corresponding to the control command; It is a control means to perform.

[For production]

The command sending means 1 adds data necessary for controlling the control means 2 to the control means 2. Then, after sending out those data, a command is applied to the control means 2. The data is data accompanying the command, and the control means 2 starts a control operation corresponding to the command together with the data input when the command is added. Since the control means 2 starts operating when a command is applied, there is no need for a command establishment signal or the like as in the prior art.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

Processor (CPU) 3 uses register address lines ADR,
It has a data line DA and a register address line ADH.
are commonly connected to the decoder 5 in the control circuit 4, and the data line DA is commonly connected to the registers 6.7.8.

In the processor (CPU) 3, when a control request for the external circuit 9 occurs, the processor 3 first outputs the data DRI.
, DR2 are stored in register 7.8. This storage first outputs data to the data line DA, and then outputs the address value to be stored to the register address line ADR. Since the address value is applied to the decoder 5, the decoder 5 outputs, for example, II level to the output terminal corresponding to the address value. The decoder output of decoder 5 is in registers 6 to 81,
The register to which the H level is applied takes in the data on the data line DA at the rising edge of the register. For example, data DPI and DR2 are sequentially taken into register 7.8 by the above-described operation.

Register 6 is a register that stores commands, and processor 3 stores data corresponding to the command in register 6.
is stored using the operation described above. On the other hand, the decoded output of the decoder 5 is applied to the input clock terminal of the register 6 as described above, but is also applied to the terminal OP of the external circuit. This terminal OP is an operation start signal terminal, and the external circuit 9 starts its operation when the signal applied to this terminal falls, that is, changes from H level to L level.

The terminals ■1 to ■3 of the external circuit 9 are connected to the outputs of the registers 6 to 8, and in the conventional circuit, the operation corresponding to the contents of this register starts at the fall of the signal applied to the terminal OP mentioned above. outputs a command establishment signal from the processor 3. However, in the embodiment of the present invention, this is not necessary, and the external circuit 9 starts operating at the fall of the signal 1g generated by the decoder 5 when the command is stored in the register 6.

FIG. 3 is a timing chart of the embodiment of the present invention described above.

For example, when a command requires decoders DRI and DR2, data DPI is stored in register 7, and then data DR2 is stored in register 8. After all the target data is stored, the command CR related to the data is finally stored in the register 6. This operation is performed in section A (between point a and point A). When storing this command CR, the decoder 5 outputs an H level signal.

The register 6 takes in data (commands output from the processor 3) on the data line at the rise of the signal output from the decoder 5, that is, when the signal changes from L level to H level.

Although not shown in FIG. 2, a chip selection signal, that is, a signal for enabling the decoder 5 is added to the decoder, and the decoder 5 is enabled when the register address is determined. That is, the decoder 5 outputs an H level pulse at that time. At this rising edge, register 6 takes in the command on data line DA.

Then, at the falling edge, the external circuit 9 operates. For example, when the external circuit 9 is a power supply controlled by the computer 3, it stores data (upper limit voltage value, lower limit voltage value) in response to the processor (CPU 3) upper and lower limit value setting commands in the register 7.8, as in the past. . Then, execute the upper and lower limit value setting commands and store them in the register. At the fall of the command storage pulse in the register 6, this power supply executes the upper and lower limit value setting commands. After this setting, the power supply outputs an alarm signal (not shown) to the processor 3 when the output voltage falls outside the voltage range due to load conditions.

There are other commands as well, such as an output voltage setting command and a current protection setting command, which can set conditions for the power supply.

As described above, the present invention operates external circuits such as a power supply immediately after a command is stored, so there is no need to generate a command confirmation signal, etc., as in the past, and time is required for processing to generate it. I don't.

Although the embodiments of the present invention have been described with respect to power supply control, the present invention is not limited to this and can be similarly applied to other devices.

〔Effect of the invention〕

As described above, since the present invention operates the external circuit using the data storage pulse of the command, there is no need to send a command confirmation signal from the processor that controls it. It is possible to obtain a command transfer method that does not require a rising signal and starts operation immediately upon reception of a command.

[Brief explanation of the drawing]

Fig. 1 is a functional block diagram of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a timing chart of the present invention, Fig. 4 is a block diagram of a conventional system, and Fig. 5 is a conventional system. This is a timing chart. ■...Command sending means, 2...Controlling means. Patent Applicant: Fujitsu Limited 1L Lock Diagram of the Present Invention (Fig. 1) Figure 2: 1 L of Lock Diagram (1) Chart Figure 3 Conventional Ga 2 Lecture Halo Figure 4

Claims (1)

[Claims] a command sending means (1) for sending out a control command and data accompanying the control command; and a command sending means (1) that takes in the data from the command sending means (1) and responds to the control command when the control command is added. 1. A command transfer method characterized by comprising: a control means (2) for performing control.