JPS63126277A - Field effect thin film transistor - Google Patents
Field effect thin film transistorInfo
- Publication number
- JPS63126277A JPS63126277A JP16748486A JP16748486A JPS63126277A JP S63126277 A JPS63126277 A JP S63126277A JP 16748486 A JP16748486 A JP 16748486A JP 16748486 A JP16748486 A JP 16748486A JP S63126277 A JPS63126277 A JP S63126277A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- insulating film
- amorphous silicon
- liquid crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 8
- 230000005669 field effect Effects 0.000 title claims description 5
- 239000010408 film Substances 0.000 claims abstract description 68
- 238000000034 method Methods 0.000 claims abstract description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 12
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 9
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 abstract description 4
- 238000002161 passivation Methods 0.000 abstract description 3
- 239000007864 aqueous solution Substances 0.000 abstract description 2
- 229910052697 platinum Inorganic materials 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000010407 anodic oxide Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000002048 anodisation reaction Methods 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は電界効果型薄膜トランジスタに関するもので
、とりわけ電界効果型薄膜トランジスタにおけるゲート
絶縁物の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to field effect thin film transistors, and more particularly to improvements in gate insulators in field effect thin film transistors.
（従来の技術）
従来技術として液晶表示パネルにおけるアモルファスシ
リコン型の電界効果型薄膜トランジスタを例にとると、
第５図において、ガラス、石英などの基板１上にゲート
電極２を形成する。ついでプラズマＣＶＤ法によりゲー
ト絶縁膜３としてシリコン窒化膜またはシリコン酸化膜
を形成後、イントリンシックアモルファスシリコン膜４
、リンをドーピングしたｎ型アモルファスシリコン膜５
をそれぞれ連続で成膜させる。そして上記イントリンシ
ックアモルファスシリコン膜４およびｎ型アモルファス
シリコン膜５をエツチングして必要な部分のみを残す（
第６図）。この上にアルミニウム金属によりソース電極
６、ドレイン電極７を形成する（第７図）。 この基板
は液晶セルに用いられるもので、この上に液晶駆動用電
極としてＩＴＯ膜８を形成する（第８図）。パシベーシ
ョン膜９としてシリコン酸化膜またはシリコン窒化膜を
プラズマエツチングで形成する。さらにアルミニウムに
より光シールド膜１０を形成し、その上を全体をおおっ
て、ポリイミド系の樹脂やシリコン酸化物により液晶配
向膜１１を形成している（第９図）。(Prior art) Taking an example of an amorphous silicon field effect thin film transistor in a liquid crystal display panel as a conventional technology,
In FIG. 5, a gate electrode 2 is formed on a substrate 1 made of glass, quartz, or the like. Next, after forming a silicon nitride film or a silicon oxide film as the gate insulating film 3 by plasma CVD method, an intrinsic amorphous silicon film 4 is formed.
, phosphorus-doped n-type amorphous silicon film 5
are successively deposited. Then, the intrinsic amorphous silicon film 4 and the n-type amorphous silicon film 5 are etched to leave only the necessary portions (
Figure 6). A source electrode 6 and a drain electrode 7 are formed thereon using aluminum metal (FIG. 7). This substrate is used for a liquid crystal cell, and an ITO film 8 is formed thereon as a liquid crystal driving electrode (FIG. 8). A silicon oxide film or a silicon nitride film is formed as the passivation film 9 by plasma etching. Further, a light shielding film 10 is formed of aluminum, and a liquid crystal alignment film 11 is formed of polyimide resin or silicon oxide covering the entire surface thereof (FIG. 9).
（発明が解決しようとする問題点）
上述の従来例における基板をマトリックス型液晶表示装
置等に用いる場合、トランジスタの数が、数十個から数
百万個必要となり、その欠陥数が歩留に影響する。この
欠陥の発生する箇所の多くはゲート電極２とソース電極
６、ドレイン電極７の交叉部分である。その原因はシリ
コン窒化膜またはシリコン酸化膜よりなるゲート絶縁物
３のフレークやゴミ等によるピンホールによりソース電
極６、ドレイン電極７とゲート電極２にリーク電流が流
れるためである。(Problems to be Solved by the Invention) When the above-mentioned conventional substrate is used in a matrix type liquid crystal display device, etc., the number of transistors is required from several tens to several million, and the number of defects affects the yield. Affect. Many of the locations where this defect occurs are at the intersections of the gate electrode 2, source electrode 6, and drain electrode 7. The reason for this is that a leakage current flows through the source electrode 6, drain electrode 7, and gate electrode 2 due to pinholes caused by flakes, dust, etc. in the gate insulator 3 made of a silicon nitride film or a silicon oxide film.
［問題点を解決するための手段］
この発明は、このような従来例における欠点を解決する
ためのものでゲート絶縁膜を異なる方法で２層に成膜す
ることにより、ピンホールの発生を低減させる″ように
したものである。[Means for Solving the Problems] This invention is intended to solve the drawbacks of the conventional example, and reduces the occurrence of pinholes by forming the gate insulating film in two layers using different methods. It was designed so that the
（実施例） 実施例１ つぎに本発明の実施例について説明する。(Example) Example 1 Next, embodiments of the present invention will be described.
第１図において、ガラスなどよりなる基板２０上にゲー
ト電極２１を形成する。ゲート電極２１の材料としては
タンタル、アルミニウムなどの陽極酸化可能な金属でし
かも酸化物の絶縁性のよいものを用いる。陽極酸化膜の
形成方法としては、ゲート電極２１をパターニングした
後、第２図示のように、０．０１〜０．１％のクエン酸
水溶液２２をつくり、ゲート電極２１を正電極に、白金
板２３を負電極としてこの中に入れる。ゲート電極２１
としてタンタルを用いた場合にはＴａＯが形成されるが
、これは２ＯＡ／ＩＶ位の成膜速度があり、その比誘電
率は２２位である。またＡｌ２Ｏ３膜の比誘電率は８位
であり、いずれも５ｔ０２の比誘電率の３４５〜３．９
より大きいので膜厚を厚くとれる。ゲート電極２１上に
陽極酸化膜による第１の絶縁膜２４を形成した後、プラ
ズマＣＶＤ法によりシリコン窒化膜またはシリコン酸化
膜により第２の絶縁膜２５を形成し、さらに真空度を落
さず連続して、イントリンシックアモルファスシリコン
２６、ｎ型アモルファスシリコン２７の各層を成膜する
（第３図）。これ以降は従来方法と同じ工程でソース・
ドレイン電極、透明電極、パシベーション膜、光シール
ド膜、液晶配向膜などを形成して、薄膜トランジスタを
設けた液晶パネルを形成する。 この実施例ではゲト絶
縁膜は陽極酸化膜の第１の絶縁膜２４とシリコン窒化物
またはシリコン酸化物による第２の絶縁膜２５の２層に
より構成されることになる。In FIG. 1, a gate electrode 21 is formed on a substrate 20 made of glass or the like. As the material for the gate electrode 21, a metal that can be anodized, such as tantalum or aluminum, and is an oxide with good insulation properties is used. As for the method of forming the anodic oxide film, after patterning the gate electrode 21, as shown in the second figure, a 0.01 to 0.1% citric acid aqueous solution 22 is prepared, and a platinum plate is formed using the gate electrode 21 as a positive electrode. 23 is placed in this as a negative electrode. Gate electrode 21
When tantalum is used as the material, TaO is formed, which has a film formation rate of about 2OA/IV and a dielectric constant of about 22nd. In addition, the dielectric constant of the Al2O3 film is 8th place, which is 345 to 3.9 of the dielectric constant of 5t02.
Since it is larger, the film thickness can be increased. After forming a first insulating film 24 made of an anodic oxide film on the gate electrode 21, a second insulating film 25 made of a silicon nitride film or a silicon oxide film is formed by a plasma CVD method, and then the second insulating film 25 is formed continuously without reducing the degree of vacuum. Then, layers of intrinsic amorphous silicon 26 and n-type amorphous silicon 27 are formed (FIG. 3). From this point onwards, follow the same process as the conventional method to prepare the sauce.
A drain electrode, a transparent electrode, a passivation film, a light shield film, a liquid crystal alignment film, etc. are formed to form a liquid crystal panel provided with thin film transistors. In this embodiment, the gate insulating film is composed of two layers: a first insulating film 24 of an anodic oxide film and a second insulating film 25 of silicon nitride or silicon oxide.
なお第１の絶縁膜２４の陽極酸化膜は、第２の絶縁膜２
５を形成後、陽極化成して形成することも可能である。Note that the anodized film of the first insulating film 24 is different from that of the second insulating film 2.
It is also possible to perform anodization after forming 5.
また第１の絶縁膜２４の陽極酸化膜は第２の絶縁膜２５
で覆った後連続してアモルファスシリコン層を形成後陽
極化成することも可能である。さらに第１の絶縁膜２４
はゲート電極を高温中で酸化して形成してもよい。Further, the anodized film of the first insulating film 24 is the anodized film of the second insulating film 25.
It is also possible to continuously form an amorphous silicon layer and then anodize it. Furthermore, the first insulating film 24
may be formed by oxidizing the gate electrode at high temperature.
実施例２
第４図において、基板３０上にゲート電極３１を形成後
シリコン窒化膜やシリコン酸化膜による第１の絶縁膜３
２をプラズマＣＶＤ法以外のＣＶＤ法、すなわち常圧Ｃ
ＶＤ法、減圧ＣＶＤ法、光ＣＶＤ法などで形成し、その
後節２の絶縁膜３３としとてプラズマＣＶＤ法によりシ
リコン窒化膜やシリコン酸化膜を形成する。つぎに連続
して、真空度を落さず、イントリンシックアモルファス
シリコン３４、ｎ型アモルファスシリコン３５の各層を
成膜し、これ以降は従来方法と同じ工程で薄膜トランジ
スタを形成する。Embodiment 2 In FIG. 4, after forming a gate electrode 31 on a substrate 30, a first insulating film 3 made of a silicon nitride film or a silicon oxide film is formed.
2 by CVD method other than plasma CVD method, that is, normal pressure C
It is formed by a VD method, a low pressure CVD method, a photo-CVD method, etc., and then a silicon nitride film or a silicon oxide film is formed by a plasma CVD method as the insulating film 33 of Section 2. Next, each layer of intrinsic amorphous silicon 34 and n-type amorphous silicon 35 is successively formed without lowering the degree of vacuum, and thereafter a thin film transistor is formed using the same steps as the conventional method.
この実施例ではゲート絶縁膜はプラズマＣＶＤ法以外の
ＣＶＤ法による第１の絶縁膜３２とプラズマＣＶＤ法に
よる第２の絶縁膜３３の２層により形成されることにな
る。In this embodiment, the gate insulating film is formed of two layers: a first insulating film 32 formed by a CVD method other than the plasma CVD method, and a second insulating film 33 formed by a plasma CVD method.
なおこの実施例におけるゲート絶縁膜の２種類の絶縁膜
３２．３３は逆にして形成してもよい。Note that the two types of insulating films 32 and 33 of the gate insulating film in this embodiment may be reversely formed.
以上要するに、ゲート絶縁膜を異なる成膜方法で２層に
形成すればよい。In short, the gate insulating film may be formed in two layers using different film formation methods.
［発明の効果］
この発明によれば、ゲート絶縁膜が異なる方法により形
成された２層の絶縁膜で構成されるので、ピンホールを
低減することができ歩留を向上させることができる。[Effects of the Invention] According to the present invention, since the gate insulating film is composed of two layers of insulating films formed by different methods, pinholes can be reduced and yield can be improved.
第１図はこの発明の実施例のトランジスタの一製造段階
における断面図、第２図は陽極酸化処理槽の斜視図、第
３図はさらに他の製造段階における断面図、第４図はこ
の発明の他の実施例の製造工程における断面図、第５図
〜第９図は従来例を製造工程を追って示す断面図である
。
２４・・・第１の絶縁膜
２５・・・第２の絶縁膜
３２・・・第１の絶縁膜
３３・・・第２の絶縁膜
以上Fig. 1 is a sectional view of a transistor according to an embodiment of the present invention at one manufacturing stage, Fig. 2 is a perspective view of an anodizing tank, Fig. 3 is a sectional view at another manufacturing stage, and Fig. 4 is a sectional view of the invention. 5 to 9 are cross-sectional views showing the manufacturing process of the conventional example. 24...First insulating film 25...Second insulating film 32...First insulating film 33...Second insulating film or higher
Claims (1)
層よりなることを特徴とする電界効果型薄膜トランジス
タ。A field effect thin film transistor characterized in that a gate insulating film is composed of two insulating layers formed by different methods.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16748486A JPS63126277A (en) | 1986-07-16 | 1986-07-16 | Field effect thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16748486A JPS63126277A (en) | 1986-07-16 | 1986-07-16 | Field effect thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63126277A true JPS63126277A (en) | 1988-05-30 |
Family
ID=15850537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16748486A Pending JPS63126277A (en) | 1986-07-16 | 1986-07-16 | Field effect thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63126277A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6147375A (en) * | 1992-02-05 | 2000-11-14 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device |
| US6331723B1 (en) | 1991-08-26 | 2001-12-18 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device having at least two transistors having LDD region in one pixel |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57153427A (en) * | 1981-03-17 | 1982-09-22 | Fujitsu Ltd | Manufacture of thin film device |
| JPS58147069A (en) * | 1982-02-25 | 1983-09-01 | Sharp Corp | Thin film transistor |
| JPS58182270A (en) * | 1982-04-16 | 1983-10-25 | Sanyo Electric Co Ltd | Manufacture of transistor |
| JPS598376A (en) * | 1982-07-06 | 1984-01-17 | Sanyo Electric Co Ltd | Manufacture of transistor |
| JPS5986266A (en) * | 1982-11-09 | 1984-05-18 | Ise Electronics Corp | Thin film transistor and manufacture thereof |
| JPS59100572A (en) * | 1982-11-30 | 1984-06-09 | Sharp Corp | Thin film transistor |
| JPS6086863A (en) * | 1983-10-19 | 1985-05-16 | Fujitsu Ltd | Insulating gate type thin film transistor |
| JPS60244071A (en) * | 1984-05-18 | 1985-12-03 | Fujitsu Ltd | Manufacture of matrix array |
-
1986
- 1986-07-16 JP JP16748486A patent/JPS63126277A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57153427A (en) * | 1981-03-17 | 1982-09-22 | Fujitsu Ltd | Manufacture of thin film device |
| JPS58147069A (en) * | 1982-02-25 | 1983-09-01 | Sharp Corp | Thin film transistor |
| JPS58182270A (en) * | 1982-04-16 | 1983-10-25 | Sanyo Electric Co Ltd | Manufacture of transistor |
| JPS598376A (en) * | 1982-07-06 | 1984-01-17 | Sanyo Electric Co Ltd | Manufacture of transistor |
| JPS5986266A (en) * | 1982-11-09 | 1984-05-18 | Ise Electronics Corp | Thin film transistor and manufacture thereof |
| JPS59100572A (en) * | 1982-11-30 | 1984-06-09 | Sharp Corp | Thin film transistor |
| JPS6086863A (en) * | 1983-10-19 | 1985-05-16 | Fujitsu Ltd | Insulating gate type thin film transistor |
| JPS60244071A (en) * | 1984-05-18 | 1985-12-03 | Fujitsu Ltd | Manufacture of matrix array |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6331723B1 (en) | 1991-08-26 | 2001-12-18 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device having at least two transistors having LDD region in one pixel |
| US6147375A (en) * | 1992-02-05 | 2000-11-14 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device |
| US6476447B1 (en) | 1992-02-05 | 2002-11-05 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device including a transistor |
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