JPS63126024A - Microcomputer - Google Patents

Abstract

PURPOSE:To reduce the load of soft to input key return data by synchronously accessing an address decoder and a key returning input port. CONSTITUTION:When a right switch on the key returning input port 10 is depressed, key return data corresponding to the kind of the depressed key are generated every generation of a pulse T0, inputted to a key return data writing buffer circuit 11 and outputted to a RAM 6. Since the MD2(0) of the RAM 6 is always specified as an address at the timing T0, the key return data are always inputted to the MD2(0). When a key indicating the succeeding digit is depressed, the key return data are generated at a timing T1 and the key return data are similarly stored in the MD2(1) of the RAM 6. Thus, the key return data are automatically stored in the RAM 6.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a microcomputer, and more particularly to a microcomputer incorporating an automatic display control circuit (hereinafter referred to as a display controller).

(B) Prior Art In a microcomputer incorporating a conventional display controller, a digit signal is output regardless of the main routine of the program, so digit key scanning cannot be easily performed.

In order to solve this problem, a method is used in which each digit is interrupted using a digit signal as an interrupt source, and key return data is stored in an internal register by an input command for each interrupt.

(c) Problems to be Solved by the Invention However, according to this method, problems arise, such as an increase in the frequency of interruptions, complicating processing, and increasing the burden on software.

The present invention was created in view of such conventional problems, and an object of the present invention is to provide a microcomputer that can be used to input key return data while reducing the burden on software.

(d) Means for Solving the Problems The microcomputer of the present invention includes a timing controller that sequentially and periodically outputs numbered control signals, and a timing controller that is accessed by the control signals and has a number of control signals. an address decoder that outputs an address designation signal corresponding to the control signal in synchronization with the control signal; a key return input port that is accessed by the control signal and generates key return data in synchronization with the control signal number; 1/
A key return data storage RAM that stores the key return data in a storage area designated by a service designation signal.
It is characterized by having the following.

(Tree) Effect According to the present invention, the at-first decoder and the key return input port are synchronously accessed by the numbered control signals output from the timing controller.

This allows the input port for key return to synchronize with the control signal of a specific number. key return data is generated. In addition, since the address decoder outputs an at1nos designation signal corresponding to that number in synchronization, the key return data is stored in a predetermined data storage area of the key return data storage RAM designated by the address designation signal. successfully stored.

(F) Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a microcomputer according to an embodiment of the present invention.

In the figure, the area to the right of A-A' shows the automatic display control circuit that is also built in conventional microcomputers, and the area to the left of A-A' shows the key return data added according to the present invention. This is a control circuit that enables automatic storage of data without using a program.

(1) is a timing controller, which has an n-bit counter (2) and key return data write control logic (3). An output signal (a) corresponding to the count number is output from the n-bit counter (1) to the atto-s decoder (4) at regular intervals.Also, the key return data write control logic (3) outputs an output signal (a) corresponding to the count number. As shown in the timing chart of FIG. 2, the key return data write control signal (KYRDEN) (b) is activated at a constant cycle by the key return data write buffer circuit (1).
is output to .

The address decoder (4) is controlled by the (a) signal, and the (
a) Number of signals (corresponding address designation signal (e) is output to display RAM (5), key return data storage RAM (6), and timing modulator (7). (7) is a timing modulator; , the digit signal (e) (T, ~Tm-) is controlled by the blanking control signal (d) output from the timing controller (1) so as to be synchronized with the segment signal f input to the segment board (9). , ) is output. (8) is a digit port of the display, and each digit (0, 1 to m-1 digits) is scanned at a constant cycle by the digit signal (e).

(5) is a display RAM, and each data storage area (MDI) stores segment data corresponding to each digit (digit I~). (9) is a segment port of the display, into which the segment signal (f) output from the display RAM (5) is input.

(]0> is a key return user capo-1-, which automatically detects the digit of the key pressed by the operator by scanning it using the digit signal (T0 to TJ-1) mentioned above. Key return data corresponding to the type (0 to -
1) will occur. (11,) is a key data write buffer circuit, which writes the key return data so that the key return data is stored in a predetermined data storage area of RAM (6) specified by the address designation signal (e). The key return data is output to the RAM (6) in synchronization with the control signal (b).

Figure 3 is a factor 1 for specifically explaining the embodiment of the present invention.
, (1,0> is the input boat for key return, (
12) is a display device comprising a digit boat (8) and a segment boat. As shown in the figure, the input board (10) for gee return has 4 x 7 keys, 7 digit signals (T, ~T,) and 8 segment signals (S
, ~S,).

Next, embodiments of the present invention will be described with reference to FIGS. 1 to 3. By operating the n-bit counter (2), the timing controller (1) outputs a signal (a) corresponding to the count number to the address decoder (4).Thereby, the address decoder (4) outputs the signal (a) corresponding to the count number. An address designation signal (C) is output in synchronization with a).

The timing modulator (7) receives the addressing signal (c
) is output. This digit signal (e) scans the digit line of the key return input port (10).

Suppose that the operator now presses the key return input board (10> switch (shown in a perspective view) shown in Figure 3. At this time, the pressing time is shorter than the scan time, so this T, Each time a pulse occurs,
Key return data corresponding to the type of key pressed is generated and input to the key return data write buffer circuit (11), and is output from the buffer circuit (11) to the RAM (6) by the signal (b). Since M D 2 (0) of RAM (6) is always addressed at timing T, the key return data is always input here.

Assume that the next digit key (the key connected to TI) is then pressed. In this case, key return data is generated at timing T, and at that timing, RAM (6
) M D 2 (1) is specified.

Therefore, the key return data is stored successfully. In this way, key return data corresponding to the type of key pressed by the operator can be automatically stored in the RAM (6).

As described above, according to the embodiment of the present invention, the conventional display controller (the right side of A-A' in FIG. 1) includes a key return data storage RAM (6) and a key return control logic (3).

Key return buffer write buffer circuit (11).

By adding the key return input board (10), the key return data generated by the key return input board (10) can be automatically transferred to the RAM (6) without going through programs such as interrupts. can. Therefore, when input data is required, the CPU can read data from the RAM at high speed via the internal data bus, and can perform high-speed data processing.

(G) As described in detail, according to the present invention, data input at any time via a key return input port can be automatically stored in the memory of a microcomputer without any program processing. . This reduces the burden on the software, and the CPU can read data from the memory at high speed when necessary, making it possible to speed up data processing.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a microcomputer according to an embodiment of the present invention, Fig. 2 is a timing chart for explaining the operation of the embodiment, and Fig. 3 shows the embodiment of the invention more specifically. It is a figure for explaining. (1)...timing controller, (2)...n
Bit counter, (3)...Key return control logic, (4)...Address decoder, (5).
... RAM for display, (6) ... RAM for storing key return data, (7) ... Timing modulator, (8) ... Digit board, (9) ...
・Segment boat, (10)...Input boat for key return, (11)...Key return data write buffer circuit, (12)...Display device, (a)
...output signal of n-bit counter 2, (b)...
・Key return data write control signal, (c)...
Address designation signal, (d)...blanking control signal, (e)...digit signal, (f)...segment signal. Applicant: Sanyo Electric Co., Ltd. and one other agent Patent attorney: Takuji Nishino and one other person Figure 1

Claims (1)

[Scope of Claims] A timing controller that sequentially and periodically outputs numbered control signals; and a timing controller that synchronizes with the control signal an addressing signal accessed by the control signal and corresponding to the number of the control signal. an address decoder that outputs key return data; a key return input port that is accessed by the control signal and generates key return data in synchronization with the control signal; A microcomputer comprising a RAM for storing key return data.