JPH03164824A - Scanning device - Google Patents

Abstract

PURPOSE:To prevent potential data at points in a circuit to be detected from being missed during interruption by ignoring software to send a select signal by a CPU and detecting potential data. CONSTITUTION:A CPU 16 is provided which is connected to rows or columns of a circuit 24 to be detected and succesively sends the select signal to a selecting part 22 at a certain timing independently of software at the time of input of an access signal from access signal generating parts 18 and 20 and reads in potential data at each point included in the row or the column selected by the selecting part 22. Since the CPU 16 ignores software to send the select signal to the selecting part 22 by the access signal and can detect potential data, detection is not interrupted though interrupt is caused. Potential data in one preceding cycle and that of next one cycle are stored in a storage part 30, and they are compared with each other to detect the point where potential data is changed. Thus, misdetection of the change of potential data at points in the circuit 24 to be detected is prevented.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a scanning device.

(Prior Art) For example, in an electronic typewriter (see FIG. 3), a scanning device is provided to check the presence or absence of human keystrokes from the keyboard 12. keyboard 12
Each key 14... has a contact at a point designated by a row and column of a circuit to be detected (not shown) wired in a matrix, and the contact is placed while the scanning device is monitoring. If there is a change in the potential at the point corresponding to the contact due to opening/closing, there is a key force and it is possible to know which key 14... has been pressed. Conventional scanning devices are controlled by software.For example, they detect potential data at all points included in a row or column of a circuit to be detected, and perform the same detection on the next row or column. One cycle of detection ends when all rows or columns (that is, all points) are detected. Scanning (detection of potential data) is performed in this way, and all of this operation is controlled by software. Note that after the completion of one cycle of scanning, a second cycle of scanning is performed, and potential data at all points is compared between the previous one cycle and the next one cycle. During the next cycle, any key 14...
When the key 14 is pressed, a change occurs in the potential data, so the grounding point, that is, the pressed key 14, can be determined from the point where the change occurs.

(Problems to be Solved by the Invention) However, the conventional scanning device described above has the following problems.

If scanning is controlled solely by software, if an interrupt occurs, such as when the motor for moving the carrier is driven in the case of an electronic typewriter, scanning will be performed for the time required to process the motor drive. There will be no. As a result, one cycle of scanning takes an extra time. Therefore, one cycle of scanning takes a long time, and if there is a key human power during the time when scanning is not performed, it will not be detected and a typo will occur.

Therefore, an object of the present invention is to provide a scanning device that can prevent errors in detecting changes in potential data at points within a circuit to be detected.

(Means for solving problems) In order to solve the above problems, the present invention includes the following configuration.

That is, in a scanning device that sequentially detects potential data in row or column units at points designated by rows and columns of a detected circuit wired in a matrix, an access signal generation section that generates an access signal at a predetermined timing is used. a selection unit connected to the row or column of the circuit to be detected and sequentially selecting a row or column for detecting potential data as selection signals are sequentially input; and a selection unit connected to the column or row of the circuit to be detected; When the access signal is input from the access signal generation section, the selection signal is sequentially sent to the selection section at a constant timing regardless of software, and the selection section generates potential data at each point included in the selected row or column. Load C
If it is possible to determine a point where there is a change in potential data, the scanning device may include a storage unit that stores the potential data read by the CPU independently of software. In addition, the CPU has previously read potential data of all points into the storage section! The present invention is characterized in that potential data for a cycle and potential data for one cycle immediately after the cycle are stored, and a potential change point in the circuit under test is determined by comparing the two.

(effect) The effect will be explained.

The access signal causes the CPU to ignore the software and send a selection signal to the selection section, enabling detection of potential data, so even if an interrupt occurs, detection will not be interrupted, so changes in potential data will not be overlooked. By storing the potential data for one previous cycle and the potential data for the next one cycle in the storage section and comparing the two, it is possible to detect a point where the potential data has changed.

(Embodiments) Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In this embodiment, a scanning device incorporated into an electronic typewriter 10 for detecting which key 14 on the keyboard 12 of the electronic typewriter (see FIG. 3) is pressed will be described as an example.

FIG. 1 shows a circuit diagram of the scanning device of this embodiment.

16 is a CPU (Central Process
ng Llnit), which is a microprocessor that controls the electronic typewriter 10. This CPU6 has DMA (Direct Me+5ory Accesses)
s) Functions are provided.

The DMA function is a function that allows access such as reading and writing to the storage section (described later) when an access signal instructing DMA is input, regardless of software. Even if an interrupt enters the CPU 16, the hardware will not This allows access to the storage section. It goes without saying that even if the CPU does not have a DMA function, it may be connected to a circuit that has a DMA function to provide the CPU with a DMA function.

18 is a frequency dividing circuit, which receives the clock pulse of the CPU 16 (
For example, a pulse interval of 163 nanoseconds is divided appropriately to output a frequency-divided pulse (for example, a pulse interval of 2 milliseconds).

Reference numeral 20 denotes a pulse generating circuit composed of a flip-flop, which operates using the output Q of the frequency dividing circuit 18 as a clock pulse. The pulse generating circuit 20 outputs an output Q (output o- pulse) as a trigger pulse (eg, pulse width 1 microsecond) at a predetermined time interval (eg, 2 milliseconds). This trigger pulse becomes an access signal, and in this embodiment, the frequency dividing circuit 18 and the pulse generating circuit 20 constitute an access signal generating section. Note that it is possible to invert the output Q of the frequency divider circuit 18 and use it as an access signal, but in the case of this embodiment, the pulse interval of the output Q of the frequency divider circuit 18 is 2 milliseconds, and the Lo- time Since the pulse width is 1 millisecond, the pulse width is too long for an access signal, so a pulse generation circuit 20 is provided. Of course, the access signal generating section may have a circuit configuration in which the frequency dividing circuit 18 and the pulse signal generating circuit 20 are integrated.

22 is a shift register which is an example of a selection section, and each row of the matrix wiring of the detected circuit 24 is connected to a row terminal Q.
They are connected to O-Q, respectively.

The shift pulse of the shift register 22 is 10 of the CPU 16.
This is the output from the RD terminal, and this output is an access signal.
This is a pulse that is output from the CPUI 6 when input to the MA RQ terminal. The shift register 22 changes the row terminals Qo→Q, ...Q8→Q every time a shift pulse is input.
, apply the voltage GH (example: +5V) to each terminal one by one in this order. Note that when the shift pulse is sent 10 times (a predetermined number of times), the CPU 16's DMA EN
A low pulse is sent from the D terminal to shift register 2.
2 is cleared and then the terminal to which the old gh is applied is returned to Qo.

Incidentally, the columns Po-P of the detected circuits 24 are connected to the CPU 1 in parallel via a buffer 26 and a data bus 28 .
Connected to 6.

30 is a RAM (Random Access
ssMemory), and a storage area is allocated to include the first memory 32 and the second memo 1J34. The first memory 32 stores the currently detected circuit 2.
The potential data of column PoxP of 4 is stored as 8-bit binary data. On the other hand, the second memory 34 stores the column P of the detected circuits 24 detected immediately before the data in the first memory 32 is detected.

~P, potential data is stored as 8-bit binary data. CPUI 6(7) access to RAM 30 is enabled via pass line 36, and
The DMA function described above makes the software irrelevant (accessible) at specific timings.

The detected circuit 24 is a matrix circuit that detects the pressing of the keys 14 on the keyboard 12 of the electronic typewriter 10, and when the keys 14 are pressed, the keys 14, .
The switch 38... arranged corresponding to... is closed, and while it is closed, the row Qo to which the switch 38 belongs is closed.
-Q, when the old gh is applied, the output potential of the column PoxPt to which the switch 38 belongs becomes the old gh.

Next, the operation of the scanning device will be explained with reference to FIGS. 1 and 2.

The clock pulse of the CPU 16 is divided by the frequency dividing circuit 18,
The output Q is inputted to the pulse generation circuit 20, and the output enable is inputted to the DMA RQ terminal of the CPU 16 as an access signal. As a result, the CPU 16 becomes capable of DMA, and also outputs Lo- from the 10RD terminal and sends it to the CLK terminal of the shift register 22 as a shift pulse.

The shift register 22 first applies a voltage g to the row terminal Qo.
Apply h (example: +5v). At that time, if the key 14... of the keyboard 12 of the electronic typewriter 10 is not pressed, the key 1 corresponding to the switch 38... connected to the row wiring connected to the row terminal Qo
If 4... is not pressed, all outputs of columns Po-P become Lo%1 and are sent to CP via data bus 2B...
“oooo” to UI 6.

000" potential data is taken in, and the CPU 16
write as data So in the memory 34 of (Fig. 2(b)
)reference). However, for example, row terminal Q.

When the switch 3 connected to the column P1 is closed by pressing the corresponding key 14, the potential data taken into the CPU 16 from the data bus 28 . . . becomes So=“oiooooooo”.

Therefore, it is possible to detect which key 14 was pressed. Then, when entering the next 10 RD times signal shift register 22, the voltage old gh is applied only to the row terminal Q1.
is applied to the column Po-P, which similarly corresponds to the row terminal Q,
8-bit potential data is taken in and stored in the second memory 3.
4 to potential data S.

(see FIG. 2(b)), this operation is repeated and stored in the second memory 34 as So to S.

When the potential data of is stored, the 10■ signal of the CPU 16 has been sent 10 times, so the DMA is sent from the CPU 16.
The END signal is sent to the CLR terminal of the shift register 22, and the shift register 22 receives the next 10 RD times signals, which returns the row terminal applying High to QO, and then returns the CP
U16 writes the captured potential data as data RO to the first memory 32 (see FIG. 2(a)), and the potential data of columns PO to Py corresponding to the next row terminal Q is written as data Sl. 1 (see FIG. 2(a)), and this operation is repeated 10 times.

When 10 pieces of data are loaded into the first memory 32 and the second memory 34, the CPU 16 compares the two pieces of data, and if they match, it starts from the end of writing the data to the second memory 34. It is determined that the keys 14 . On the other hand, if both parties do not lose, press key 14 (if the data changes from 0 to 1)
, or the press has been released (when the data changes from 1 to 0), and when the CPU 16 determines that the key has been pressed, the CPU 16 performs an operation such as printing a character corresponding to the key 14 according to a predetermined program. When the comparison (judgment) is completed, the CPU 6 transfers the contents of the first memory 32 to the second memory 34, clears the first memory 32 (does not necessarily have to be cleared), and performs the next detection. The potential data is stored in the first memory 32 as data Ro-R, and the contents of the first memory 32 are again compared with the contents of the second memory 34, which is the previous data that was previously in the first memory 32. do.

By repeating this operation, the CPU 16
Scanning is performed to determine whether or not the key 14 . . . 2 has been pressed.

In the above embodiments, the scanning device is used for scanning key presses on the keyboard of an electronic typewriter, but the scanning device may also be used for scanning, for example, for detecting the presence or absence of plotting on a digitizer. It can also be used for.

Although various preferred embodiments of the present invention have been described above, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that many modifications can be made without departing from the spirit of the invention. be.

(Effects of the Invention) When the scanning device according to the present invention is used, there is no scanning delay caused by interrupts, so it is possible to prevent potential data from being overlooked at a point in the detected circuit during interruption of interrupts. becomes. Also, claim 4 or 5
If this configuration is adopted, it will be effective to prevent forgetting to detect a change in potential data at a point in the circuit to be detected.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a scanning device according to the present invention, FIG. 2 is an explanatory diagram showing the stored contents of a storage section thereof, and FIG. 3 is a perspective view of an electronic typewriter according to the embodiment. 16... CPU5 1B... Frequency dividing circuit, 20... Pulse generation circuit, 22... Shift register, 24... Detected circuit, 30... RAM.

Claims (1)

[Claims] 1. In a scanning device that sequentially detects potential data in units of rows or columns at points specified by rows and columns of a circuit to be detected wired in a matrix, an access signal is sent at a predetermined timing. an access signal generation section that generates an access signal; a selection section that is connected to the row or column of the circuit to be detected and that sequentially selects a row or column for detecting potential data as selection signals are sequentially input; and a column of the circuit to be detected. or connected to a row, and when the access signal is input from the access signal generation section, the selection signal is sequentially sent to the selection section at a constant timing regardless of software, and the selection signal is included in the row or column selected by the selection section. A scanning device comprising a CPU that reads potential data at each point. 2. The access signal generating section is characterized by comprising a frequency dividing circuit that divides the frequency of the clock signal of the CPU, and a pulse generating circuit that sends an access signal to the CPU in synchronization with the timing of the output of the frequency dividing circuit. The scanning device according to claim 1. 3. The scanning device according to claim 1 or 2, wherein the selection section is a shift register, and the selection signal is a shift pulse sent from the CPU. 4. The scanning device according to claim 1, 2 or 3, further comprising a storage unit that stores the potential data read by the CPU independently of software. 5. The CPU stores in the storage section one cycle's worth of potential data, which is the potential data of all the points previously read, and one cycle's worth of potential data immediately after the cycle, and compares the two. 5. The scanning device according to claim 4, further comprising determining a potential change point in the circuit under test.