JPS63124440A - Methode of operation analysis of semiconductor device - Google Patents
Methode of operation analysis of semiconductor deviceInfo
- Publication number
- JPS63124440A JPS63124440A JP61270283A JP27028386A JPS63124440A JP S63124440 A JPS63124440 A JP S63124440A JP 61270283 A JP61270283 A JP 61270283A JP 27028386 A JP27028386 A JP 27028386A JP S63124440 A JPS63124440 A JP S63124440A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- electron beam
- semiconductor device
- resist
- operation analysis
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004458 analytical method Methods 0.000 title claims abstract description 22
- 238000010894 electron beam technology Methods 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000007789 sealing Methods 0.000 claims abstract description 5
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 238000005259 measurement Methods 0.000 abstract description 14
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 239000002184 metal Substances 0.000 abstract description 8
- 239000011347 resin Substances 0.000 abstract description 5
- 229920005989 resin Polymers 0.000 abstract description 5
- 230000008878 coupling Effects 0.000 abstract description 2
- 238000010168 coupling process Methods 0.000 abstract description 2
- 238000005859 coupling reaction Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- NTIZESTWPVYFNL-UHFFFAOYSA-N Methyl isobutyl ketone Chemical compound CC(C)CC(C)=O NTIZESTWPVYFNL-UHFFFAOYSA-N 0.000 description 1
- UIHCLUNTQKBZGK-UHFFFAOYSA-N Methyl isobutyl ketone Natural products CCC(C)C(C)=O UIHCLUNTQKBZGK-UHFFFAOYSA-N 0.000 description 1
- 229920002319 Poly(methyl acrylate) Polymers 0.000 description 1
- XSTXAVWGXDQKEL-UHFFFAOYSA-N Trichloroethylene Chemical group ClC=C(Cl)Cl XSTXAVWGXDQKEL-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 239000004926 polymethyl methacrylate Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、対土成形までがなされ、製品として完成した
半導体装置を再度開封し、その動作解析を行う方法に関
する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for re-opening a semiconductor device that has been completed as a product, including soil molding, and analyzing its operation.
従来の技術
超LSIで代表される高積積度の半導体集積回路では、
パターンの微細化、配線の多層構造化が進んでいる。特
に、多層配線構造の半導体集積口2 ベ−i
路では、絶縁膜の下側に配線層が位置するところとなる
。Conventional technologyIn high-density semiconductor integrated circuits represented by VLSI,
Patterns are becoming finer and wiring is becoming more multilayered. Particularly, in the semiconductor integration port 2 of the multilayer wiring structure, the wiring layer is located below the insulating film.
ところで、このような構造とされた半導体集積回路の動
作解析、特に、不良解析に際しては、絶縁膜の下側に配
置された配線層の電位波形の測定が必要であるが、通常
用いられている金属探針によっては電位波形の測定が困
難である。By the way, when analyzing the operation of a semiconductor integrated circuit with such a structure, especially when analyzing failures, it is necessary to measure the potential waveform of the wiring layer placed under the insulating film. It is difficult to measure potential waveforms depending on the metal probe.
この金属探針を用いる測定装置にかわり、電子ビームを
用いる測定装置が使用されるに至っている。Measuring devices that use electron beams have come to be used instead of measuring devices that use metal probes.
この測定装置による測定は、半導体集積回路基板上の動
作解析点に電子ビームを照射し、この部分から発生する
2次電子により、動作解析点に位置する配線層の電位波
形を測定する方法である。Measurement using this measuring device is a method in which an electron beam is irradiated to a motion analysis point on a semiconductor integrated circuit board, and the potential waveform of the wiring layer located at the motion analysis point is measured using secondary electrons generated from this portion. .
発明が解決しようとする問題点
しかしながら、動作解析の対象とされた半導体集積回路
が多層配線構造のものであると、配線層上を覆う絶縁膜
の帯電現象によって電位コントラストが低下するところ
となシ、高い精度の測定結果を得ることは困難であった
。特に、不良解析等J ベージ
においてこの動作解析がなされることは既に説明したと
ころであるが、不良解析の対象となる半導体集積回路は
、通常、封止成形までがなされたものである。したがっ
て、樹脂等の封止外囲体を取り除いて露出させた半導体
集積回路基板の面状態は絶縁膜で覆われた状態となシ、
このままの状態で動作解析を行っても良好な測定結果を
得ることはできなかった。Problems to be Solved by the Invention However, if the semiconductor integrated circuit targeted for operation analysis has a multilayer wiring structure, the potential contrast may decrease due to the charging phenomenon of the insulating film covering the wiring layer. However, it was difficult to obtain highly accurate measurement results. In particular, it has already been explained that this operation analysis is performed in the J-page, such as failure analysis, but the semiconductor integrated circuit that is the target of failure analysis is usually one that has been subjected to sealing molding. Therefore, the surface of the semiconductor integrated circuit board exposed by removing the sealing envelope made of resin or the like is not covered with an insulating film.
Even if we performed a motion analysis in this state, it was not possible to obtain good measurement results.
問題点を解決するための手段
本発明は、このような問題点を排除することができる動
作解析方法の提供を目的としてなされたもので、動作解
析の対象となる半導体装置の封止外囲体を取シ除き、半
導体基板を露出させたのち、動作解析点となる半導体基
板部分を覆う絶縁膜上に電位波形測定用電極を形成し、
こののち、この電位波形測定用電極部を電子ビームで照
射することを特徴とする方法である。Means for Solving the Problems The present invention has been made for the purpose of providing an operation analysis method that can eliminate such problems, and is intended to provide a method for analyzing the operation of a semiconductor device, which is an object of operation analysis. After removing the semiconductor substrate and exposing the semiconductor substrate, electrodes for measuring potential waveforms are formed on the insulating film covering the part of the semiconductor substrate that will be the point of operation analysis.
This method is characterized in that the potential waveform measurement electrode section is then irradiated with an electron beam.
作用
この発明の方法によれば、電位波形測定用電極に金属配
線層の電位変化があられれ、絶縁膜の影響が除かれる〇
実施例
以下に図面を参照して本発明にかかる半導体装置の動作
解析法について説明する。Operation According to the method of the present invention, the potential change of the metal wiring layer is applied to the potential waveform measuring electrode, and the influence of the insulating film is eliminated.Examples The operation of the semiconductor device according to the present invention will be described below with reference to the drawings. The analysis method will be explained.
(以 下 余 白 )
ぺ2ページ
第1図〜第5図は、動作対象となる半導体装置に電位波
形測定用電極が形成され、電位波形の測定がなされるに
至るまでの状態を示した要部の拡大断面図である。(Margins below) Figures 1 to 5 on page 2 show the main points of the process from the formation of potential waveform measurement electrodes on a semiconductor device to be operated to the measurement of potential waveforms. FIG.
第1図は、動作解析の対象となる樹脂封止形半導体装置
の部分拡大断面図であシ、基板支持体1の上に固着され
た半導体基板、例えば、シリコン基板2の表面を覆う二
酸化シリコン膜3の上に金属配線層゛4が形成され、さ
らにこの上が絶縁膜5で覆われた半導体素子が樹脂6で
封止された構造となっている。FIG. 1 is a partially enlarged sectional view of a resin-sealed semiconductor device to be subjected to operation analysis. A metal wiring layer 4 is formed on the film 3, and a semiconductor element whose top is covered with an insulating film 5 is sealed with a resin 6.
この半導体装置の封止外囲体である樹脂を取り除いて半
導体素子の表面を露出させたのち1電子ビーム用ポジ型
レジストとして、ポリメチルクリレート(PMMA )
を0.6μmの膜厚となるように回転塗布法で塗布し、
さらに170’Cの温度で30分間にわたるレジストベ
ーク処理を施す。After removing the resin that is the sealing envelope of this semiconductor device and exposing the surface of the semiconductor element, polymethyl acrylate (PMMA) was used as a positive resist for electron beams.
was applied using a spin coating method to a film thickness of 0.6 μm,
Further, a resist bake treatment is performed at a temperature of 170'C for 30 minutes.
第2図は、この処理の後の状態を示す図であシ、図示す
るように表面全域が電子ビーム用ポジ型レジストアによ
って被覆された構造となる。この後、6 ベーク
電子ビーム露光装置に半導体装置を配置し1電子ビーム
8で所定の箇所、すなわち、動作解析点部分に位置する
電子ビーム用ポジ型レジスト部分を直接露光したのち、
半導体装置を電子ビーム露光装置から取シ出し、メチル
イソブチルケトン(MXBK)で60秒間の現像処理を
施し、さらに1120°Cの温度で30分間にわたるポ
ストベーク処理を施す。FIG. 2 is a diagram showing the state after this processing, and as shown in the figure, the entire surface is covered with a positive resist for electron beams. After this, the semiconductor device is placed in a 6-bake electron beam exposure device, and a predetermined location, that is, a positive resist portion for the electron beam located at the motion analysis point is directly exposed with the 1 electron beam 8.
The semiconductor device is taken out from the electron beam exposure apparatus, developed with methyl isobutyl ketone (MXBK) for 60 seconds, and then post-baked at a temperature of 1120° C. for 30 minutes.
第3図は、ポストベーク処理後の状態を示す図であシ、
電子ビームによる直接露光が施された部分に開口9が形
成される。FIG. 3 is a diagram showing the state after post-baking treatment;
An opening 9 is formed in the portion directly exposed by the electron beam.
次いで、第4図で示すように、アルミニウムの抵抗加熱
蒸着によって0.2μmの膜厚のアルミニウム層10を
形成する。このようにして形成したアルミニウム層は、
開口内に形成された部分と電子ビーム用ポジ型レジスト
上に形成された部分とが分断された状態、もしくは、こ
れに近い状態を呈する。Next, as shown in FIG. 4, an aluminum layer 10 having a thickness of 0.2 μm is formed by resistance heating vapor deposition of aluminum. The aluminum layer formed in this way is
The portion formed within the opening and the portion formed on the positive resist for electron beams exhibit a separated state, or a state close to this.
以上の処理を経た半導体素子をトリクロルエチレンでボ
イルし、電子ビーム用ポジ型レジスト77 へ−・
を除去すると1この上に形成されたアルミニウム層部分
も同時に取シ去られ、開口内に形成されたアルミニウム
層部分のみが絶縁膜5の上に残シ。When the semiconductor element subjected to the above processing is boiled with trichlorethylene and the positive resist for electron beam 77 is removed, the aluminum layer formed on it is also removed at the same time, and the aluminum layer formed in the opening is removed. Only the aluminum layer portion remains on the insulating film 5.
第5図で示す電位波形測定用電極11が形成される。The potential waveform measuring electrode 11 shown in FIG. 5 is formed.
このようにして形成された電位波形測定用電極11は、
この下側に位置する金属配線層4と容量結合する関係に
あるため、金属配線層4の電位変化が電位波形測定用電
極にあられれる。したがって、この電極を電子ビームで
照射し、この部分から発生する2次電子を測定すること
により動作解析がなされる。The potential waveform measurement electrode 11 formed in this way is
Since there is a capacitive coupling relationship with the metal wiring layer 4 located below, potential changes in the metal wiring layer 4 are applied to the potential waveform measuring electrode. Therefore, the operation is analyzed by irradiating this electrode with an electron beam and measuring the secondary electrons generated from this part.
以上の説明では1電位波形測定用電極を1箇所に形成す
る場合を例示しだが、動作解析点の数に対応させて形成
すればよく、特に数の制限はない。In the above description, the case where one potential waveform measurement electrode is formed at one location is exemplified, but the electrodes may be formed in correspondence with the number of motion analysis points, and the number is not particularly limited.
また、動作解析の対象となる半導体装置も半導体集積回
路に限られるものではない。Further, the semiconductor device to be subjected to operation analysis is not limited to semiconductor integrated circuits.
発明の効果
本発明によれば、電位コントラストが低下することのな
い状態で測定がなされるため、高い測定精度を得ること
ができ、正確な動作解析を可能にする効果が奏される。Effects of the Invention According to the present invention, since measurement is performed in a state where the potential contrast does not deteriorate, high measurement accuracy can be obtained, and the effect of enabling accurate motion analysis is achieved.
第1図〜第5図は、本発明の動作解析方法の下で電位波
形の測定がなされるに至るまでの状態を示す半導体装置
の要部の拡大断面図である。
1・・・・・・基板支持体、2・・・・・・シリコン基
板、3・・・・・・二酸化シリコン膜14・・・・・・
金属配線層、6・・・・・・絶縁膜、6・・・・・・樹
脂、7・・・・・・電子ビーム用ポジ型しジスl−,8
,12・・・・電子ビーム、9・・・・・・開口、10
°°゛・・・アルミニウム層、11・・・・・・電位波
形測定用電極。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名襄口
;> ご
−八
龜 区
I
CN】
の
塚 塚1 to 5 are enlarged cross-sectional views of essential parts of a semiconductor device showing the state up to the measurement of a potential waveform under the operation analysis method of the present invention. 1...Substrate support body, 2...Silicon substrate, 3...Silicon dioxide film 14...
Metal wiring layer, 6... Insulating film, 6... Resin, 7... Positive type resistor for electron beam l-, 8
, 12...Electron beam, 9...Aperture, 10
°°゛... Aluminum layer, 11... Electrode for potential waveform measurement. Name of agent Patent attorney Toshio Nakao and one other person
Claims (1)
半導体基板を露出させたのち、動作解析点となる半導体
基板部分を覆う絶縁膜上に電位波形測定用電極を形成し
、次いで、同電位波形測定用電極を電子ビームで照射し
、発生する2次電子を測定することを特徴とする半導体
装置の動作解析方法。After removing the sealing envelope of the semiconductor device to be subjected to operation analysis and exposing the semiconductor substrate, electrodes for measuring potential waveforms are formed on the insulating film covering the part of the semiconductor substrate that will be the operation analysis point. A method for analyzing the operation of a semiconductor device, which comprises irradiating an electrode for measuring a potential waveform with an electron beam and measuring generated secondary electrons.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61270283A JPS63124440A (en) | 1986-11-13 | 1986-11-13 | Methode of operation analysis of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61270283A JPS63124440A (en) | 1986-11-13 | 1986-11-13 | Methode of operation analysis of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63124440A true JPS63124440A (en) | 1988-05-27 |
Family
ID=17484099
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61270283A Pending JPS63124440A (en) | 1986-11-13 | 1986-11-13 | Methode of operation analysis of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63124440A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10766431B2 (en) | 2014-06-26 | 2020-09-08 | Kyocera Corporation | Imaging apparatus and vehicle |
-
1986
- 1986-11-13 JP JP61270283A patent/JPS63124440A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10766431B2 (en) | 2014-06-26 | 2020-09-08 | Kyocera Corporation | Imaging apparatus and vehicle |
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