JPS5870530A - Resist pattern formation - Google Patents

Resist pattern formation

Info

Publication number
JPS5870530A
JPS5870530A JP16897781A JP16897781A JPS5870530A JP S5870530 A JPS5870530 A JP S5870530A JP 16897781 A JP16897781 A JP 16897781A JP 16897781 A JP16897781 A JP 16897781A JP S5870530 A JPS5870530 A JP S5870530A
Authority
JP
Japan
Prior art keywords
pattern
development
resist
resist film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16897781A
Other languages
Japanese (ja)
Inventor
Makoto Yoshimi
信 吉見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16897781A priority Critical patent/JPS5870530A/en
Publication of JPS5870530A publication Critical patent/JPS5870530A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26Processing photosensitive materials; Apparatus therefor
    • G03F7/30Imagewise removal using liquid means

Abstract

PURPOSE:To control development hours based on the intensity information and to form a pattern with high accuracy by a method wherein a developing pattern is exposed to the monitor regions of a resit film and an electromagnetic wave is aimed at the regions at the time of a development process and the penetrated electromagnetic wave is detected. CONSTITUTION:Three kinds of patterns as developing patterns are exposed with equal areas to the minotr regions 3a-3c of a resisit film 3 on a substrate 1 before development. The region 3a is formed as the pattern permitting the exposure of all processed substances and the region 3b is formed as the pattern covered all the revese of the processed substance with a resist and the pattern having the same kind of width as that of a fine pattern on the substrate 1 is formed on the region 3c. An electromagnetic wave such as infrared rays is aimed at the respective regions through a mask 7 and the intensity of the infrared rays detectors 8a-8c and developing hours are controlled based on the value detected by the respective detectors 8a-8c at the developing process for the substrate 1 and the fine pattern of the substrate 1 is developed with high accuracy.

Description

【発明の詳細な説明】 本発明は、レジストパターン形成方法に係わシ、特に現
像工程時の寸法制御の高精度化をはかったレジストパタ
ーン形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a resist pattern, and particularly to a method for forming a resist pattern in which dimensional control during a development process is highly accurate.

近時、集積回路の高密度化は著しく′、素子を形成する
パターンの寸法は1〔μ諺〕或い社すプ電タロンκなろ
うとしている.かかる微細パターン形成は、第1図←)
に示す如く基板l上に形成し九被加工物2上にざらにレ
ジス}y!jlk布形成し、このレジスト膜Sに所望の
パターンに従って光、電子線或いはX線等のエネルギ線
を照射し、その後同図(b)に示す如く現像処理を行い
レジストパターン4を形成する.次いで、上記残ったレ
ジスト膜3をマスクとして被加工物2をエツチング、つ
まシ食刻法によシ被加工物2にレジストパターン4を転
写して行われている。
In recent years, the density of integrated circuits has increased significantly, and the dimensions of the patterns that form the elements are about to become as small as 1 [mu] or the size of an electronic circuit. Such fine pattern formation is shown in Figure 1←)
As shown in FIG. 9, a resist is formed on the substrate l and roughly formed on the workpiece 2}y! This resist film S is irradiated with energy beams such as light, electron beams, or X-rays in accordance with a desired pattern, and then developed as shown in FIG. 4B to form a resist pattern 4. Next, the workpiece 2 is etched using the remaining resist film 3 as a mask, and the resist pattern 4 is transferred onto the workpiece 2 by a pick etching method.

しかしながら、この種の方法にあっては次のような間融
があった。すなわち、レジストパターンの形成に゛際し
、露光は極めて精度良く行えるが、現像によるパターン
の寸法制御性は患いものである。このため、現像時にレ
ジストパターン4を光学顕微鏡で観察しながら現像時間
を制御するようにしている。しかし、光学顕微%の解像
度以下である1 (11m)或いはサプンクロンのパタ
ーンに対しては、パターンのエツジが不鮮明となり、正
確な寸法測定が困難であった。
However, this type of method has the following problems. That is, when forming a resist pattern, exposure can be carried out with extremely high precision, but the dimensional controllability of the pattern by development is difficult. For this reason, the development time is controlled while observing the resist pattern 4 with an optical microscope during development. However, for patterns of 1 (11 m) or Sapunchron whose resolution is less than that of an optical microscope, the edges of the patterns become unclear, making it difficult to accurately measure dimensions.

その結果正確な寸法制御が困難となシ、これがために微
−なパターンを高精度に形成することはできなかった。
As a result, accurate dimensional control is difficult, and for this reason, fine patterns cannot be formed with high precision.

本発明は上記事情を考慮してなされたもので、その目的
とするところは、レジスト膜の現像時におけるパターン
寸法制御性の向上をはかbiで、微細パターンを高精度
に形成することのでKある。
The present invention has been made in consideration of the above circumstances, and its purpose is to improve pattern size controllability during development of a resist film and to form fine patterns with high precision. be.

まず、本発明の詳細な説明する。本発明は、被加工物上
にレジスト膜を塗布形成し′たのちレジスト膜を結党・
現像して所望のレジストパターンを形成する方法におい
て、現潅工椙前に上記レジスト膜のモニタ領域に現像モ
ニタ用パターンを露光し、現鍛工程時に上記モニタ領域
に電磁波を照射して上記モニタ領域を透過した電磁波の
強度を検出し、この検出情報に基づいて現酸の時間を制
御するようにした方法である。
First, the present invention will be explained in detail. In the present invention, a resist film is applied and formed on a workpiece, and then the resist film is bonded and formed.
In the method of forming a desired resist pattern by development, a development monitoring pattern is exposed on a monitor area of the resist film before the development process, and electromagnetic waves are irradiated to the monitor area during the development process to expose the monitor area. This method detects the intensity of the electromagnetic waves that have passed through it, and controls the current acid time based on this detected information.

すなわち、本発明の骨子は、現像モニタ用パターンが露
光されたモニタ領域に電磁波を照射し、その透過量から
現像パターンの寸法を測定することにある。
That is, the gist of the present invention is to irradiate an electromagnetic wave onto a monitor area where a development monitor pattern has been exposed, and to measure the dimensions of the developed pattern from the amount of the electromagnetic wave transmitted.

第2図に示す如く基板I上のレジス)[5のモニタ領域
5a、6b、5cに現像モニタ用パターンとして、3種
類のパターンを等しい面積8oにそれぞれ露光する。こ
こで、モニタ領域5aには第3図(a)に示す如く下地
の被加工物2が全て露出するパターン(全領域露光)を
、モニタ領域6bには逆に同図(b) K示す如く全て
レジストで覆われるパターン(1!光せず)を形成する
。また、モニタ領域6clCは菓子用の微−パターンと
同程度のパターン幅を有するものが規則的に並んだパタ
ーン、例えば第3図(C)に示す如く調定ピッチのライ
ンパターンを形成する。
As shown in FIG. 2, three types of patterns are exposed in equal areas 8o as development monitoring patterns in the monitor areas 5a, 6b, and 5c of the resist on the substrate I. Here, the monitor area 5a has a pattern (full area exposure) in which the underlying workpiece 2 is completely exposed as shown in FIG. 3(a), and the monitor area 6b has a pattern as shown in FIG. 3(b) K. A pattern completely covered with resist (1! No light) is formed. Further, the monitor area 6clC forms a pattern in which patterns having a pattern width comparable to that of a confectionery fine pattern are regularly lined up, for example, a line pattern with a predetermined pitch as shown in FIG. 3(C).

なお、第2図中6は素子領域を示している。Note that 6 in FIG. 2 indicates an element region.

次に、現像途中における寸法測定は、前記各モニタ領域
5a、5b、5cに元(電磁波)を照射して行うが、光
の波長λをレジスト膜3には吸収が強く被加工物質2お
よび基板IKはほとんど透過する波長領域に選べばよい
。通常のレジストは高分子材料からなシ、また基板1や
被加工物2はシリコン或いはシリコンの化合物からなる
ため、波長λをレジストの赤外吸収域に選べば、基板1
および被加工物2に対する光の透過率は略1と見做して
よい。光の単位面積当シの強度を工、レジストによる透
過の割合をα、モニタ[a域5Cにおける下地被加工物
の露出割合をtとすると、一定の時間規律した後の基板
裏面で検知される透過光量は モニタ領域6aに対し・・・・・・・・・・・・・・・
・・・I8゜モニタ領域5bに対し・・・・・・・・・
・・・・−・・・α・工・8゜モニタ領域5Cに対し−
・・・・・・・・・・・・・・・・〔tα+(x−i)
)I・80 となる。モニタ領域5Cの光量は現像が進行し、tが増
加するのに伴って増加する。ここで、パターンの設計値
によってtの理想値は予め知ることができるため、前記
3つの透過光量の比を測定し、モニタ領域5Cの透過光
量が理想値に達したとき現像を停止すれば、微細パター
ンは設計値に極めて近い値となる。PIlえば、モニタ
領域5Cの露光パターンをラインの幅と間隔とが弄しい
パターン(半分領域露光)とすれば、t=0.5であり
モニタ領域5h、lb、5cの透過光量比はそれぞれI
、α、は−となシ、各・領域5a、5b、5cから出る
透過光量は現像時間に対し第4図に示す如く変化する。
Next, dimension measurement during development is carried out by irradiating each monitor area 5a, 5b, 5c with a source (electromagnetic wave). IK should be selected in a wavelength range that is almost transparent. Ordinary resists are not made of polymer materials, and the substrate 1 and workpiece 2 are made of silicon or silicon compounds, so if the wavelength λ is chosen to be in the infrared absorption range of the resist, the substrate
The transmittance of light to the workpiece 2 can be considered to be approximately 1. Assuming that the intensity of light per unit area is α, the rate of transmission through the resist is α, and the exposure rate of the underlying workpiece in area 5C of the monitor is t, it is detected on the back side of the substrate after a certain period of time. The amount of transmitted light is for the monitor area 6a...
...For I8° monitor area 5b...
・・・・・・・・・α・Work・8゜For monitor area 5C-
・・・・・・・・・・・・・・・ [tα+(x−i)
)I・80. The amount of light in the monitor area 5C increases as development progresses and t increases. Here, since the ideal value of t can be known in advance from the design value of the pattern, if the ratio of the three amounts of transmitted light is measured and the development is stopped when the amount of transmitted light in the monitor area 5C reaches the ideal value, The fine pattern has values extremely close to the design values. For example, if the exposure pattern of the monitor area 5C is a pattern in which the width and spacing of lines are difficult (half area exposure), t=0.5, and the transmitted light amount ratio of the monitor areas 5h, lb, and 5c is I, respectively.
, .alpha., and .alpha., the amount of transmitted light emitted from each region 5a, 5b, 5c changes with development time as shown in FIG. 4.

すなわち、モニタ領域5&での透過率Aは一定時間まで
増大するが、その後は一定(1)となる。モニタ領域5
bでの透過率Bは現像時間に関係なく一定(ロ)となる
。モニタ領域5Cでの透過率Cは現像時間に伴い増大す
ることになる。そして、現像の適正時間は上記透過率C
がにとなるとき、つt#)時間Toで示される。なお、
第4図においてモニタ領域5bのレジスト塩1における
膜減シは無視したが、例え膜減シがあっても前記割合α
が時間的に多重増大するだけで現−の適正時間は全く同
様にして検知することができる。
That is, the transmittance A in the monitor area 5& increases until a certain time, but then becomes constant (1). Monitor area 5
The transmittance B at b is constant (b) regardless of the development time. The transmittance C in the monitor area 5C increases with development time. The appropriate time for development is the transmittance C
t#) is denoted by the time To. In addition,
In FIG. 4, the film reduction in the resist salt 1 in the monitor area 5b is ignored, but even if there is film reduction, the ratio α
The current proper time can be detected in exactly the same way, only by increasing the number of times.

かくして本発明によれば、レジスト膜の現慮時における
パターン寸法制御性の向上をはかり得て、従来困難であ
った1〔μm〕或いはサブ建クロンパターンの正確な制
御が可能となり、微細な素子の製作に絶大なる効果を発
揮する。
Thus, according to the present invention, it is possible to improve the pattern size controllability when actually designing a resist film, and it is now possible to accurately control 1 [μm] or sub-scale patterns, which has been difficult in the past. It is extremely effective in the production of.

以下、本発明の詳細を図示の実施例によって説明する。Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

基板Iにはシリコンウエーノ・を、被加工物2には膜厚
5000(^〕の多結晶シリコンを、レジスト膜Sには
膜厚1〔μm〕のPMMA (ポリメチルメタクリレー
ト)を用いた。次に、周知の電子線露光技術を利用し、
ウェーハの中央素子領域6に回路パターンを露光すると
共にウェーハの周辺モニタ領域la、5b、5cに前記
第3図61)〜(C)と同様なパターンをそれぞれ2〔
關雪〕の面積で露光形成した。ここで、上記回路パター
ンの最小パターン幅が0.5(#鳳〕であったのテ、モ
ニタ領域5cにはO,S(μ諷〕のライン幅と0. !
S (sll)の間隔を有するラインパターンを形成し
た。
Silicon urethane was used for the substrate I, polycrystalline silicon with a thickness of 5000 (^) was used for the workpiece 2, and PMMA (polymethyl methacrylate) with a thickness of 1 [μm] was used for the resist film S. Next, using well-known electron beam exposure technology,
A circuit pattern is exposed on the central element region 6 of the wafer, and patterns similar to those shown in FIG.
The area was formed by exposure to light. Here, although the minimum pattern width of the above circuit pattern was 0.5 (#0), the monitor area 5c has a line width of O, S (μ) and 0.!
A line pattern with an interval of S (sll) was formed.

次に、現像液としてurBx (メチルイソブチルケト
ン)を用い、一定時間の現像後、パターン幅をモニタし
ながら追加の現像を行い適正のパターン幅を得た。第5
図はこのとき使用したパターン幅モニタ装置を示す模式
図であシ、図中1は入射光(赤外光)をモ二り領域1B
IL。
Next, using urBx (methyl isobutyl ketone) as a developer, after development for a certain period of time, additional development was carried out while monitoring the pattern width to obtain an appropriate pattern width. Fifth
The figure is a schematic diagram showing the pattern width monitoring device used at this time.
IL.

13b、13cのみに照射するためのマスク、8a 、
ljb、8cは赤外線検出器である。そして、上記検出
器8a、8b、8cの各検出出力に基づいて前述した処
理を行うことによってパターン幅を等価的にモニタして
いる。なお、使用した赤外光はモニタ用パターンによっ
て強い回折を示すので、赤外線検出器8a、Ilb、8
Cを前記ウェーハの裏面に接触させて透過光をもれなく
検出できるようにした。
A mask for irradiating only 13b and 13c, 8a,
ljb and 8c are infrared detectors. The pattern width is equivalently monitored by performing the above-described processing based on the detection outputs of the detectors 8a, 8b, and 8c. Note that the infrared light used exhibits strong diffraction due to the monitoring pattern, so the infrared detectors 8a, Ilb, 8
C was brought into contact with the back surface of the wafer so that all transmitted light could be detected.

かくして形成されたレジストパターンを電子顕微鏡で観
測したところ、モニタ領域5Cのノ(ターンのツイン幅
と間隔とは共に0.5〔μm〕であシ、素子領域6に形
成された回路Iくターンも設計値に極めて近いものであ
った。したがって本実施例方法によれば、レジストパタ
ーンを誦精度に形成することができ、集積回路の高密度
化に寄与し帰る等の効果を奏する。
When the resist pattern thus formed was observed with an electron microscope, it was found that the twin width and interval of the turns in the monitor area 5C were both 0.5 [μm], and the circuit I formed in the element area 6 was Therefore, according to the method of this embodiment, the resist pattern can be formed with repeatability, contributing to higher density of integrated circuits.

なお、本発明は上述した実施例に限定されるものではな
い。例えば、前記現像モニタ用/(ターンの1つとして
ライン幅と間隔との等しい)(ターンを用いたが、これ
は所望の7<ターンの寸法によって任意に選択すること
ができる。また、前記モ二り領域は必ずしも3つ必要な
ものではなく、1つのモニタ領域に適当なパターンを露
光し、誼領域の透過光量を検出することによって、現像
状態を確認することも可能である。さらに、現像モニタ
用パターンとして第6図に示す如き一定寸法のチェッカ
パターン等を用いることもできる。また、実施列では現
像の度合を確認するため現中液からウェーハを取シ出し
てモニタしているが、入射波長を適当に選択するととK
より現像液中でのモニタも可能である。
Note that the present invention is not limited to the embodiments described above. For example, for the development monitor/(one of the turns, a turn with equal line width and interval) was used, but this can be arbitrarily selected depending on the desired dimension of the turn. Three double areas are not necessarily required, and it is also possible to confirm the development state by exposing an appropriate pattern to one monitor area and detecting the amount of transmitted light in the double area. As a monitor pattern, a checker pattern of a fixed size as shown in Fig. 6 can also be used.Furthermore, in the actual process, the wafer is removed from the developing solution and monitored to check the degree of development. If the incident wavelength is selected appropriately, K
Monitoring in the developer is also possible.

要するに本発明は、その要旨を逸脱しない範囲で、種々
変形して実施することができる。
In short, the present invention can be implemented with various modifications without departing from the gist thereof.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(11) (b)は従来のレジストパターン形成
1横を示す断面模式図、第2図乃至第4図はそれぞれ本
発明の詳細な説明するためのもので第2図は平面図、第
3図(a)〜(e)は第2図の要部拡大図、第4図は現
像時間に対する透過率の変化を示す特性図、第5図は本
発明の一実施例方法に使用し九パターン幅モニタ装胃を
示す模式図、第6図は変形例を示す現像モニタ用パター
ンの平面図である。 1・・・基板、2・・・被加工物、3・・・レジ゛スト
膜、4・・・レジストパターン、5a、5b、5C…モ
ニタ領域、6・・・素子領域、7・・・マスク、8a。 #b 、Jic・・・赤外線検出器。 出顧人代理人  弁理士 鉤 江 武 2第1図 第21Q 第4図 第5図
FIG. 1(11)(b) is a schematic cross-sectional view showing the side of conventional resist pattern formation 1, FIGS. 2 to 4 are for explaining the present invention in detail, and FIG. 2 is a plan view; 3(a) to 3(e) are enlarged views of the main parts of FIG. 2, FIG. 4 is a characteristic diagram showing changes in transmittance with respect to development time, and FIG. FIG. 6 is a schematic diagram showing a nine-pattern width monitor mounting, and FIG. 6 is a plan view of a development monitor pattern showing a modified example. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Workpiece, 3...Resist film, 4...Resist pattern, 5a, 5b, 5C...Monitor area, 6...Element area, 7... Mask, 8a. #b, Jic...Infrared detector. Client's agent Patent attorney Takeshi Kagori 2 Figure 1 Figure 21Q Figure 4 Figure 5

Claims (2)

【特許請求の範囲】[Claims] (1)被加工物上にレジスト膜を形成する工程と、上記
レジスト膜を所望Iリーンに露光する工程と、しかるの
ち上記レジスト膜を現像する工程とからなるレジスト膜
くターン形成方法において、前記現像工椙前に前記レジ
スト1lII4のモ二り領域に現渫モニタ用ノ(ターン
を露光し、前記現像工程時に上記モニタ領域に電磁波を
照射して上記モニタWA斌を透過した電磁波の強度を検
出し、この検出情報に基づいて前記′現像の時間を制御
することを特徴とするレジストパターン形成方法。
(1) A resist film pattern forming method comprising the steps of forming a resist film on a workpiece, exposing the resist film to a desired I lean light, and then developing the resist film. Before the development step, the monitoring area of the resist 1lII4 is exposed to light for use in development monitoring, and during the development process, the monitoring area is irradiated with electromagnetic waves and the intensity of the electromagnetic waves transmitted through the monitor WA is detected. and controlling the development time based on the detected information.
(2)前記現鐵モニタ用ノ(ターンは、g光なしの/(
ターン、全領域露光の〕(ターンおよび半分鎮域亨光の
パターンからなるものであることを特徴とする特許請求
の範囲第1項記載のレジ:禾 トノー°ターン形成方法
。 体)前記現像工程時に照射する電磁波の波長社、前記レ
ジスト膜に対し吸収係数が高く、前記被加工物に対して
は透過係数が高く、かつレジスト膜を感光させない波長
領械であることを特徴とする請求 ジストパターン形成方法。
(2) The current iron monitor's (turn is /( without g light)
1. The method for forming a turn according to claim 1, characterized in that the pattern consists of a pattern of a turn and a half area exposure. A resist pattern characterized in that the wavelength range of the electromagnetic waves irradiated is in a wavelength range that has a high absorption coefficient for the resist film, a high transmission coefficient for the workpiece, and does not expose the resist film to light. Formation method.
JP16897781A 1981-10-22 1981-10-22 Resist pattern formation Pending JPS5870530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16897781A JPS5870530A (en) 1981-10-22 1981-10-22 Resist pattern formation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16897781A JPS5870530A (en) 1981-10-22 1981-10-22 Resist pattern formation

Publications (1)

Publication Number Publication Date
JPS5870530A true JPS5870530A (en) 1983-04-27

Family

ID=15878063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16897781A Pending JPS5870530A (en) 1981-10-22 1981-10-22 Resist pattern formation

Country Status (1)

Country Link
JP (1) JPS5870530A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6216523A (en) * 1985-07-16 1987-01-24 Toshiba Corp Method and device for developing of resist pattern
JPS62193247A (en) * 1986-02-20 1987-08-25 Fujitsu Ltd Development endpoint detecting method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS513173A (en) * 1974-06-25 1976-01-12 Matsushita Electric Ind Co Ltd HAKUMAKU PATAANSEIZOSOCHI
JPS5410677A (en) * 1977-06-23 1979-01-26 Ibm Method of controlling development or etching process
JPS5412672A (en) * 1977-06-30 1979-01-30 Ibm Method of controlling resist pattern development

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS513173A (en) * 1974-06-25 1976-01-12 Matsushita Electric Ind Co Ltd HAKUMAKU PATAANSEIZOSOCHI
JPS5410677A (en) * 1977-06-23 1979-01-26 Ibm Method of controlling development or etching process
JPS5412672A (en) * 1977-06-30 1979-01-30 Ibm Method of controlling resist pattern development

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6216523A (en) * 1985-07-16 1987-01-24 Toshiba Corp Method and device for developing of resist pattern
JPS62193247A (en) * 1986-02-20 1987-08-25 Fujitsu Ltd Development endpoint detecting method

Similar Documents

Publication Publication Date Title
EP0469765B1 (en) Method for monitoring photoresist latent images
CA1085968A (en) Resist development control system
TWI293141B (en) Dimension monitoring method and system
US4179622A (en) Method and system for in situ control of material removal processes
JPS6275442A (en) Deciding method for exposure amount of photosensitive lacquer layer
JPS5870530A (en) Resist pattern formation
JP3244783B2 (en) Alignment apparatus and method, and exposure apparatus and semiconductor device manufacturing method using the same
EP0134453B1 (en) Method for exposure dose calculation of photolithography projection printers
JP4160239B2 (en) Exposure amount measuring method and exposure amount measuring apparatus
JPH0697151A (en) Formation of etching pattern
GB2257504A (en) Determining the relative position of semiconductor water patterns
JP2802177B2 (en) Method for measuring dissolution rate of photoresist surface
Lane et al. Conventional novolak resists for storage ring x‐ray lithography
JPH04372112A (en) X-ray exposure mask
JPS6258654B2 (en)
DE102004008500B4 (en) Method for determining a radiation power and an exposure device
JP3166803B2 (en) X-ray exposure mask
JPS59144134A (en) End point judging apparatus of photo mask etching
JPS6286725A (en) Manufacture of semiconductor device
JPH02159011A (en) Control of pattern size in photolithography
JPH07130645A (en) Mask for x-ray exposure and x-ray aligner using same
JPS5848919A (en) Preparation of semiconductor device
JPH03179444A (en) Resist pattern forming method
JPH05241350A (en) Resist pattern forming method
JPH02302020A (en) X-ray mask and its manufacture