JPS63122262A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63122262A JPS63122262A JP61268948A JP26894886A JPS63122262A JP S63122262 A JPS63122262 A JP S63122262A JP 61268948 A JP61268948 A JP 61268948A JP 26894886 A JP26894886 A JP 26894886A JP S63122262 A JPS63122262 A JP S63122262A
- Authority
- JP
- Japan
- Prior art keywords
- mosfet
- gate
- titanium nitride
- titanium
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 230000006866 deterioration Effects 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Composite Materials (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ｒａｓｘの高信頼性を保証する半導体装置に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device that guarantees high reliability of RASX.
本発明は、Ｈ型ＭＯ８Ｆ１０ＴとＰ型ＭＯ１３？１１Ｔ
を積層した。いわゆるスタックドＣＭＯ１３Ｆ］！！Ｔ
において、シリコン基板上には第１Ｍ０ＥｉｌＦＦｉＴ
のゲート瞑、多結晶シリコン・チタンシリサイド・チタ
ンナイトライドの３層構造を持つ第１゜２の共通なゲー
ト電極、及び、第１と異極の第２ＭＯ８？］ＩＩＴのゲ
ート膜と多結晶シリコン層が蓄積して成る％Ｐ型Ｍ０８
７１！ｌ’ｌ’とＭｆｉＭＯ８１Ｆ’ＢＴが積層した構
造を特徴としている。The present invention is based on H-type MO8F10T and P-type MO13?11T.
were laminated. So-called stacked CMO13F]! ! T
, a first M0EilFFiT is formed on the silicon substrate.
a common gate electrode of 1°2 with a three-layer structure of polycrystalline silicon, titanium silicide, and titanium nitride, and a 2nd MO8? with a different polarity from the first. ]%P-type M08 consisting of IIT gate film and polycrystalline silicon layer accumulated
71! It is characterized by a structure in which l'l' and MfiMO81F'BT are stacked.
（従来の技術〕
従来の積層ＣＭＯ８７１！ｆＴにおいて、ゲート電極は
多結晶シリコンから成る。しかしながら多結晶シリコン
では、その高抵抗ゆえに、信号の遅延が大きく高速−ｅ
ｘには向いていない、このため抵抗の低いシリサイドと
多結晶が積層されたポリサイド構造がゲート電極として
採用されククある。(Prior art) In the conventional multilayer CMO871!fT, the gate electrode is made of polycrystalline silicon.However, polycrystalline silicon has a large signal delay due to its high resistance, and is
For this reason, a polycide structure in which low-resistance silicide and polycrystal are laminated is adopted as the gate electrode.
第２図は、この従来のポリサイドゲート電極を持り積層
ＣＭＯ８？ｌＴを示す、従来の構造ではチタンシリサイ
ド４上に直接第２Ｍ０Ｅ＋７１！！！グー） ＩＩ Ｂ
ｉＯａ ６が形成され暮。Figure 2 shows this conventional multilayer CMO 8? with a polycide gate electrode. In the conventional structure, the second M0E+71! is directly on the titanium silicide 4. ! ! Goo) II B
iOa 6 was formed.
しかしながら、シリサイド上にｓｈｏ！＠形成する場合
、チタンシリサイドのチタンは酸化し、析出したシリコ
ン原子が、チタンシリサイド４と８ｊ０１Ｇ界面を凹凸
にする。との凹凸のため第２Ｍ０８ＩＦＥＴのゲート耐
圧が劣化し、 ＭＯ８１ＦＩＩＩＴからなるＴＪＳ工の
信頼性を損ねるという欠点を有する。However, sho on silicide! In the case of @ formation, titanium in the titanium silicide is oxidized, and the precipitated silicon atoms make the interface between the titanium silicide 4 and 8j01G uneven. This has the disadvantage that the gate breakdown voltage of the second M08IFET deteriorates due to the unevenness of the surface, impairing the reliability of the TJS made of MO81FIIIT.
本発明の目的はかかる従来の欠点を取り除き。The object of the present invention is to obviate such conventional drawbacks.
高信頼性が保障されるＬ１３工を実現するための積層Ｃ
ＭＯＥＩＩＰＥＴ’ｉ提供することにある。Laminated C to realize L13 construction that guarantees high reliability
MOEIIPET'i is to provide.
従来の問題を解決するために本発明では、チタンシリサ
イドとａｇｏ 、との間にチタンナイトライド層を形成
した。チタンナイトライドはシリサイドに比べ酸化され
に＜〈、均一で平担なチタンナイトライドとＢイ０冨の
界面を形成できる。従って本発明では第２Ｍ０８７１！
！Ｔのゲート耐圧が優れた高信頼の半導体装置を可能に
する。In order to solve the conventional problems, in the present invention, a titanium nitride layer is formed between titanium silicide and ago. Titanium nitride is less susceptible to oxidation than silicide and can form a uniform and flat interface between titanium nitride and B0-rich. Therefore, in the present invention, the second M0871!
! To enable a highly reliable semiconductor device with excellent gate breakdown voltage of T.
以下実施列を用いて説明する。 This will be explained below using implementation columns.
第１図は本発明による積層ＣＭ０８ＩＦ１！ｆＴの構造
断面図であフ、第２図は従来の積層Ｃ：Ｍ０８ＦＩｎＴ
の構造断面図である。FIG. 1 shows the laminated CM08IF1 according to the present invention! Fig. 2 is a cross-sectional view of the structure of fT.
FIG.
本発明による積層ＣＭＯＥｉＦＦｔＴにおいては。In the stacked CMOEiFFtT according to the present invention.
第１図に示すごと＜％ ＢＳ基板１にはＮ型の第１Ｍ０
８７ＩＴのソースドレイン及びゲート膜２が形成され、
第１．２の共通ゲート電極は、多結晶シリコン３．−チ
タンシリサイド４．及びチタンナイトライド５から形成
され、Ｐ型の第２Ｍ０８ＦＥＴのゲート膜６及びソース
・ドレイン及びチャネルからなる多結晶シリコン層７が
形成されることによ５１ＭＭ０ａ管Ｚ丁と２ＭＯ８：Ｆ
ＩＴが積層されている１本発明ＯｗＩ造によれば、Ｐ型
の第２ Ｍ Ｏ８Ｆ ＲＴ ＯＢｉＯｔ ６は、熱的に
安定なチタンナイトライド層５上に形成されるため、チ
タンナイトライド５とａｚｏ１６の界面にはＳ（が析出
されることがなく、平担な界面を得ることができる。従
って第２Ｍ０５ＦＫＴのゲート膜耐圧の劣化を抑制した
積層ＣＭＯＥ１１ＦＦｉＴを可能くする。As shown in Fig. 1, the BS substrate 1 has an N-type first M0
87IT source/drain and gate films 2 are formed,
The 1.2nd common gate electrode is made of polycrystalline silicon 3. -Titanium silicide4. and titanium nitride 5, and a gate film 6 of a P-type second M08FET and a polycrystalline silicon layer 7 consisting of a source, drain, and channel are formed, thereby forming a 51MM0a tube Z and 2MO8:F.
According to the OwI structure of the present invention in which IT is laminated, the P-type second MO8F RT OBiOt 6 is formed on the thermally stable titanium nitride layer 5, so that the titanium nitride 5 and the azo16 S (S) is not precipitated at the interface, and a flat interface can be obtained. Therefore, a multilayer CMOE11FFiT in which deterioration of the gate film breakdown voltage of the second M05FKT is suppressed is possible.
以上説明したように１本発明の積眉？ＭＯ日ＩＥＴは、
第２Ｍ０１３ＰＫＴＯゲート耐圧劣化を防ぎ、高信頼性
ＩＪＳ工を提供する。As explained above, is it the product of this invention? MO day IET is
2nd M013PKTO gate breakdown voltage deterioration is prevented and highly reliable IJS construction is provided.
第１図は本発明による１Ｍ０８Ｆ’！！：’ｒ、！：Ｒ
ＭＯ８ＩＰＥＴの積層構造断面図。
第２図は従来のＭＭＯ８１１ＣＴと：Ｅ’ＭＯＥｉ？Ｉ
！ｆＴの積層構造断面図。
１・・Ｂ４基板 ２０・ゲート熱酸化膜３、・・多結晶
シリコン
４・・チタンシリサイド
５・・チタンナイトライド
６・・ＳｊＯ，（第２ＭａｓｙｍＴゲート艇）７・・多
結晶シリコン
以 上Figure 1 shows 1M08F' according to the present invention! ! :'r,! :R
A cross-sectional view of the laminated structure of MO8IPET. Figure 2 shows the conventional MMO811CT: E'MOEi? I
! A sectional view of the laminated structure of fT. 1.B4 substrate 20.Gate thermal oxide film 3,...Polycrystalline silicon 4..Titanium silicide 5..Titanium nitride 6..SjO, (2nd MasymT gate boat) 7..Polycrystalline silicon or more
Claims (1)
ゆるスタツクドＣＭＯＳＦＥＴにおいて、第１ＦＥＴの
ゲート膜上には多結晶シリコン、チタンシリサイド、チ
タンナイトライドが積層され、該チタンナイトライド層
上には第２ＦＥＴのゲート膜が形成され、該第２ＦＥＴ
のゲート膜上には多件晶シリコンが形成され、シリコン
基板上には第１のゲート膜、多結晶シリコン・チタンシ
リサイド・チタンナイトライドの３層構造を持つゲート
電極、第２のゲート膜及び多結晶シリコンが蓄積し、Ｐ
型ＭＯＳＦＥＴとＮ型ＭＯＳＦＥＴが積層した構造を持
つことを特徴とする半導体装置。In a so-called stacked CMOSFET in which an N-type MOSFET and a P-type MOSFET are stacked, polycrystalline silicon, titanium silicide, and titanium nitride are stacked on the gate film of the first FET, and the gate film of the second FET is stacked on the titanium nitride layer. is formed, and the second FET
Polycrystalline silicon is formed on the gate film, and a first gate film, a gate electrode having a three-layer structure of polycrystalline silicon, titanium silicide, and titanium nitride, a second gate film, and a gate electrode are formed on the silicon substrate. Polycrystalline silicon accumulates and P
A semiconductor device characterized by having a structure in which a type MOSFET and an N type MOSFET are stacked.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61268948A JPS63122262A (en) | 1986-11-12 | 1986-11-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61268948A JPS63122262A (en) | 1986-11-12 | 1986-11-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63122262A true JPS63122262A (en) | 1988-05-26 |
Family
ID=17465513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61268948A Pending JPS63122262A (en) | 1986-11-12 | 1986-11-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63122262A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4980732A (en) * | 1987-10-15 | 1990-12-25 | Nec Corporation | Semiconductor device having an improved thin film transistor |
-
1986
- 1986-11-12 JP JP61268948A patent/JPS63122262A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4980732A (en) * | 1987-10-15 | 1990-12-25 | Nec Corporation | Semiconductor device having an improved thin film transistor |
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