JPS61139067A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61139067A JPS61139067A JP26125284A JP26125284A JPS61139067A JP S61139067 A JPS61139067 A JP S61139067A JP 26125284 A JP26125284 A JP 26125284A JP 26125284 A JP26125284 A JP 26125284A JP S61139067 A JPS61139067 A JP S61139067A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline
- gate
- silicide
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 abstract description 10
- 229910021332 silicide Inorganic materials 0.000 abstract description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 5
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021344 molybdenum silicide Inorganic materials 0.000 abstract description 2
- 229910021341 titanium silicide Inorganic materials 0.000 abstract description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 2
- 239000007772 electrode material Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 16
- 230000000694 effects Effects 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、共通ゲー）ＭＣ１Ｓ型トランジスタあるいは
折りたたみゲートＭＯ３型トランジスタのゲート材料構
造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gate material structure of a common gate (MC1S) type transistor or a folded gate MO3 type transistor.
従来、共通ゲーｈＭｏ Ｓ型トランジスタのゲート材料
構造は、第１図に示す構造となっていた。Conventionally, the gate material structure of a common game hMo S type transistor has been the structure shown in FIG.
すなわち、８１基板１の表面にはフィールド酸化膜２、
第１のゲート酸化膜５、第１のソース及びドレイン拡散
層３，４が形成され、前記第１のゲート酸化膜５上には
多結晶Ｓｉからなるゲート電Ｗ１６が形成され、該ゲー
ト電極６上には、該多結晶Ｓｉを酸化して得られた第２
のゲート酸化膜７が形成され、該第２のゲート酸化膜７
上にはＳｉ膜８が形成され、該Ｓｉ膜８には第２のソー
ス及びドレイン拡散層９，１０が形成されて成るのが通
例であった。That is, on the surface of the 81 substrate 1, there is a field oxide film 2,
A first gate oxide film 5, first source and drain diffusion layers 3 and 4 are formed, and a gate electrode W16 made of polycrystalline Si is formed on the first gate oxide film 5. On top is a second layer obtained by oxidizing the polycrystalline Si.
A gate oxide film 7 is formed, and the second gate oxide film 7
Typically, a Si film 8 is formed thereon, and second source and drain diffusion layers 9 and 10 are formed on the Si film 8.
前記従来技術の如く、共通ゲー）ＭＯＳ型トランジスタ
の共通ゲート材料を多結晶Ｓｉとなすことにより、多結
晶Ｓｉの抵抗値が大なるため、トランジスタの動作速度
を速くできないという問題点があった。As in the prior art described above, by using polycrystalline Si as the common gate material of the common gate MOS transistors, the resistance value of polycrystalline Si becomes large, so there is a problem that the operating speed of the transistor cannot be increased.
本発明は、かかる従来技術の問題点を解決するために、
共通ゲー）ＭＯ８型トランジスタのゲート材料構造を多
結晶Ｓｉ−シリサイド−多結晶Ｓｉの３層構造となすこ
とを特徴とする。In order to solve the problems of the prior art, the present invention has the following features:
A common feature is that the gate material structure of the MO8 type transistor is a three-layer structure of polycrystalline Si-silicide-polycrystalline Si.
前記の如く、共通ゲートＭＯ５型トランジスタのゲート
材料構造を多結晶Ｓｉ−シリサイド−多結晶Ｓｉの３層
構造となすことにより、多結晶Ｓｉ単層の共通ゲートに
比べて、ゲート電極の抵抗値を小さくできる作用がある
と共に、５ｉ−３ｉＯ２系の良好な界面特性はそのまま
維持できるという作用もある。As mentioned above, by forming the gate material structure of the common gate MO5 type transistor into a three-layer structure of polycrystalline Si-silicide-polycrystalline Si, the resistance value of the gate electrode can be lowered compared to a common gate made of a single layer of polycrystalline Si. It has the effect of being able to be made smaller, and also has the effect of maintaining the good interfacial properties of the 5i-3iO2 system.
以下、実施例により本発明を詳述する。 Hereinafter, the present invention will be explained in detail with reference to Examples.
第２図は本発明の一実施例を示す共通ゲートＭＯＳ型ト
ランジスタの断面図である◇すなわち、Ｓｉ基板１１０
表面にはフィールド酸化膜１２・第１のゲート酸化膜１
５、第１のソース・ドレイン拡散層１５．１４が形成さ
れ、前記第１のゲート酸化膜１５上には第１の多結晶８
１層１６とタングステン・シリサイドあるいはモリブデ
ン・シリサイドあるいはチタン・ソリサイド等からなる
シリサイド膜７と、第２の多結晶Ｓｉ膜１８から成る３
層構造のゲート電極が形成され、前記第２の多結晶Ｓｉ
、膜１８上には第２のゲート酸化膜１９が形成され、該
Ｓｉ膜２Ｑには第２のソース・ドレイン拡散層２１．２
２が形成されて成る。FIG. 2 is a cross-sectional view of a common gate MOS type transistor showing one embodiment of the present invention. In other words, the Si substrate 110
Field oxide film 12 and first gate oxide film 1 are on the surface.
5. A first source/drain diffusion layer 15.14 is formed, and a first polycrystalline layer 8 is formed on the first gate oxide film 15.
A layer 3 consisting of a first layer 16, a silicide film 7 made of tungsten silicide, molybdenum silicide, titanium silicide, etc., and a second polycrystalline Si film 18.
A layered gate electrode is formed, and the second polycrystalline Si
, a second gate oxide film 19 is formed on the film 18, and a second source/drain diffusion layer 21.2 is formed on the Si film 2Q.
2 is formed.
第３図は本発明のその他の実施例を示す共通グー４ＭＯ
３型トランジスタの断面図である。すなわち、Ｓｉ基板
５１０表面にはフィールド酸化膜３２、ＩＮのゲート酸
化膜３５、第１のソース・ドレイン拡散層５５．５４が
形成され、前記第１のゲート酸化膜３５上には第１の多
結晶Ｓｉ膜３６と部分的に形成されたシリサイド膜３７
と第２の多結晶Ｓｉ膜３８がシリサイド膜３７と第２の
多結晶Ｓｉ膜５８かシリサイド膜３７の側壁を被覆した
状態の３層構造のゲート電極が形成され、前記第２の多
結晶Ｓｉ膜５日上にはＳｉ膜４ａが形成され、該Ｓｉ膜
４０には第２のソース・ドレイン拡散層４１．４２が形
成されて成る。FIG. 3 is a common goo 4MO showing another embodiment of the present invention.
FIG. 3 is a cross-sectional view of a type 3 transistor. That is, on the surface of the Si substrate 510, a field oxide film 32, an IN gate oxide film 35, and a first source/drain diffusion layer 55, 54 are formed, and on the first gate oxide film 35, a first polyimide film is formed. Crystalline Si film 36 and partially formed silicide film 37
A gate electrode having a three-layer structure is formed in which the second polycrystalline Si film 38 covers the silicide film 37 and the sidewalls of the second polycrystalline Si film 58 or the silicide film 37. A Si film 4a is formed on the film 5, and second source/drain diffusion layers 41 and 42 are formed on the Si film 40.
本発明の如く、共通ゲー）ＭＯＳ型トランジスタのゲー
ト１！極材料構造を多結晶Ｓｉ−シリサイド−多結晶Ｓ
ｉの６層構造となすことによりｔ極配線の電気抵抗が減
少でき、ＭＯ３型トランジスタの速度特性を速くするこ
とができる効果がある。As in the present invention, common gate) MOS type transistor gate 1! The polar material structure is polycrystalline Si-silicide-polycrystalline S
By forming the i six-layer structure, the electrical resistance of the t-pole wiring can be reduced, and the speed characteristics of the MO3 type transistor can be improved.
第１図は従来技術による共通ゲートＭＯ９型トランジス
タの断面図を、第２図及び第３図は本発明の実施例を示
す共通ゲートＭＯ８型トランジス゛りの断面図である。
１．１１．３１・・・３１基板
２．１２．３２・・・フィールド酸化膜３．４及び１３
．１４及び５５．３４・・・第１のソース・ドレイン拡
散層
９．１０及び２１．２２及び４１．４２・・・第２のソ
ース・ドレイン拡散層
５．１５．３５・・・第１のゲート酸化膜７．１９．５
９・・・第２のゲート酸化膜８．２０．４０・・・Ｓｉ
膜
６・・・多結晶Ｓｉ膜
１６．３６・・・第１の多結晶Ｓｉ膜
１８．３８・・・第２の多結晶Ｓｉ膜
１７．３７・・・シリサイド膜
第１図
第２図
第３区FIG. 1 is a sectional view of a common gate MO9 type transistor according to the prior art, and FIGS. 2 and 3 are sectional views of a common gate MO8 type transistor showing an embodiment of the present invention. 1.11.31...31 substrate 2.12.32...field oxide film 3.4 and 13
．． 14 and 55.34...First source/drain diffusion layer 9.10, 21.22 and 41.42...Second source/drain diffusion layer 5.15.35...First gate Oxide film 7.19.5
9... Second gate oxide film 8.20.40... Si
Film 6... Polycrystalline Si film 16.36... First polycrystalline Si film 18.38... Second polycrystalline Si film 17.37... Silicide film Figure 1 Figure 2 3rd ward
Claims (1)
関し、多結晶Ｓｉ−シリサイド−多結晶Ｓｉの３層構造
となすことを特徴とする半導体装置。A semiconductor device characterized in that the gate material structure of a common gate MOS transistor has a three-layer structure of polycrystalline Si-silicide-polycrystalline Si.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26125284A JPS61139067A (en) | 1984-12-11 | 1984-12-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26125284A JPS61139067A (en) | 1984-12-11 | 1984-12-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61139067A true JPS61139067A (en) | 1986-06-26 |
Family
ID=17359242
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26125284A Pending JPS61139067A (en) | 1984-12-11 | 1984-12-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61139067A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5194749A (en) * | 1987-11-30 | 1993-03-16 | Hitachi, Ltd. | Semiconductor integrated circuit device |
| US5341014A (en) * | 1992-01-07 | 1994-08-23 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and a method of fabricating the same |
| US5569947A (en) * | 1994-06-28 | 1996-10-29 | Nippon Steel Corporation | Insulated-gate field-effect transistor in a semiconductor device in which source/drain electrodes are defined by formation of silicide on a gate electrode and a field-effect transistor |
| US5606192A (en) * | 1993-12-17 | 1997-02-25 | Nec Corporation | Semiconductor integrated circuits having bipolar transistors and LDD-structured MOSFET |
| US5872385A (en) * | 1994-05-02 | 1999-02-16 | Motorola Inc. | Conductive interconnect structure and method of formation |
-
1984
- 1984-12-11 JP JP26125284A patent/JPS61139067A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5194749A (en) * | 1987-11-30 | 1993-03-16 | Hitachi, Ltd. | Semiconductor integrated circuit device |
| US5483083A (en) * | 1987-11-30 | 1996-01-09 | Hitachi, Ltd. | Semiconductor integrated circuit device |
| US5619055A (en) * | 1987-11-30 | 1997-04-08 | Hitachi, Ltd. | Semiconductor integrated circuit device |
| US5700705A (en) * | 1987-11-30 | 1997-12-23 | Hitachi, Ltd. | Semiconductor integrated circuit device |
| US5341014A (en) * | 1992-01-07 | 1994-08-23 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and a method of fabricating the same |
| US5606192A (en) * | 1993-12-17 | 1997-02-25 | Nec Corporation | Semiconductor integrated circuits having bipolar transistors and LDD-structured MOSFET |
| US5872385A (en) * | 1994-05-02 | 1999-02-16 | Motorola Inc. | Conductive interconnect structure and method of formation |
| US5569947A (en) * | 1994-06-28 | 1996-10-29 | Nippon Steel Corporation | Insulated-gate field-effect transistor in a semiconductor device in which source/drain electrodes are defined by formation of silicide on a gate electrode and a field-effect transistor |
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