JPS63122175A - Mos field-effect transistor - Google Patents

Abstract

PURPOSE:To lengthen the life of a device by optimizing the concentration of an impurity inside ah n-layer of an LDD-type MOSFET. CONSTITUTION:After a gate oxide film 12 has been deposited on a p-type Si substrate 11, a gate electrode 13 is formed in such a way that a polysilicon layer doped with, e.g., P of high concentration is deposited and patterned. Then, by an ion implantation process of a donor such as P, As or the like by making use of the gate electrode 13 as a mask, n<-> layers 14a, 14b are formed. If the highest concentration of an impurity inside the n<-> layers is set to 2.5X10<18>-5X10<18>cm<-3>, it is possible to obtain a long-lived LDD-type MOSFET where both the reduction of the concentration of an electric field at a channel and the resistance to depletion by an electron trapped inside the gate oxide film are optimized.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a MOS field effect transistor (hereinafter referred to as MOSFE).
(referred to as T) 1. Especially LDD with high hot carrier resistance (Lightly Doped Drain)
) type MOSFET.

(Prior Art) Conventionally, this type of device has been disclosed in the literature, IEEE)
ACTIO8ON ELECTORON DEVICE
S) VOL.

ED-32, I62. February 1985 p, 9.429-
There are 433 disclosures. In general, as MOS transistors are miniaturized and the channel electric field increases, hot carriers are generated, which are injected into the gate oxide film and trapped. conductance). Various attempts have been made to prevent this, and in particular, the LDD structure disclosed in the above-mentioned document has been widely studied. FIG. 2 is a schematic sectional view for explaining the structure, which will be explained below using the drawings.

In FIG. 2, 1 is the St substrate, 2 is the gate oxide film, and 3 is the St substrate.
is the f-1 electrode, for example, n+ polysilicon, 4m,
4b is an n'''' layer formed by ion-implanting As (arsenic), PC phosphorus) at a low concentration using the gate 3 as a mask, 5a,
Sidewall 5b is formed by stacking anisotropic etching of PSG (phosphor glass), etc., and 6a and 6b are formed by ion implantation of As, P, etc. at high concentration using the dirt electrode 3 and sidewall 5m, 5b as a mask. source and drain regions.

Here, normally, a potential Ov is applied to the source region 6a, and about 5V is applied to the drain region 6b. -) The channel is controlled by the voltage of the electrode 3, and a current is passed between the source region 6a and the drain region 6b to operate. n-layer 4
In the structure without a and 4b, the electric field does not peak at the end of the drain region 6b, which is a heavily doped layer, and all hot carriers are generated. In order to reduce this peak electric field, n'''' layers 4m and 4b are provided.
In a*4b, impurities of the same conductivity type and at a lower concentration than the source region 6a' and the drain region 6b are introduced.

The difference in impurity concentration between the n-layers 4m and 4b greatly affects the electric field of the channel.

On the other hand, the electrons trapped in the dirt oxide film on the n-layer 4m and 4b are generated in the n-layer 4m.

The degree to which the sigm value, which has a large resistance due to depletion of 4b, deteriorates is also greatly influenced by the impurity concentration of the n'''' layers 4m and 4b.

In the above literature, as a result of integrating these, n14a, 4b
It is stated that a surface concentration of 1X10 to 2.5X10 cm is preferable. In addition, the n-layer is 4m here.

The surface concentration of 4b is also the peak concentration.

(Problem to be solved by the invention) However, in the method described above, the dart length is 1.0 μm.
In the case of m, is it small? −) long, then n
Some impurity concentration is 1X1018~2.5X1018m
−' is not optimal, for example, the dart length is 0.8 μm.
When the temperature reaches a certain level, the FET deteriorates so much that normal operation becomes impossible.

Therefore, the present invention is directed to the LDD W MOSFET described above.
The purpose of the present invention is to optimize the i-layer impurity concentration of the semiconductor device and provide a device with excellent characteristics and a long device life.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention includes a pW silicon substrate and a goo electrode in which a dirt metal is formed on a predetermined region of the silicon substrate via an insulating film. In this silicon substrate, source and drain regions containing nfi impurities such as P and As are formed opposite to both sides of this gate electrode, and a region formed in contact with the source side of this drain region is formed. P at a lower concentration than the drain region of
In an LDD type MOS comprising at least a low concentration n-type impurity region containing an n-type impurity such as As, the low concentration impurity region has an impurity concentration of 2.5×10 c.
m~5×10” country-3.

(Function) As described above, according to the present invention, since a low concentration impurity region with an impurity concentration of 2.5X10 to 5X10 cm is provided in the MOSFET, the electric field strength of the channel is reduced and the electrons trapped in the gate oxide film are reduced. It is possible to increase the resistance to depletion due to depletion, and it is possible to improve the life of the MOSFET.

(Example) FIGS. 1(a) to 1(d) are process sectional views of an LDD type MOSFET for detailed explanation of the present invention, which will be explained below using the drawings.

First, as shown in FIG. 1(a) K, a p-type St substrate 11
After laminating the Ke-) oxide film 12, a gate electrode 13f having a cedar length of 0.8 μm is formed by laminating and nocturning polysilicon doped with a high concentration of P, for example. Next, as shown in FIG. 1(b), a peak impurity concentration of 3XIOc is achieved by ion-implanting donors such as P and As using the r--to electrode 13t'' mask.
m layers 14a and 14b are formed.

After that, as shown in FIG. 1(c), after laminating a PSG film on the surface, etching is performed using an anisotropic etching method such as RIE (reactive ion etching) to form a side wall of PSG only on the side surface of the gate electrode. 15a, 15bt-form.

Next, as shown in FIG. 1(d), a donor such as P#As is ion-implanted using the dart electrode 13 and the side walls 15m and 15b as a mask, so that the peak impurity concentration is reduced to approximately 2.
．． 5×10 source region 16a and drain region 1
6bfj! :Form.

In these series of steps, it is the impurity concentration of the n'' layer that has the most influence on hot carrier resistance, that is, the life of the MOSFET. FIG. 3 shows experimental results regarding the relationship between the peak impurity concentration of the n'''' layer and the life of the MOSFET. Here, the lifetime means that the drain voltage of the MOSFET is 7. OV and a dart voltage of 3.5 Vt- were applied, an accelerated test was conducted, and the time was taken as the time for the gm value to deteriorate by 10% of the initial value. The gate length of this MOSFET is 0.8μm,
As is clear from Figure 3, the n-layer peak: the impurity concentration is
It can be seen that the life of the MOSFET is maximum at 3 x 10' 8 cm-3. In addition, the drain voltage of the LDD structure MOSFET is 5. QV, f When used for 10 years under the normally used conditions of gate voltage 0 to 5 V, in order to suppress the deterioration of gm to less than 10 times the initial value, in the accelerated test shown in Fig. 3, 5 × 10 (
It is necessary to ensure the lifespan of sea), as shown in Figure 3.
The peak impurity concentration of the layer is 2.5X10 ~ 5X10
It turns out that cm should be used.

As mentioned above, the peak impurity concentration of the n-layer is set to 2.5X1
By setting it as 018~5 x 1018 cm-3,
A long-life LDD fi MOSFET optimized for both reduction of electric field concentration in the channel and resistance to depletion due to electrons trapped in the gate oxide film?
,Obtainable.

In the embodiment of the present invention, e-) n-
Although the layers 14h and 14bf are formed, the same effect can be expected even if only the n- layer 14b on the drain region 16b side where electric field concentration occurs is formed.

(Effects of the Invention) As described above, according to the present invention, in a MOSFET with a short dart length of about 0.8 μm, nl with a peak impurity concentration of 2.5×10” to 5×10” cm
4 megapit dynamic random access memory (L with a density of 4MDRAM or higher)
This makes it possible to improve the lifespan of MOSFETs, which can also be used for SI.

[Brief explanation of the drawing]

Figure 1 shows an LDD type MOS for detailed explanation of the present invention.
FET process cross-sectional diagram, Figure 2 is a conventional LDD 131M
FIG. 3, a cross-sectional view of the OSFET, is a diagram showing the relationship between the peak impurity concentration of the n-layer and the life of the MOSFET. 1.11...Si substrate, 2.12...dirt oxide film, 3, 13-...dirt electrode, 4a, 4b, J4a. 14b...n-layer, 5 m, 5 b
, 15 m, 15 b = side wall, 6
a, 16a--source region, 6b, 16b
...Drain area. Patent applicant Oki Electric Industry Co., Ltd. LDD type MO5FETn Engineering TV? rm) (fk1*+
1) Figure 1: Condolences to LDD! ! ! MO5FET 5U 2nd
Figure 6 Procedural Amendment (White Wa 1, Indication of Case 1986 Patent Application No. 266762 2, Title of Invention MOS Field Effect Transistor 3, Person Making Amendment Relationship with Case Patent Application Person Place (〒105) 1-7-12-4 Toranomon, Minato-ku, Tokyo
, Agent address (105) 1-7-1 Toranomon, Minato-ku, Tokyo
No. 2\, - 6, Contents of amendment (1) Page 2, line 12 of specification M p, P, 42
9-433 disclosure" is corrected to read "dart length 0.8 μm."

Claims (1)

[Claims] 1) A p-type silicon substrate, a gate electrode in which a gate metal is formed on a predetermined region of the silicon substrate via an insulating film, and both sides of the gate electrode in the silicon substrate. source and drain regions containing n-type impurities formed opposite to the drain region; and a low concentration n-type impurity containing n-type impurities at a lower concentration than the drain region formed in contact with the source side of the drain region. An LDD comprising at least a region (
LightlyDopedDrain) type MOS field effect transistor, wherein the impurity concentration of the low concentration impurity region is 2.5×10
^1^8cm^-^3~5x10^1^8cm^-^3
A MOS field effect transistor characterized by: 2) The MOS field effect transistor according to claim 1, wherein the n-type impurity is one or more impurities selected from P (phosphorus) and As (arsenic).