JPS63120470A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To adjust uniformly and with excellent repreducibility the current value between the respective ohmic electrode layers of source.drain, by a method wherein after an amorphous layer is formed by performing selectively and in an adjustable manner an ion implantation into a part in an active layer corresponding to a recess etching, this amorphous layer is eliminated and a recess etching surface is formed. CONSTITUTION:When a compound semiconductor device is manufactured, a recess etching surface 5 is made in an active layer 2 before a gate 6 is formed, and the current value between the respective ohmic electrode layers 4, 4 of source.drain is adjusted. In such a working process, after an amorphous layer 8 is formed by performing selectively in an adjustable manner an ion implantation 7 into a part in the active layer 2 corresponding to a recess etching, and a desired current value is adjusted, this amorphous layer 8 is eliminated to form the recess etching surface 5. For example, the active layer 2 is formed on a semi-insulating GaAs substrate 11, and the respective ohmic electrode layers 4, 4 of source. drain are formed by applying a photoresist pattern 3 to a mask. Successively, after the amorphous layer 8 is formed by ion implantation 7, the amorphous layer 8 is eliminated by etching, and the recess etching surface 5 is made.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a Schottky barrier gate field effect transistor using a compound semiconductor such as gallium arsenide.
In particular, this invention relates to an improvement in the method of adjusting the current value between the source and drain ohmic electrode layers before the gate is formed.

[Conventional technology]

The main manufacturing steps of a conventional Schottky barrier gate field effect transistor (hereinafter referred to as 5BFET) according to its general structure are shown in FIGS. 2(a) to 2(d).

That is, in the conventional configuration shown in FIG.
3 is a photoresist pattern patterned on the substrate surface; 4 and 4 are formed at positions corresponding to source and drain on the active layer 2 using this pattern 3 as a mask; 5 is a recessed etched surface formed on the active layer 2 to form a gate, and 8 is a gate electrode layer buried in this recessed etched surface 5.

However, the manufacturing process for this conventional configuration is as follows:
First, the active layer 2 is selectively formed on a predetermined portion of the main surface of the semi-insulating gallium arsenide substrate 1 by an ion pillar implantation method or the like. A photoresist pattern 3 is formed by patterning using, for example, a photoresist pattern 3, and by using this photoresist pattern 3 as a mask, source and drain ohmic electrode layers 4.4 are formed at positions corresponding to the source and drain on the active layer 2. (Figure 2(a)).

Next, add 2 parts of etching solution, for example, tartaric acid + 1 part
(By selectively etching the portion of the active layer 4 corresponding to the gate using the mixed etching solution No. 202,
The recess-etched surface 5 is placed while adjusting the current value that waves between each ohmic electrode layer 4 to a desired value (FIG. 4(b)).

Next, on these entire surfaces, an electrode metal layer 6a is formed, for example, by vapor deposition (FIG. 2(C)), and then, for example,
By immersing it in acetone and removing unnecessary pattern parts, a gate pattern is formed on the recessed etched surface 5F- to form the goo 1-'rrt and JIi layers 6, and each ohmic layer of the source and drain is formed. electrode layer 4,
4, wiring layers 4a and 4a are left on each layer 17 (FIG. 4(d)), thus obtaining the desired 5BFET structure.

[Problem that the invention seeks to solve]

The 5nFET structure in the conventional example is manufactured as described above, and when transferring the etched surface of the glue for current value adjustment, Therefore, in order to uniformly adjust the current value, it is necessary to partially re-etch the etching speed.
However, since the etching solution has a very large influence, it is necessary to constantly monitor the etching solution.

This inventive method was devised to solve these conventional problems, and its purpose is to:
This type of Schottky barrier gate electric field is designed to uniformly and reproducibly adjust the 1TL flow of each source ψ drain within the two substrate wafers and between the substrate wafer phases 17. An object of the present invention is to provide a method for manufacturing an effect transistor.

[Means for solving problems]

In order to achieve the above object, the method for manufacturing a Schottky barrier gate field effect transistor according to the present invention includes adjusting the current value between the source and drain ohmic electrode layers by applying a recessed etched surface to the active layer before forming the gate electrode. In the step of forming an amorphous layer by selectively and adjustingly implanting ions into the recess-etchable portion of the active layer, and adjusting the current value to the required value,
This amorphous layer is removed to form a recessed etched surface.

[For production]

That is, in the case of the method of the present invention, ion implantation is selectively and controlled into the recess-etched portion in the active layer, thereby making the recess-etched portion amorphous to the required thickness. By forming an amorphous layer, the thickness of the corresponding part of the active layer can be narrowed with good control, and as a result, the current value between the source and drain ohmic electrode layers can be adjusted uniformly and to the required value. It can be performed with good reproducibility.

〔Example〕

Hereinafter, a method for manufacturing a Schottky barrier gate field effect transistor according to an embodiment of the present invention will be described in detail with reference to FIGS. 1(a) to 1(f).

These FIGS. 1(a) to 1f) are cross-sectional views sequentially showing the manufacturing steps of MESFET according to the method of this embodiment. Figure 2 (a) to d) Conventional lateral horns,
The same reference numerals indicate the same or equivalent parts.

That is, in the embodiment method shown in FIG. 1, first, the active layer 2 is selectively formed at a predetermined portion of the main surface I of the semi-insulating gallium arsenide substrate 11 by ion implantation or the like. Photoengraving on top of these 1. The photol/cyst pattern 3 is formed by using etching method etc.
After patterning, the photoresist pattern 3 is used as a mask to form source and drain ohmic electrode layers 4 at positions corresponding to the sources and drains of the active layer 2.
4 (see figure (a)).

Then, these photoresist patterns 3. By selectively and adjustingly performing ion implantation 7 from above using O and each ohmic electrode layer 4, 4 as a mask, (
(b) in the same figure, it is possible to form the amorphous layer 8 by effectively making the portion corresponding to the recess etch in the active layer 2, and by extension, the portion corresponding to the gate, amorphous with good controllability ((b) in the same figure). C)). That is, by forming this amorphous layer 8, the formation depth of the corresponding portion of the active layer 2 is narrowed, and as a result, the value of the current flowing between the ohmic electrode layers 4 can be adjusted to a desired value. It is.

Next, by immersing this in a hydrochloric acid solution heated to, for example, about 80° C., the amorphous layer 8 formed by the ion implantation 7 in the recess etched portion of the active layer 2 can be removed. The recessed etched surface 5 can be transferred as expected (FIG. 2(d)).

Subsequently, as in the case of the conventional method, with the photoresist pattern 3 left in the negative state,
After that, an electrode metal layer 8a is formed on the entire surface thereof by, for example, vapor deposition, as shown in FIG. 2(e).

For example, by immersing this in acetone and removing unnecessary pattern parts including the photoresist pattern 3, a gate pattern is formed on the recessed etched surface 5 to form a gate electrode layer 6, and the source - Wiring layers 4a and 4a are left in each drain ohmic electrode layer 4.4-L (FIG. (f)), thus obtaining the desired 5BFET structure.

Therefore, in the configuration of the 5BFET according to this embodiment, the thickness of the relevant portion of the active layer can be selectively and adjustedly narrowed, and as a result, the power supply value between the source and drain ohmic electrode layers can be adjusted as required. It is possible to achieve uniform values and with good reproducibility.

Although the method of the above embodiment has been described using a semi-insulating gallium arsenide substrate, it can also be applied to other methods such as a shrimp layer substrate, and the same effects and effects can be obtained.

〔Effect of the invention〕

As detailed above, according to the method of the present invention, when manufacturing a compound semiconductor device, a recessed etched surface is placed in the active layer before the gate is formed to adjust the current value between the source and drain ohmic electrode layers. In the process, ion implantation is selectively and controlled into the recess-etched parts of the active layer, thereby making the recess-etched parts amorphous to the required thickness and forming an amorphous layer. After adjusting the current value to the required value.

Since this amorphous layer is removed to form a recess-etched surface, unlike the conventional method where the recess-etched surface is simply transferred by etching, there is no possibility of variations in the transfer amount. There is no fear,
The thickness of the corresponding part of the active layer can be selectively and adjusted with good controllability, and as a result, the current value between each source/drain ohmic electrode layer can be adjusted to the desired value uniformly and with good reproducibility. In addition, it does not damage the substrate wafer, and the method is relatively simple. i
It has excellent features such as being easy to implement.

[Brief explanation of the drawing]

Figure 1 (a) to f) shows the compound "1" according to the present invention.
'-5B according to an embodiment applying the method for manufacturing a conductor device
3A and 3B are cross-sectional views sequentially showing the manufacturing process of the FET,
In addition, FIGS. 2(a) to d) show the same results obtained by the conventional method.
FIGS. 3A and 3B are cross-sectional views sequentially showing the manufacturing process of the -3l IFET. ■... Semi-insulating gallium arsenide substrate, 2... Active layer, 3... Photoresist I pattern, 4.4...
...Each ohmic electrode layer corresponding to source and drain, 5.
. . . Recessed etched surface, 6. . . Gate electrode layer, 7.
...Ion implantation, 8...Amorphous layer.

Claims (1)

[Claims] When manufacturing a compound semiconductor device, in the step of adjusting the current value between each source/drain ohmic electrode layer by applying a recess-etched surface to the active layer before gate formation, ions are applied to the recess-etched portion of the active layer. The method further includes the step of performing implantation selectively and in a controlled manner to form an amorphous layer and adjusting the current value to a required value, and then removing the amorphous layer to form the recessed etched surface. A method for manufacturing a compound semiconductor device characterized by: