JPS63119251A - C-mos field effect transistor - Google Patents
C-mos field effect transistorInfo
- Publication number
- JPS63119251A JPS63119251A JP62257710A JP25771087A JPS63119251A JP S63119251 A JPS63119251 A JP S63119251A JP 62257710 A JP62257710 A JP 62257710A JP 25771087 A JP25771087 A JP 25771087A JP S63119251 A JPS63119251 A JP S63119251A
- Authority
- JP
- Japan
- Prior art keywords
- channel transistor
- diode
- type channel
- gate electrode
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000001681 protective effect Effects 0.000 abstract description 8
- 238000007599 discharging Methods 0.000 abstract description 3
- 108090000699 N-Type Calcium Channels Proteins 0.000 abstract 3
- 102000004129 N-Type Calcium Channels Human genes 0.000 abstract 3
- 108010075750 P-Type Calcium Channels Proteins 0.000 abstract 3
- 238000010586 diagram Methods 0.000 description 4
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Abstract
Description
【発明の詳細な説明】
本発明は相補型ＭＯＳ電界効果トランジスタ（以下、Ｃ
−ＭＯＳ ＰＥＴという）の入力保護回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary MOS field effect transistor (hereinafter referred to as C
- MOS PET) input protection circuit.
従来、絶縁ゲート電界効果トランジスタには、静電気や
高圧ノイズからゲート絶縁膜を保護するため、抵抗とダ
イオードから成る保護回路が設けられている。Conventionally, insulated gate field effect transistors are provided with a protection circuit consisting of a resistor and a diode to protect the gate insulating film from static electricity and high voltage noise.
第１図は代表的な入力保護回路を示す図であシ、Ｐチャ
ンネルトランジスタ１とＮチャンネルトランジスタ２か
ら成るＣ−ＭＯＳ ＦＥＴによるインバーター回路で
、それぞれのトランジスタ１．２のゲート電極は共通に
接続されて保護回路３を介して入力端子７に接続されて
いる。保護回路３は抵抗４、ダイオード５及び６によ多
形成されている。第１図の保護回路３に於て入力端子７
に高電圧が印加された時、ダイオード５及び６によシゲ
ート酸化膜上のゲート電極は低電圧にクランプされる。Figure 1 is a diagram showing a typical input protection circuit. It is an inverter circuit using a C-MOS FET consisting of a P-channel transistor 1 and an N-channel transistor 2, and the gate electrodes of each transistor 1 and 2 are connected in common. and is connected to the input terminal 7 via the protection circuit 3. The protection circuit 3 is made up of a resistor 4 and diodes 5 and 6. At the input terminal 7 in the protection circuit 3 shown in FIG.
When a high voltage is applied to diodes 5 and 6, the gate electrodes on the silicate gate oxide films are clamped to a low voltage.
すなわち、電源電圧ＶＤＤよシ大きな正の電圧が印加さ
れた時はダイオード５が動作し、接地電位Ｖ８８よシ低
い負の電圧が印加された時はダイオード６が動作する。That is, when a positive voltage greater than the power supply voltage VDD is applied, the diode 5 operates, and when a negative voltage lower than the ground potential V88 is applied, the diode 6 operates.
抵抗４はダイオード５及び６に流れる電流を制限しダイ
オード５，６の破壊を保護する働きをする。The resistor 4 serves to limit the current flowing through the diodes 5 and 6 and protect the diodes 5 and 6 from being destroyed.
このような保護回路３に於て、保護耐量を増加大きくし
てダイオードの破壊電流を上げれば良い。In such a protection circuit 3, the protection withstand capacity may be increased to increase the breakdown current of the diode.
しかしながらこれらの二つの対策はいずれも次の理由に
よシネ利益をもたらす。すなわち、ダイオード５及び６
には寄生の接合容量Ｃ１１及びＣｉ２が存在し、これら
の容量Ｃｉ１． Ｃｉｚを充放電するために時間の遅れ
が生ずる。ゲート電極を充放電する時定数は次式で与え
られる。However, both of these two measures bring about cine benefits for the following reasons. That is, diodes 5 and 6
There are parasitic junction capacitances C11 and Ci2, and these capacitances Ci1. A time delay occurs to charge and discharge Ciz. The time constant for charging and discharging the gate electrode is given by the following equation.
ｔ ＝Ｒ（Ｃｉｘ ＋ Ｃｉ２＋ Ｃｏｔ ＋ＣＯ２）
ここでＲは保護抵抗４の値、Ｃｏ１及び０．２はそれぞ
れＰチャンネルトランジスタ１及びＮチャンネルトラン
ジスタ２のゲート絶縁膜の容量である。t = R (Cix + Ci2+ Cot + CO2)
Here, R is the value of the protective resistor 4, and Co1 and 0.2 are the capacitances of the gate insulating films of the P-channel transistor 1 and the N-channel transistor 2, respectively.
容量Ｃ，１及びＣｏ２の大きさはチャンネル幅に比例す
る量であるが、通常のＣ−ＭＯＳ集積回路の入力ＮＯＴ
回路では接合容量Ｃｉ１及びＣｉ２に比べて無視できる
くらい小さい値である。容量Ｃｉ１及びＣｊｚはほぼ同
じ大きさで普通１〜３ＰＦに設計される。従って、従来
対策に従って、抵抗几あるいは接合容量Ｃｉ１． Ｃｉ
ｚを大きくするとインバータ回路の動作を遅らせること
になる。The sizes of capacitances C,1 and Co2 are proportional to the channel width, but the input NOT of a normal C-MOS integrated circuit
In the circuit, this value is negligibly small compared to the junction capacitances Ci1 and Ci2. The capacitances Ci1 and Cjz are approximately the same size and are usually designed to be 1 to 3 PF. Therefore, according to conventional measures, the resistance or junction capacitance Ci1. Ci
Increasing z will delay the operation of the inverter circuit.
以上、説明したように従来の入力保護回路３は保護耐量
を上げようとすると伝達遅延時間が長くなシ、スピード
を速くしようとすると保護耐量が小さくなるという欠点
があった。As described above, the conventional input protection circuit 3 has the disadvantages that when trying to increase the protection withstand capacity, the transmission delay time becomes long, and when trying to increase the speed, the protection withstand capacity decreases.
本発明の目的は従来の保護回路の欠点を除去し、高速で
動作し得る保護回路を備えたＣ−ＭＯＳ ＦＥＴを提供
する事にある。An object of the present invention is to eliminate the drawbacks of conventional protection circuits and provide a C-MOS FET equipped with a protection circuit that can operate at high speed.
本発明によれば、Ｐチャンネルトランジスタのゲート電
極から基板に電流を流す第１のダイオードと、このＰチ
ャンネルトランジスタのゲート電極と入力端子間に接続
された第１の保護抵抗と、Ｎチャンネルトランジスタの
基板からこのトランジスタのゲート電極に電流を流す第
２のダイオードと、このＮチャンネルトランジスタのゲ
ート電極と入力端子間に接続された第２の保護抵抗とか
ら成る入力保護回路を備えたＣ−ＭＯＳ ＦＥＴを得
る。According to the present invention, a first diode that allows current to flow from the gate electrode of the P-channel transistor to the substrate, a first protective resistor connected between the gate electrode of the P-channel transistor and the input terminal, and a first diode that allows current to flow from the gate electrode of the P-channel transistor to the substrate; A C-MOS FET equipped with an input protection circuit consisting of a second diode that allows current to flow from the substrate to the gate electrode of this transistor, and a second protection resistor connected between the gate electrode of this N-channel transistor and the input terminal. get.
以下、図面を参照して、本発明をよ）詳細に説明する。Hereinafter, the present invention will be explained in detail with reference to the drawings.
第２図は本発明の一実施例を示す等価回路図である。図
中、第１図と同じ引用数字は同じ成分を示す。第２図の
入力保護回路に於てはＰチャンネルトランジスタＩＫ接
続されるダイオード５及び抵抗４１はＮチャンネルトラ
ンジスタに接続されるダイオード６及び抵抗４２とそれ
ぞれ分離している。従って充放電の時定数は
Ｐチャンネル ｔｌ ＝Ｒ１（Ｃｔｔ ＋ＣＯＸ ）
Ｎチャンネル ｔ２＝Ｒ２（Ｃｉ２ ＋Ｃｏ２）とな
る。ここでｆＬ１＝Ｒ２、Ｃ１ｔ＝Ｃｉｚとすればｔｌ
＝４２となシ回路動作上問題はない。Ｃｉｔ 、 Ｃｉ
ｚ。FIG. 2 is an equivalent circuit diagram showing an embodiment of the present invention. In the figure, the same reference numerals as in FIG. 1 indicate the same components. In the input protection circuit of FIG. 2, the diode 5 and resistor 41 connected to the P-channel transistor IK are separated from the diode 6 and resistor 42 connected to the N-channel transistor, respectively. Therefore, the time constant of charging and discharging is P channel tl = R1 (Ctt + COX)
N channel t2=R2(Ci2 +Co2). Here, if fL1=R2 and C1t=Ciz, then tl
=42, there is no problem in circuit operation. Cit, Ci
z.
Ｒ，！、Ｒ，２を従来の保護回路のＣｉとＲに等しく設
計すれば保護耐量は同じで動作速度は２倍速くなる。R,! , R,2 are designed to be equal to Ci and R of the conventional protection circuit, the protection capability is the same and the operating speed is twice as fast.
又、動作速度を同じにすれば保護耐量を２倍に強くする
ことができる。第２図の回路は従来の回路に比べて保護
抵抗１ヶ多くなるだけであシ、例えば最小寸法のポリシ
リコン層でこの保護抵抗を形成すれば面積の増加はごく
わずかであシコスト高にはならない。Furthermore, if the operating speed is kept the same, the protection capability can be doubled. The circuit shown in Figure 2 only requires one more protective resistor than the conventional circuit.For example, if this protective resistor is formed from a polysilicon layer of the minimum size, the increase in area will be negligible and the cost will increase. No.
以上説明したように、本発明は高速を要求されるＣ−Ｍ
ＯＳ型電界効果トランジスタあるいは集積回路に好適な
入力保護回路を提供する。As explained above, the present invention is applicable to C-M which requires high speed.
An input protection circuit suitable for OS type field effect transistors or integrated circuits is provided.
第１図は従来の入力保護回路を示す等価回路図、第２図
は本発明の一実施例を示す等価回路図である。FIG. 1 is an equivalent circuit diagram showing a conventional input protection circuit, and FIG. 2 is an equivalent circuit diagram showing an embodiment of the present invention.
Claims (1)
ネルトランジスタの基板に電流を流す第１のダイオード
と、前記Ｐチャンネルトランジスタのゲート電極と入力
端子間に接続された第１の保護抵抗と、Ｎチャンネルト
ランジスタの基板から該Ｎチャンネルトランジスタのゲ
ート電極に電流を流す第２のダイオードと、前記Ｎチャ
ンネルトランジスタのゲート電極と前記入力端子間に接
続された第２の保護抵抗とを含むことを特徴とするＣ−
ＭＯＳ型電界効果トランジスタ。a first diode that allows current to flow from the gate electrode of the P-channel transistor to the substrate of the P-channel transistor; a first protection resistor connected between the gate electrode of the P-channel transistor and the input terminal; and a substrate of the N-channel transistor. and a second protection resistor connected between the gate electrode of the N-channel transistor and the input terminal.
MOS type field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62257710A JPS63119251A (en) | 1987-10-12 | 1987-10-12 | C-mos field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62257710A JPS63119251A (en) | 1987-10-12 | 1987-10-12 | C-mos field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63119251A true JPS63119251A (en) | 1988-05-23 |
| JPH0347745B2 JPH0347745B2 (en) | 1991-07-22 |
Family
ID=17310034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62257710A Granted JPS63119251A (en) | 1987-10-12 | 1987-10-12 | C-mos field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63119251A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1087441A2 (en) * | 1999-09-22 | 2001-03-28 | Kabushiki Kaisha Toshiba | Stacked mosfet protection circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4830189A (en) * | 1971-08-19 | 1973-04-20 | ||
| JPS5763861A (en) * | 1980-10-06 | 1982-04-17 | Nec Corp | Semiconductor device |
-
1987
- 1987-10-12 JP JP62257710A patent/JPS63119251A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4830189A (en) * | 1971-08-19 | 1973-04-20 | ||
| JPS5763861A (en) * | 1980-10-06 | 1982-04-17 | Nec Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1087441A2 (en) * | 1999-09-22 | 2001-03-28 | Kabushiki Kaisha Toshiba | Stacked mosfet protection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0347745B2 (en) | 1991-07-22 |
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