JPS63118232U - - Google Patents
Info
- Publication number
- JPS63118232U JPS63118232U JP1030387U JP1030387U JPS63118232U JP S63118232 U JPS63118232 U JP S63118232U JP 1030387 U JP1030387 U JP 1030387U JP 1030387 U JP1030387 U JP 1030387U JP S63118232 U JPS63118232 U JP S63118232U
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- semiconductor chip
- contact
- electrode
- insulating material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 2
- 239000011521 glass Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Die Bonding (AREA)
Description
第１図は本考案の一実施例の断面図、第２図は
第１図に示すチツプマウント部の面を垂直方向か
ら見た平面図、第３図は本考案の他の実施例の断
面図、第４図は従来のミニフラツトパツケージト
ランジスタの一部破裁斜視図である。 １，２，１１，１２……円柱状電極、１ａ……
半片電極、１ｂ……絶縁材、１ｃ……楕円形端面
、１ｄ……つば、３，６……半導体チツプ、３ａ
……盛上げ電極、４……ガラス管、５，７……リ
ード、８……連結線、９……封止樹脂。
第１図に示すチツプマウント部の面を垂直方向か
ら見た平面図、第３図は本考案の他の実施例の断
面図、第４図は従来のミニフラツトパツケージト
ランジスタの一部破裁斜視図である。 １，２，１１，１２……円柱状電極、１ａ……
半片電極、１ｂ……絶縁材、１ｃ……楕円形端面
、１ｄ……つば、３，６……半導体チツプ、３ａ
……盛上げ電極、４……ガラス管、５，７……リ
ード、８……連結線、９……封止樹脂。
Claims (1)
- 突合せ端面間に半導体チツプをはさむ二つの円
柱状電極のうち一方の円柱状電極は絶縁材をはさ
んで縦方向に二つの半片電極に分かれており、か
つ、前記半片電極のそれぞれは前記半導体チツプ
の表面上の二つの盛上げ電極にそれぞれ接触し、
他方の電極は前記半導体チツプの裏面と接触し、
前記突合せ部の外周を絶縁管で包み封止してなる
ことを特徴とするトランジスタ。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1030387U JPS63118232U (ja) | 1987-01-26 | 1987-01-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1030387U JPS63118232U (ja) | 1987-01-26 | 1987-01-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63118232U true JPS63118232U (ja) | 1988-07-30 |
Family
ID=30796469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1030387U Pending JPS63118232U (ja) | 1987-01-26 | 1987-01-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63118232U (ja) |
-
1987
- 1987-01-26 JP JP1030387U patent/JPS63118232U/ja active Pending