JPS63117538A - Receiver - Google Patents

Abstract

PURPOSE:To make the investigation of data by every byte by a CPU unnecessary, and to realize the fast transfer of the data, by detecting a control character stipulated by a synchronous communication system in DMA transfer, and informing it to the CPU. CONSTITUTION:Synchronization between a control block and a data block sent from a serial line to a receiver is taken by a communication control LSI13, and a SYN character is removed. Afterwards, the block is changed to a reception data, and is transferred byte by byte to a memory 2 by a DMAC4. During the above DMAC transfer, the data at a time when a DACK signal to the LSI13 becomes active is detected at a control character detection circuit CRWD6 via a data bus 12. An interruption signal is generated when the data is the control character stipulated at the CRWD6, and it is informed to the CPU1 via a signal line 21, an interruption controller INTC5, and a signal line 24. And the CPU1 finds a transfer opposite address while executing an interruption processing, and processes the data with a stipulated communication procedure.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a receiving device using a byte-oriented synchronous communication method, and particularly to improving its data receiving ability.

[Conventional technology]

In recent years, with the development of serial transmission technology and integrated circuit technology,
Communication control large-scale integrated circuits (hereinafter referred to as communication control LSIs) that handle various protocols have become commercially available at relatively low prices and are being used in various data communication devices.

Figure 5 shows, for example, transistor technology (November 1985 C
FIG. 2 is a block diagram showing a conventional receiving device shown in "Special feature: All about microcomputer data communication technology: Serial interface design method" published on pages 355 to 384 of Q Publishers.

In the figure, 1 is a central processing unit (hereinafter referred to as CPU);
2 is a memory, 3 is a multi-protocol serial controller (hereinafter referred to as MPSC) as a communication control LSI that receives data sent through a serial line, 4
The MPSC3 uses direct memory access (hereinafter referred to as DM).
A DMA controller (hereinafter referred to as DMAC) that controls DMA transfer between MPSC 3 and memory 2 when used in mode A), 5 is MPSC 3 and DMAC 4
This is an interrupt controller (hereinafter referred to as INTC) that concentrates and controls interrupt signals from such sources.

Further, each of these devices is connected by a control bus 11 and a data bus 12, and furthermore, an MPS
DMAC4 is connected between C3 and INTC5 by signal line 22.
A signal line 23 connects INTC5 and C
The 0th order operation in which the PU1 is connected to the signal line 24 and an interrupt signal is transmitted will be described. Control methods for the receiving apparatus having such a configuration include a program control method and a DMA control method. In the program control method, the CPU 1 performs polling or the signal line 22,
Interrupt processing for interrupts from the MPSC 3 via the INTC 5 and signal line 24 directly controls the control bus 11 and controls the MPSC 3 and memory 2 via the data bus 12.
This method transfers data between On the other hand, in the DMA control method, DMAC4 receives a DMA request from MPSC3.
By requesting and acquiring the right to use the control bus 11 from the CPU, the MP
This is a method in which all data transfer between SC3 and memory 2 is performed.

The DMA method is superior to the program method in terms of high throughput requirements and the reduction of load for input/output control (hereinafter referred to as F0 control).
C (High-Level Data LinkCo
ntrol), S DLC(S)'nchron
In the case of a bit-oriented synchronous communication method such as DataLink Control), a DMA control method is often used.
c (Mono Synchronous Commun
icat ions )% Bi 5ync (Bi
narySynchronousCommunicat
In the case of a byte-oriented synchronous communication method such as . J
pl) 7201A MPSCj--Zers, Manual (Published by NEC Corporation) Like P75-P79,
A DMA method is not used, but a program control method using interrupts or the like is used. In this case, every time one byte of data sent via the serial line is received by the MPSC 3, an interrupt is raised to the CPU via the signal line 22, the NTC 5, and the signal line 24. CPU
1 performs data transfer between the MPSC 3t and the memory 2 while searching whether the content of the data corresponds to the control characters shown in FIG. With the above configuration, in the byte-oriented synchronous communication method, the CPU
It is not possible to reduce the load of 1, and even if a DMA method is used, it is necessary to search the data area byte by byte after DMA transfer.For the same reason, an increase in the number of lines and a reduction in throughput There was a problem in that it was not possible to respond to demands such as increases.

This invention was made to solve the above problems, and even in the byte-oriented synchronous communication system, DM
It is an object of the present invention to obtain a high-throughput receiving device that can use the A method and reduce the load on the CPU.

[Means for solving problems]

In order to achieve the above object, the receiving device according to the present invention has the following features:
Set the multiprotocol serial controller to DMA mode, transfer the received data by DMA, and
The data transferred during MA transfer is read on the bus, and when the content is a control character specified by the byte-oriented synchronous communication method, the control character detection circuit issues an interrupt signal to the CPU. It is.

Further, in a receiving device according to another aspect of the present invention, the control character detection circuit issues the interrupt signal to the CPU and latches the contents of the control character and the transfer address.

[Effect]

By raising an interrupt signal to the CPU during DMA transfer to indicate that a control character has been received, the receiving device according to the present invention enables the CPU to efficiently search for the control character without having to search the data one byte at a time. shall be.

Furthermore, the receiving device according to another aspect of the present invention further includes the content of the control character and the transfer destination address. 5. It is possible to read this n from the CPU under I10 control.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 to 5, 11, 12, and 22 to 24 are the same as those in the prior art denoted by the same reference numerals in FIG. 5, and therefore their explanation will be omitted. 6 is connected to the data bus 12, and the MPS
A control character detection circuit (hereinafter referred to as CRWD) generates an interrupt signal when the data being transferred by DMA between C3 and memory 2 is a control character specified by the byte-oriented synchronous communication method.
21 is a signal line that transmits the interrupt signal t-CPUI from the CRWD6.

Next, the operation will be explained. Figure 3 1d Monos)
FIG. 2 is an explanatory diagram showing a basic block format of a byte-oriented synchronous communication method such as the 'nc method or the B157nc method. The control blocks and data blocks sent via the serial line υ in the form of Figure 3 a and b are the MPS
Synchronization is established at C3 and the SYN character is removed. The subsequent blocks are DMAed one byte at a time with the received data.
It is transferred to memory 2 by C4. The CRWD 6 detects data via the data bus 12 during DMA transfer, that is, when the DACK signal from the DMAC 4 to the MPSC 3 is active, and when it is a control character defined in FIG. 4, generates an interrupt signal. CPUI K is notified via the signal line 21, INTC5, and signal line 24. CPU1
It is learned that a control character has been received by an interrupt from a computer, and during the interrupt processing, the transfer destination address of the control character is learned by reading the current address register of DMAC4, and the transfer destination address is determined according to the communication procedure defined by each protocol. Process the data.

Next, another embodiment of the present invention will be described with reference to the drawings. In Figure 2, 1~6,11°12.21~2
4 is the same as the one with the same reference numeral in FIG. 1, so the explanation thereof will be omitted. 7.8 is a latch circuit that latches the contents of the transfer data and the transfer destination address when the CRWD 6 generates an interrupt signal, and these are connected to the control bus 11 and the data bus 12, respectively.

Next, the operation will be explained. The CRWD 6 detects a predetermined control character, generates an interrupt signal, and operates in the same manner as shown in FIG. 1 until the CPU 1 is notified. When this interrupt signal is generated, the content of the transfer data, that is, the control character, is latched in the latch circuit 7, and the transfer address is latched in the latch circuit 8.

The CPU 1 learns that the control character has been received by the interrupt, reads the contents of the latch circuits 7 and 8 under the control of I10, learns all of the control characters and the transfer destination address, and executes the respective protocols. Data is processed using the communication procedures specified in .

Note that the timing for reading the contents of the latch circuits T and 8 only needs to be until the next control character is received.

In addition, in the embodiments of both the inventions described above, the number of channels accommodated is one.
Although only channels have been described, multiple channels can be accommodated by cascading interrupt controllers. In that case, in another invention of this invention,
A latch circuit must be provided for each channel.

〔Effect of the invention〕

As described above, according to the present invention, the control characters specified by the synchronous communication method are detected during DMA transfer and the K is set so that the CPU can be notified. High-speed transfer is possible, and CP
This has the effect of greatly reducing the load on U. Further, according to another aspect of the present invention, since the content of the detected control character and the transfer address are latched,
The timing to read the control characters and transfer destination address is as follows.
Since it only needs to be done until the next control character is received, it has the effect of providing more time than a method such as immediately reading the current address register of the DMA controller by interrupt processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a receiving device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a receiving device according to another embodiment of the present invention, and FIG. 3 is a byte-oriented synchronous communication system. Fig. 4 is an explanatory diagram showing a part of the control characters of the communication method.
FIG. 5 is a block diagram showing a conventional receiving device. 1 is the CPU, 2H memory, 3HMPSC (communication control LSI), 4uDMAC, 1ltcRWD, 7°8 is the latch circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant: Mitsubishi Electric Corporation (2 others) Figure 1 Figure 2

Claims (2)

[Claims] (1) In a receiving device in which a communication control large-scale integrated circuit receives data sent from a serial line using a byte-oriented synchronous communication method, the received data is transferred from the communication control large-scale integrated circuit to a memory. and a direct memory access controller for detecting the content of the data during direct memory access transfer, and when the content is a control character specified in the byte-oriented synchronous communication method, the central A receiving device comprising a control character detection circuit that outputs an interrupt signal to a processing device. (2) In a receiving device in which a communication control large-scale integrated circuit receives data sent from a serial line using a byte-oriented synchronous communication method, the received data is transferred from the communication control large-scale integrated circuit to a memory. and a direct memory access controller for detecting the content of the data during direct memory access transfer, and when the content is a control character specified in the byte-oriented synchronous communication method, the central A receiving device comprising: a control character detection circuit that outputs an interrupt signal to a processing device; and a latch circuit that latches the contents of the control character and a transfer destination address.