JPS63114151A - Resin sealed semiconductor device - Google Patents

Resin sealed semiconductor device

Info

Publication number
JPS63114151A
JPS63114151A JP25850686A JP25850686A JPS63114151A JP S63114151 A JPS63114151 A JP S63114151A JP 25850686 A JP25850686 A JP 25850686A JP 25850686 A JP25850686 A JP 25850686A JP S63114151 A JPS63114151 A JP S63114151A
Authority
JP
Japan
Prior art keywords
resin
semiconductor chip
sealed
frame
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25850686A
Other languages
Japanese (ja)
Inventor
Shigeki Sako
酒匂 重樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP25850686A priority Critical patent/JPS63114151A/en
Publication of JPS63114151A publication Critical patent/JPS63114151A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent a contact with a resin of a semiconductor device, and to eliminate a malfunction due to resin stress and the deterioration is reliability by a method wherein a hollow section is formed, an electrode body and a cap sealing a semiconductor chip are mounted, the semiconductor chip and an inner lead section are connected and the inside of the cap is sealed with the resin, leaving an outer lead section for a lead frame. CONSTITUTION:A frame-shaped electrode body 6 is bonded with adhesives 7 so as to surround the periphery of a semiconductor chip 5 to a square shape on a bed section 1. Electrode groups on the inside of a groove section 62 and electrode groups on the semiconductor chip 5 are connected by wires 9 for leading out electrodes, and electrode groups on the outside of a groove section 61 and inner lead section 2 groups are connected by wires 10 for leading out electrodes. The semiconductor chip 5 and the wires 9 for leading out the electrodes are sealed under the state in which the periphery of the semiconductor chip 5 and the wires 9 is hollowed, and the whole body except outer lead sections 3 are sealed with a resin 11 as the hollow state is kept as it is. Accordingly, the semiconductor chip 5 is not brought into contact with the resin 11, thus removing the malfunctioning of the semiconductor chip 5 caused by stress of the resin 11 and the deterioration of reliability.

Description

【発明の詳細な説明】 [発明の目的コ (産業上の利用分野) 本発明は樹脂封止型半導体装置に係り、特に半導体チッ
プと樹脂との接触を防止する封止構造に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) The present invention relates to a resin-sealed semiconductor device, and particularly to a sealing structure that prevents contact between a semiconductor chip and a resin.

(従来の技術) 従来の樹脂封止型半導体装置は、第2図に示すようにリ
ードフレームのベッド部21上に接着された半導体チッ
プ22および電極取り出しワイヤ23がリードフレーム
のインナーリード部24と共に樹脂25により封止され
ている。
(Prior Art) In a conventional resin-sealed semiconductor device, as shown in FIG. It is sealed with resin 25.

しかし、上記のような封止構造は、半導体チッブ22と
樹脂25とが接触しているので、樹脂応力により半導体
チップ22の動作不良を発生する。
However, in the sealing structure as described above, since the semiconductor chip 22 and the resin 25 are in contact with each other, the semiconductor chip 22 may malfunction due to resin stress.

これを避けるため、樹脂25の応力を低減すると、一般
に樹脂特性上、熱伝導率が減少し、半導体チップ22の
放熱効果におのずと限度が発生する。
In order to avoid this, if the stress of the resin 25 is reduced, the thermal conductivity will generally decrease due to the characteristics of the resin, and the heat dissipation effect of the semiconductor chip 22 will naturally have a limit.

一方、チップ表面を電気信号が伝搬する半導体チップ(
マイクロ波チップ等)については、チップ表面と封止材
料とが接触しないように、従来はチップ周囲を中空状態
にすることが可能なセラミックパッケージや金属封止の
パッケージが用いられてきた。しかし、このようなセラ
ミックパッケージや金属封止のパッケージはパッケージ
自体の材料コストが高いので、半導体装置のコストダウ
ンを図る上で大きな障害となっている。
On the other hand, semiconductor chips (
For microwave chips (microwave chips, etc.), ceramic packages or metal-sealed packages that can be made hollow around the chip have conventionally been used to prevent contact between the chip surface and the sealing material. However, such ceramic packages and metal-sealed packages have high material costs for the packages themselves, which is a major obstacle in reducing the cost of semiconductor devices.

(発明が解決しようとする問題点) 本発明は、上記したように樹脂応力により半導体チップ
の動作不良が発生するという問題点、セラミックパッケ
ージ等はパッケージ材料のコストが高いという問題点を
解決すべくなされたもので、半導体チップの動作の信頼
性が高く、封止材料のコストが安く、低価格化が可能な
樹脂封止型半導体装置を提供することを目的とする。
(Problems to be Solved by the Invention) The present invention aims to solve the above-mentioned problem that semiconductor chips malfunction due to resin stress and the problem that the cost of package materials for ceramic packages is high. It is an object of the present invention to provide a resin-sealed semiconductor device which has a highly reliable operation of a semiconductor chip, uses a low cost sealing material, and can be manufactured at a low price.

[発明の構成] (問題点を解決するための手段) 本発明の樹脂封止型半導体装置は、リードフレームのベ
ッド部上に設けられた半導体チップの周囲に中空部を残
して半導体チップを囲んで密閉するように電極体および
キャップを設け、半導体チップとインナーリード部とを
上記電極体を介して電極取り出し用ワイヤにより接続し
、リードフレームのアウターリード部を残して他の部分
を樹脂により封止してなることを特徴とする。
[Structure of the Invention] (Means for Solving the Problems) The resin-sealed semiconductor device of the present invention surrounds the semiconductor chip by leaving a hollow space around the semiconductor chip provided on the bed portion of the lead frame. An electrode body and a cap are provided so that the electrode body and the cap are sealed, and the semiconductor chip and the inner lead part are connected via the electrode body with a wire for taking out the electrode, and the other parts are sealed with resin, leaving the outer lead part of the lead frame. It is characterized by stopping.

(作 用) 半導体装置はキャップにより覆われていて樹脂とは接触
していないので、樹脂応力による動作不良、信頼性低下
をまねくおそれがない。しかも、半導体チップ周辺に中
空部を残して密閉されているので、外部からの水分の侵
入に対するシールド効果が得られる。また、チップ表面
を電気信号が伝搬するような半導体装置であっても、チ
ップ表面は樹脂に接触していないので電気的特性が安定
に得られる。また、樹脂は安価であるので、半導体装置
を安価に実現することが可能になる。
(Function) Since the semiconductor device is covered by the cap and is not in contact with the resin, there is no risk of malfunction or decreased reliability due to resin stress. Furthermore, since the semiconductor chip is sealed leaving a hollow space around it, a shielding effect against moisture intrusion from the outside can be obtained. Furthermore, even in a semiconductor device in which an electrical signal propagates on the chip surface, stable electrical characteristics can be obtained because the chip surface is not in contact with the resin. Furthermore, since resin is inexpensive, it becomes possible to realize semiconductor devices at low cost.

(実施例) 以下、図面を参照して本発明の一実施例を詳細に説明す
る。
(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第1図に示す樹脂封止型半導体装置において、1.2.
3はそれぞれリードフレームのアイランド部(ベッド部
)、インナーリード部、アウターリード部である。、上
記ベッド部1上の中央部には接着剤4により半導体チッ
プ5が接着されており、上記ベッド部1上で半導体チッ
プ5の周りを方形に囲むように枠状の電極体6が接着剤
7により接着されている。この電極体6は、絶縁材料か
らなる枠体61の上面中央部に後述するキャップ8を栽
せるための溝部62が形成され、上記枠体61の上面の
溝部62の両側部分の電極部相互間を電気的に接続する
ように複数の導電体63が枠体61内に埋設されている
。溝部62の内側の電極群と半導体チップ5上の電極群
との間は電極取り出し用ワイヤ9により接続されており
、溝部6、の外側の電極群とインナーリード部2群との
間は電極取り出し用ワイヤ10により接続されている。
In the resin-sealed semiconductor device shown in FIG. 1, 1.2.
3 are an island portion (bed portion), an inner lead portion, and an outer lead portion of the lead frame, respectively. A semiconductor chip 5 is bonded to the central portion of the bed portion 1 with an adhesive 4, and a frame-shaped electrode body 6 is bonded with the adhesive so as to surround the semiconductor chip 5 in a rectangular manner on the bed portion 1. 7. This electrode body 6 has a groove 62 formed in the center of the upper surface of a frame 61 made of an insulating material, in which a cap 8 described later is formed, and a groove 62 on both sides of the groove 62 on the upper surface of the frame 61 between the electrode parts. A plurality of conductors 63 are embedded within the frame 61 so as to electrically connect them. The electrode group inside the groove 62 and the electrode group on the semiconductor chip 5 are connected by an electrode extraction wire 9, and the electrode group outside the groove 6 and the inner lead part 2 group are connected by an electrode extraction wire 9. are connected by a wire 10.

さらに、前記枠体6、上に箱状キャップ8の開口端部が
載置されることによって、半導体チップ5および電極取
り出し用ワイヤ9の周囲が中空状になった状態で密閉さ
れており、この中空状態を保ったままアウターリード部
3以外の全てが樹脂11により封止されている。
Furthermore, by placing the open end of the box-shaped cap 8 on the frame 6, the periphery of the semiconductor chip 5 and the electrode extraction wire 9 is sealed in a hollow state. Everything except the outer lead portion 3 is sealed with resin 11 while maintaining a hollow state.

上記封止構造の半導体装置によれば、半導体チップ5の
電極とインナーリード部2とは電極体6を介して電極取
り出し用ワイヤ9,1oにより所要の電気的接続が施さ
れており、半導体チップ5はキャップ8により覆われて
いて樹脂11とは接触していないので、樹脂11の応力
により半導体チップ5の動作不良、信頼性低下をまねく
おそれはな、い。したがって、樹脂11の応力を低減さ
せる必要もなく、樹脂11の熱伝導率の低下、放熱効果
の低下をまねくおそれもない。しかも、キャップ8およ
び電極体6により半導体チップ5を囲んでいるので、外
部からの水分の侵入に対するシールド効果が得られるよ
うになり、半導体チップ5の信頼性が向上する。また、
チップ表面を電気信号が伝搬するような半導体チップ5
であっても、チップ表面は樹脂11に接触しないように
保護されているので、半導体チップ5の電気的特性の安
定化の点で有効であり、しかも樹脂11はセラミックパ
ッケージや金属封止パッケージに比べて安価(1/10
0〜1/1000程度)であり、大幅なコストダウンが
可能である。
According to the semiconductor device having the above-mentioned sealing structure, the electrodes of the semiconductor chip 5 and the inner lead portion 2 are electrically connected via the electrode body 6 by the wires 9, 1o for taking out the electrodes, and the semiconductor chip Since the semiconductor chip 5 is covered by the cap 8 and is not in contact with the resin 11, there is no risk that the stress of the resin 11 will cause malfunction or decrease in reliability of the semiconductor chip 5. Therefore, there is no need to reduce the stress of the resin 11, and there is no risk of a decrease in the thermal conductivity of the resin 11 or a decrease in the heat dissipation effect. Furthermore, since the semiconductor chip 5 is surrounded by the cap 8 and the electrode body 6, a shielding effect against intrusion of moisture from the outside can be obtained, and the reliability of the semiconductor chip 5 is improved. Also,
A semiconductor chip 5 in which an electrical signal propagates on the chip surface
However, since the chip surface is protected from coming into contact with the resin 11, it is effective in stabilizing the electrical characteristics of the semiconductor chip 5. Moreover, the resin 11 is suitable for ceramic packages and metal sealed packages. Cheaper compared to (1/10
(approximately 0 to 1/1000), making it possible to significantly reduce costs.

なお、上記実施例の樹脂封止型半導体装置の信頼性につ
いて、熱サイクル数対製熱応力による不良率および加湿
時間対湿気による不良率を実測したところ、従来例の樹
脂封止半導体装置に比べて大幅に改善されていることが
確認された。
Regarding the reliability of the resin-sealed semiconductor device of the above example, we actually measured the defective rate due to the number of thermal cycles versus manufacturing thermal stress and the defective rate due to humidification time versus humidity. It was confirmed that there was a significant improvement.

なお、上記実施例において、キャップ8を導体により形
成し、電極体6における複数の電極部のうちの1つ、に
導電性接着剤により電気的に接続し、この電極部を電極
取り出しワイヤにより接地用のインナーリード部に接続
するようにすれば、半導体チップ5を外部電界から保護
することができ、信頼性を一層向上させることができる
In the above embodiment, the cap 8 is formed of a conductor, electrically connected to one of the plurality of electrode parts in the electrode body 6 with a conductive adhesive, and this electrode part is grounded with an electrode lead wire. If the semiconductor chip 5 is connected to a dedicated inner lead portion, the semiconductor chip 5 can be protected from external electric fields, and reliability can be further improved.

なお、本発明は上記実施例に限られるものではなく、キ
ャップ8、電極体6の形状を変形してもよく、両者を一
対的に構成してもよい。
Note that the present invention is not limited to the above-mentioned embodiment, and the shapes of the cap 8 and the electrode body 6 may be modified, and both may be configured as a pair.

[発明の効果〕 上述したように本発明の樹脂封止型半導体装置によれは
、半導体チップの動作の信頼性が高く、封止材料のコス
トが安く、低価格化が可能になるなどの効果が得られる
[Effects of the Invention] As described above, the resin-sealed semiconductor device of the present invention has the following effects: the operation of the semiconductor chip is highly reliable, the cost of the sealing material is low, and the cost can be reduced. is obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の樹脂封止型半導体装置の一実施例を示
す断面図、第2図は従来の樹脂封止型半導体装置を示す
断面図である。 1・・・リードフレームのベッド部、2・・・リードフ
レームのインナーリード部、3・・・リードフレームの
アウターリード部、5・・・半導体チップ、6・・・電
極体、6□・・・枠体、62・・・溝部、63・・・導
電体、8・・・キャップ、9.10・・・電極取り出し
用ワイヤー、11・・・樹脂。
FIG. 1 is a sectional view showing an embodiment of the resin-sealed semiconductor device of the present invention, and FIG. 2 is a sectional view showing a conventional resin-sealed semiconductor device. DESCRIPTION OF SYMBOLS 1... Bed part of lead frame, 2... Inner lead part of lead frame, 3... Outer lead part of lead frame, 5... Semiconductor chip, 6... Electrode body, 6□... - Frame body, 62...Groove portion, 63...Conductor, 8...Cap, 9.10...Wire for taking out the electrode, 11...Resin.

Claims (4)

【特許請求の範囲】[Claims] (1)リードフレームのベッド部上に設けられた半導体
チップの周囲に中空部を残して半導体チップを囲んで密
閉するように電極体およびキャップを設け、半導体チッ
プとリードフレームのインナーリード部とを上記電極体
を介して電極取り出し用ワイヤにより接続し、リードフ
レームのアウターリード部を残して他の部分を樹脂によ
り封止してなることを特徴とする樹脂封止型半導体装置
(1) An electrode body and a cap are provided to surround and seal the semiconductor chip, leaving a hollow space around the semiconductor chip provided on the bed part of the lead frame, and connect the semiconductor chip and the inner lead part of the lead frame. A resin-sealed semiconductor device, characterized in that the electrode body is connected via an electrode lead wire, and the lead frame is sealed with a resin except for the outer lead portion of the lead frame.
(2)前記キャップは導体からなり、接地用インナーリ
ードに接続されることを特徴とする前記特許請求の範囲
第1項記載の樹脂封止型半導体装置。
(2) The resin-sealed semiconductor device according to claim 1, wherein the cap is made of a conductor and is connected to a grounding inner lead.
(3)前記電極体は、方形状の絶縁性枠体の上面中央部
に溝部が形成され、上記枠体の上面における上記溝部の
両側部分の電極部相互間を電気的に接続するように上記
枠体内に導電体が埋設されてなり、前記リードフレーム
のベッド部上で半導体チップを囲む位置に接着されてい
ることを特徴とする前記特許請求の範囲第1項記載の樹
脂封止型半導体装置。
(3) In the electrode body, a groove is formed in the center of the upper surface of a rectangular insulating frame, and the electrode body is configured to electrically connect the electrode parts on both sides of the groove on the upper surface of the frame. The resin-sealed semiconductor device according to claim 1, wherein a conductor is embedded in the frame and is bonded to a position surrounding the semiconductor chip on the bed portion of the lead frame. .
(4)前記枠体の上面部の溝部にキャップの開口端部が
載置されていることを特徴とする前記特許請求の範囲第
3項記載の樹脂封止型半導体装置。
(4) The resin-sealed semiconductor device according to claim 3, wherein the open end of the cap is placed in the groove in the upper surface of the frame.
JP25850686A 1986-10-31 1986-10-31 Resin sealed semiconductor device Pending JPS63114151A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25850686A JPS63114151A (en) 1986-10-31 1986-10-31 Resin sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25850686A JPS63114151A (en) 1986-10-31 1986-10-31 Resin sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPS63114151A true JPS63114151A (en) 1988-05-19

Family

ID=17321154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25850686A Pending JPS63114151A (en) 1986-10-31 1986-10-31 Resin sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS63114151A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0339851U (en) * 1989-08-29 1991-04-17
US5173766A (en) * 1990-06-25 1992-12-22 Lsi Logic Corporation Semiconductor device package and method of making such a package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0339851U (en) * 1989-08-29 1991-04-17
US5173766A (en) * 1990-06-25 1992-12-22 Lsi Logic Corporation Semiconductor device package and method of making such a package

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