JPS63113635A - Data processor - Google Patents

Abstract

PURPOSE:To facilitate data transfer between a conventional program before address expansion and a program after the address expansion and to secure the compatibility with a conventional data processor by expanding address length without varying data length. CONSTITUTION:When conventional data length is (d) bits long and general register length is (r) bits long, the data length is (d) bits long regardless of the effective length of an operand length and data is processed by a (d)-bit arithmetic means. Further, the data is loaded and stored by a (d)-bit main storage access means. The data is transferred directly between the programs which differ in operand address effective length and the compatibility with the conventional data process is easily secured. Further, the operand address is generated by reading the effective bit length of the operand address out of an (r)-bit general register by an address generating circuit 4 according to the effective length of the operand address. Consequently, main storage addresses which exceed the (d)-bit length can be expanded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to data processing using a large-capacity main memory, and in particular to expanding main memory addresses while ensuring compatibility with conventional data processing devices. The present invention relates to a suitable data processing device.

[Conventional technology]

A conventional technique for expanding the main memory address of a data processing device is described in the IBM System/370 Extemporets Architecture Principles of Operation (1983), Volume 5, manual of IBM Corporation.
- pages 4 to 5-10 and pages 7-1 to 7-8
Page (I BMSystem/ 370 Pr1nci
ples of 0operation (1983) p.
p, 5-4 to 5-10. PP, 7-1 to 7-8). This conventional technology uses a virtual memory method and has two virtual address length modes, a 24-bit mode and a 31-bit mode, and has fixed-point data and
The data length of logical data etc. is 32 bits. The general-purpose register has a length of 32 bits, and data operation instructions such as addition and subtraction are prepared for all 32 bits of the general-purpose register. Since no address operation instruction is provided, address operation is executed using this data operation instruction. When a data operation instruction is executed, all 32 bits of the general-purpose register are read, the operation is performed, and the resulting 32 bits are written to the general-purpose register. A main memory access instruction whose operand is in main memory specifies two general-purpose registers as a pace register and an index register for generating operand addresses in the instruction code. The main memory access virtual address is generated by adding the contents of the pace register and index register and the displacement in the instruction code. At this time, it is specified that the upper part of the addition result that exceeds the address length is ignored, so normally this addition is performed only from the general-purpose registers, which are the pace register and the index register, to the essential parts of the virtual address, depending on the virtual address length mode. Read and execute. That is, in the 24-bit mode, 24 bits are read from the least significant bit of the general-purpose register to the most significant bit, and in the 31-bit mode, 31 bits are read from the least significant bit to the most significant bit of the general-purpose register.

The load instruction, which is a main memory access instruction, reads 32-bit data from the main memory at the address generated as described above, regardless of the virtual address length mode, and writes it into the entire 32-bit general-purpose register.

The virtual address length mode is indicated by a 1-bit mode pit in a register called the program status word that holds the state of the processing unit. The mode pit can be changed by a mode change branch instruction, and by changing the mode pit, the virtual address length mode is changed.

[Problem that the invention seeks to solve]

The conventional technology described above does not take into consideration the case where the address extension width is large and the extended address length exceeds the data length before extension, that is, the bit length of the general-purpose register.

In that case, if the conventional technology is used, the data length must be extended beyond the extended address, and the data operation instruction must be made to execute an operation on the extended data length.

When the data length is expanded, it becomes difficult to exchange data between the conventional program created before the expansion and the new program created after the expansion. For example, the data length is 32 in a conventional program.
If the new program is 64 bits, in order to pass data from the conventional program to the new program, it is necessary to convert the 32-bit data to 64-bit data. Therefore, there is a problem in that increasing the data length makes it difficult to guarantee compatibility.

Furthermore, as described in Japanese Patent Publication No. 60-53895, a second conventional technique for extending a main memory address is to generate an extended address and extend the address when the address extension mode is specified and an operand address is to be generated. If mode is not specified or if you want to generate an instruction address, use
The extended upper part of the extended address was set to ``0''.

Since this conventional technique does not extend instruction addresses, it has the advantage that the amount of change in conventional software can be reduced and main memory addresses can be easily expanded. However, the case where the address extension width exceeds the data length is not taken into consideration, and there is a drawback similar to that of the first conventional technique.

An object of the present invention is to provide a data processing apparatus that guarantees compatibility with conventional data processing apparatuses and that makes it possible to efficiently expand main memory addresses.

[Means for solving problems]

The above purpose is to provide a means for specifying any one of a plurality of effective lengths of an a-bit operand address, a group of r-bit general-purpose registers with a pit or more, and a single or plural number of registers specified by an arithmetic instruction in response to an arithmetic instruction. a of the first general-purpose register of
an arithmetic means that reads the least significant d bits smaller than the bit, performs an operation, and writes the result of the d bit operation to the least significant d bits of a second general-purpose register specified by the arithmetic instruction; Address generation means for generating an a-bit operand address by reading a specified effective length of an operand address from one or more third general-purpose registers specified by a memory access instruction; and an operand address generated by the address generation means. main memory access means that reads d bits from the main memory and writes them to a fourth general-purpose register specified by the main memory access command in response to the main memory, or reads the least significant d bits of the fourth general-purpose register and writes them to the main memory. This is achieved by providing

[Effect]

If the conventional data length is d bits and the general-purpose register length is r bits, the data length is d bits regardless of the effective length of the operand address, operations on data are performed by d-bit arithmetic means, and data is loaded and stored. is d
Since this is performed by bit main memory access means, data can be directly exchanged between programs with different operand address effective lengths, and compatibility with conventional data processing devices can be easily guaranteed. The operand address is generated by the address generation means that reads the bit length corresponding to the effective length of the operand address from the r-bit general-purpose register according to the effective length of the operand address, so it is possible to extend the main memory address beyond d bits. become.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 9. This embodiment employs a virtual memory system and has three virtual address length modes (hereinafter referred to as address modes): 24 bits, 31 bits, and 48 bits. Therefore, the effective length of the operand address is 24 bits, 31 bits, or 48 bits depending on each mode. FIG. 9 shows virtual storage areas that can be accessed for each address mode. In the 24-bit mode, it is possible to access the area 201 of virtual addresses 0 to 2241. In the 31-bit mode, it is possible to access the area 202 of virtual addresses 0 to 2311. In the 48-bit mode, it is possible to access the area 203 of virtual addresses 0 to 24B-1. . The data length is 32 bit mode regardless of the address mode.

FIG. 1 is a configuration diagram of this embodiment. This embodiment includes an instruction register 1 that holds the instruction code to be executed, an instruction decoder 2, a program state word (PSW) 3, a flip-flop V18 that controls the bit length of address operations, and a real address of the operand that is generated from the instruction code. Address generation circuit 4, main memory 5, fetch data register 6.16
64-bit length general-purpose register 7. 64-bit address calculation circuit 8. 32-bit data calculation circuit 9, register 1
0, selector 11, 20, 21, AND gate 14, O
It consists of an R gate 13. FIG. 2 is a block diagram of the 64-bit address calculation circuit 8. The 64-bit address arithmetic circuit 8 includes a 64-bit binary fixed-point arithmetic circuit 51, a 64-bit logic arithmetic circuit 52, and selectors 53 and 54. FIG. 3 is a block diagram of the 32-bit data calculation circuit 9. As shown in FIG. 3
The 2-bit data calculation circuit 9 includes a 32-bit binary fixed-point calculation circuit 61, a 32-bit logical calculation circuit 62, a 32-bit decimal calculation circuit 63, and selectors 64 and 65.

FIG. 4 is a block diagram of the address generation circuit 4. The address generation circuit 4 includes a 48-bit three-man power adder 71, a 31-bit three-man power adder 72, and a 24-bit three-man power adder 73.
, registers 74, 75, and 76 that hold addition results, a selector 77, an address conversion circuit 78 that converts virtual addresses into real addresses, and a real address register 79 that holds real addresses. FIG. 5 shows an RX command format 96 which is the format of the main memory access command of the data processing device of this embodiment. RX instruction format 96 has operation code (OP) 97 and first operand register number (R) 98.
．． 2nd operand index register number (X) 99
, second operand pace register number (B) 100.
It consists of a 12-bit second operand displacement (D) 101.

FIG. 6 shows an RR instruction format 102 which is the format of an arithmetic instruction. The RR instruction format 102 has an operation code (OP) 103. First operand register number (R1
) 104, second operand register number (R2) 10
Consists of 5. Program status word 3 has bits (Al) 16 and (A2) 17 that control the address mode.

Bit AI, 16. 24 when A2,17 is (0,0)
bit mode, (1,0), 31 bit mode, (
0,1) or (1,1) indicates 48-bit mode. When flip-flop V18 is 0, the target bit length of address operation instructions and main memory access instructions whose access target is an address is 64 bits regardless of the address mode, and when flip-flop V18 is 1, the target bit length is 24 bit mode. If you are in 31-bit mode, you can use 32 bits, and if you are in 48-bit mode, you can use 64 bits.

Next, the operation of this embodiment will be explained. First, the commands of the data processing device of this embodiment will be explained. In this example, there are address operation instructions that perform operations between general-purpose registers to calculate virtual addresses, data operation instructions that perform operations between general-purpose registers to calculate data, and data operations between main memory and general-purpose registers. It has a main memory access instruction that performs transfer.

The address operation instruction has the RR instruction format 102, and an example of an instruction is an unsigned binary fixed-point addition instruction (ADDA).
command). The data operation instruction has the RR instruction format 102, and an example of the instruction is a signed binary fixed-point addition instruction (ADD instruction). The main memory access instruction has an RX instruction format 96, and examples of the instruction include a data load instruction (L instruction) that accesses data, a data store instruction (ST all instructions, and an address load instruction (LA instruction) that accesses an address. instruction), address store instruction (S
There is a TA command).

Next, the operation of this embodiment when a main memory access instruction is executed will be explained. When execution of a main memory access instruction is started, an instruction code is set in instruction register 1. Instruction decoder 2
is the RX instruction format 96. in instruction register 1. The operation code 97 of the main memory access instruction is decoded and the operation code 97 is set on the signal line ○C36.

In addition, a signal vertical MA indicating that it is a main memory access command is
45 to 1, and set the signal line Al39 to 0 for instructions whose access target is data, such as L instruction and ST all instructions, and set signal line Al39 to 0 for instructions whose access target is address, such as LA instruction and STA instruction. Set the signal line Al39 to 1. The address generation circuit 4 generates an X field 99 and a B field 10 of the RX instruction format 96 in the instruction register 1.
The two general-purpose registers 7 pointed to by 0 (each called an index register uppace register) and the D field 10
Add a value of 1 to generate an operand address. In this addition, three types of adders 71, 72 .
One of the 73 addition results is selected as shown in FIG. 7 by the signal line AM37 indicating the address mode. That is, when the signal line AM37 is (0, O) indicating the 24-bit mode, the lowest 24 bits of the two general-purpose registers 7 designated as the index register and the pace register are read out, and they and 1 of the instruction register 1 are read out.
The value of the 2-bit D field 101 is added by a 24-bit adder 73. The result of addition is 4 by supplementing the top 0.
It is set in an 8-bit register 76, selected by a selector 77, and sent to an address conversion circuit 78. When the signal line AM37 indicates the 31-bit mode (i, o), the lowest 31 bits of the general-purpose register 7 are read out and the result added by the 31-bit adder 72 is selected by the selector 77. Signal line AM37 is (0°1) or (1
, 1) indicates 48-bit mode, general-purpose register 7
Read the lowest 48 bits and add 48 bits l! s7
The result of addition by 1 was selected by the selector 77. The address conversion circuit 78 converts the addition result selected by the selector 77, that is, the operand address which is a virtual address, into a real address, and converts the operand address selected by the selector 77 into a real address register 79.
Set the real address to . In the case of a load instruction such as an L instruction or an LA instruction, the main memory then uses the real address register 7.
The contents of the main memory corresponding to the real address 9 are set in the fetch data register 6. If the signal line LS, 46 is 1, the fetch data length is 64 bits, and the selector 2 selects the upper 32 bits and lower 32 bits of the fetch data.
1 and written to the fetch data register 6 via lines 83 and 84, respectively. If the signal LS is O, the fetch data is 32 bits, and the fetch data is selected by the selector 21 and written to the lower 32 bits of the fetch data register 6 via the line 84.The contents of the fetch register 6 are 64-bit address operations. It is written to the general-purpose register 7 designated by the R field 98 of the RX instruction format 96 via the circuit 8 or the 32-bit data calculation circuit 9. At this time, in the case of 32-bit data, 32 bits of 0 are added to the upper part of the data in register 10, and the data is written to general-purpose register 7. The selector is
Depending on whether the signal LS is 1 or O, the output 34 of the arithmetic unit 8 and the output 49 of the register 10 are selected. In the case of an ST instruction or an STA instruction, data and addresses are similarly written from the general-purpose register 7 to the main memory device via selectors 11 and 21. When the signal LS is 1, the selector 20 selects the upper three of the lines 80.
2 bits and the lower 32 bits are selected and line 85.
88 to the main memory bag @5, and when the signal LS is O! The lower 32 bits on line 80 are sent to line 85.

The main memory device 5 writes or reads 64-bit data when the signal LS is 1, and reads or writes 32-bit data when the signal LS is 0. The signal line LS46 handles 32 targets.
This indicates whether it is bit data or a 64-bit address, and the value is determined from the bits of the program status word and gates 13 and 14 as shown in FIG.

Next, the operation of this embodiment when a data operation instruction and an address operation instruction are executed will be explained. When execution of an instruction is started, an instruction code is set in instruction register 1. The instruction decoder 2 decodes the operation code 103 of the RR instruction format 102 instruction in the instruction register 1 and outputs the signal gOc.
Set operation code 103 to 36. Also, to indicate that this is not a main memory access command, the signal line MA
45 is set to 0, and the signal line AI is set to 1 in the case of an address operation instruction, and to 0 in the case of a data operation instruction.

The 32-bit data arithmetic circuit 9 uses the R of the RR instruction format 102.
Reads the lowest 32 bits of the two general-purpose registers 7 specified by the 1 field 104 and the R2 field 105, executes the operation specified by the signal line ○C36, and adds 0 to the upper 32 bits of the result to the register 10. and set it. 64-bit address calculation circuit 8 uses RR instruction format 10
All 64 bits of the two general-purpose registers 7 specified by the R1 field 104 and R2 field 105 of 2 are read out and the operation specified by the signal line 0C36 is executed. The selector 11 writes the output of the 64-bit address calculation circuit 8 to the general-purpose register 7 if the signal line L346 is 1, and writes the output of the register 10 to the general-purpose register 7 if the signal line L846 is 0.

The mode pits 16 and 17 of program status word 3 are changed by executing a branch instruction that saves the old mode pit and sets a new mode pit.

Additionally, changes to flip-flop V18 are performed using dedicated read and write commands.

Since these instructions are not essential to the present invention, detailed explanations will be omitted.

In this embodiment, when writing data to a general-purpose register, the upper part of the data length of the general-purpose register is set to 0, so that the address exchange between the conventional program before address extension and the new program after address extension is It becomes possible to use the data calculation result of the conventional program as it is as the address of the new program, and it becomes easy to guarantee compatibility with the conventional data processing device. Furthermore, since it is possible to perform address calculations with a bit length that exceeds the data length, address calculations can be performed faster than when data calculations are performed twice by dividing the address into upper and lower parts. In addition, since loads and stores between the main memory and general-purpose registers can be performed using a general-purpose register length that is larger than the data length, address data can be loaded and stored faster than when loading and storing address data twice, dividing it into upper and lower parts. Can be loaded and stored. Furthermore, if the address arithmetic unit and address data load/store length are made constant regardless of the address mode, a program with an address mode less than the data length can calculate, load, and store addresses exceeding the data length. Addresses that exceed the data length can be exchanged between an address mode that is less than the data length and an address mode that exceeds the data length, making it easier to guarantee compatibility.

In addition, by changing the address arithmetic unit and address load/store length according to the address mode, it is possible to calculate addresses less than the data length with an address arithmetic means that exceeds the data length, or to load addresses that are less than the data length with an address arithmetic means that exceeds the data length. There is no longer a need to store and store addresses, and address calculations and address loads and stores can be performed at high speed.

As one of the other configurations of the embodiment of the present invention, the address generation circuit 4 of the above embodiment has one adder with a length of 48 bits, and in the case of the 24-bit mode and the 31-bit mode, the lowest 24 bits of the addition result and Use 31 bits. Furthermore, a configuration can be considered in which a 64-bit data calculation circuit is provided in place of the 64-bit address calculation circuit 8 and the 32-bit data calculation circuit 9, and the lowest 32 bits of the 64-bit calculation result are used for 32-bit data calculation. but,
In the above embodiment, a separate arithmetic unit was used with emphasis on high-speed calculation of 32-bit length.

Furthermore, as a second embodiment of the present invention, the 64-bit address calculation circuit 8 of the first embodiment may have a length of 48 bits, and all address calculations may have a length of 48 bits. Here, the length is set to 64 bits in order to be able to perform simultaneous operations on data that is not an address in the 16 bits higher than the 48 bits of the general purpose register.

Furthermore, as a third embodiment of the present invention, an embodiment may be considered in which, except for the flip-flop V18 of the first embodiment, address calculations and main memory accesses for addresses are always made to have a length of 64 bits. In this case, address operations in 24-bit mode and 32-bit mode may become slower, but this has no effect on the main effect of the present invention.

〔Effect of the invention〕

According to the present invention, since the address length can be extended while keeping the data length the same, it is easy to transfer data between a conventional program before address extension and a program after address extension.
Compatibility with conventional data processing devices can be guaranteed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a 64-bit address calculation circuit of the same embodiment, FIG. 3 is a block diagram of a 32-bit data calculation circuit of the same embodiment, and FIG. Fig. 4 is a block diagram of the address generation circuit of the same embodiment, Fig. 5 is a block diagram of the RX instruction format of the same embodiment, Fig. 6 is a block diagram of the RR instruction format of the same embodiment, and Fig. 7 is the address generation circuit. FIG. 8 is an operation table of the circuit selector. 9th
The figure is a diagram of a virtual storage area in the address mode of the same embodiment. 3...Program status word, 7...General-purpose register, 4
...Address generation circuit, 8...64-bit address calculation circuit, 9...32-bit data calculation circuit, 11.
... Selector, 5... Main memory device. $1 Zuko 2m *zI! 1 rod 91!1

Claims (1)

[Claims] 1. A main memory device, and at least one second memory device having a first bit length or shorter.
means for specifying a bit length selected from among the bit lengths as an address length; a plurality of registers each having a third bit length greater than or equal to the first bit length; is executed on the first data held in the first register specified by the instruction or read from the main storage device, and the second data as the operation result is specified by the instruction. second
a register or a main storage device,
The effective digit length of the first data and the effective digit length of the second data are greater than or equal to the first bit length in the first operation mode and less than the first bit length in the second operation mode. an arithmetic means having a short fourth bit length, and responding to a bit length portion equal to the address length specified by the specifying means among the third data held in the third register specified by the instruction; to access the main memory by generating an address with the first bit length, and in the first operation mode, data having at least the first bit length is accessed in the second operation. In mode, the fourth
access means that enables data having a bit length of 1 to be transferred between the main memory, the arithmetic means, one of the plurality of registers and the main memory; and the arithmetic means in response to an instruction. or means for controlling the operation mode of the access means.