JPS63111479A - Ic testing device - Google Patents

Abstract

PURPOSE:To easily vary the contents of a connection between a measuring circuit and a pin by driving a relay according to data whose bit positions are assigned corresponding to respective relays respectively. CONSTITUTION:A CPU 10 reads pin specification data out of a memory 11 and stores it in a pin register 12. The pin specification data indicates that a flag corresponding to a bit position corresponding to the number of a relay or pin is 1 as to connections between respective connection pins and DC measurement units 2-5 that have the pin numbers. Shift registers 15a-15d are driven successively in series, and consequently AND circuits 18a-18e are placed in a gate state in series; and AND outputs become true at bit positions where bits in the register 12 are set and relay driving circuits 19a-19e are connected at every time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an IC test device, and in particular, to an IC test device. I
The present invention relates to an IC test device that can quickly switch connections between each pin of a II constant device and a 4III constant circuit.

[Prior Art] Conventional IC test equipment is provided with a plurality of measurement units in order to shorten measurement time, and serial or other (
By connecting the pins in parallel, 64 pins to 128 pins can be connected in parallel.
By connecting many pins such as pins to the measurement unit,
We are measuring the characteristics, etc.

In this case, one? The 1l11 constant units are each commonly connected to a plurality of pins via relays, and when one of the relays is driven, one of the commonly connected pins and one of the 1ltll constant units are selectively connected. be done. The relay is generally designated and driven by a processor (hereinafter referred to as CPU) according to the measurement mode.

[Problems to be Solved] However, when the relay drive signal is obtained from the CPU in this way, the connection switching time is determined by the CPU machine cycle, and faster processing cannot be expected.

On the other hand, in order to achieve high-speed processing, it is possible to connect each pin and relay by hardware, but since the connection relationship is fixed, it is necessary to switch from serial/1llll constant to parallel measurement. However, the disadvantage is that the circuit becomes complicated and the number of circuits increases. Moreover,
Such an increase in the number of circuits not only makes the device expensive, but also increases the amount of heat generated, which adversely affects the reliability of measurement.

In addition, with this kind of hardware connection, it is possible to connect a specific pin to another measurement circuit, which is required, for example, when measuring two devices with a small number of pins at the same time. It also lacks flexibility when it comes to connections and not connecting specific pins.

[Object of the Invention] The present invention solves the problems of the prior art as described above. One object of the present invention is to provide an IC test device that can connect a measurement circuit to each pin of a device under test at high speed with a simple circuit configuration, and can ensure flexibility in connection.

[L stage for solving the problem] Means in the IC test device of the present invention to achieve such an object include a register that stores data in which each bit position is assigned to correspond to each relay. , a gate signal generation circuit that generates FSI number of gate signals corresponding to each bit output of this data, and a gate signal generation circuit that receives the output of each bit and outputs each of these outputs according to the gate signal corresponding to the bit position. and a drive signal generation circuit that outputs a signal for driving a relay corresponding to each of the gate signals, and the gate signal generation circuit sequentially generates a plurality of gate signals in accordance with a clock signal and at least some of the plurality of gate signals. It selectively generates either one at the same time, and selects the relay to be connected by setting a flag at a predetermined bit position of the data.

[Operation] With this configuration, if the data is set in advance, the relay can be driven with only the gate signal.
The connection between the l1l11 constant circuit and the pin can be switched at the speed of the gate signal.

Moreover, since it is equipped with a gate signal generation circuit that selectively generates multiple gate signals sequentially or at least some of them simultaneously, it is possible to switch between serial and parallel scanning. . moreover,
Since the connection relationship can be changed by changing the data contents, flexibility in changing the connection contents can be ensured.

Therefore, the connection relationship becomes flexible, and serial/parallel scanning can be easily changed, and high-speed measurement is possible without affecting the CPU machine cycle.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram mainly showing a drive circuit of an IC test device to which the present invention is applied, and FIG. 2 is a circuit diagram illustrating its pin connection relationship.

In FIG. 2, ■ is an IC as a device under test, and four DC measurement circuit units (PMU) 2, 3
．． 4.5. PMU2 has pin number S;1.
5+ 9. ...and so on, 4n+l fraud (n=o
+t, 2t 3. They are commonly connected to the pins of φ·11) via a relay Ri (where 1=4n+1). Also, PMU3 is Pingyu Jino 2.8.10.
・Fist・It is commonly connected to 4n+2 total 1-1 pins via relay Ri (however, 1=4n+2), and PMU4 has pin numbers 3, 7.9. . . . are commonly connected to the 4n+3rd pin via a relay Ri (where 1=4n+3). Furthermore, P.M.
U5 has pin numbers 4, 8, 12 . ...and so on, the relay Ri (however, 1=
4n+4).

Here, when measuring by connecting each pin of the IC serially, the relays Ri are sequentially driven according to the pin numbers, and at the same time 7! The PMUs on the constant side are also PMU2, 3,
Select 4.5 in order, return to PMU2 again, and
It is sufficient to select PMU2, 3.4.5 and sequentially connect each pin to each PMU through such circulation.

On the other hand, when driving in parallel, the relay RI t
R1+/t R1+2 + RI+J (However,
i = an integer from 1 to n) by simultaneously driving the corresponding P
MU2, 3.4.5 perform measurements at the same time, and sequentially update i by 1.

The drive circuit shown in FIG. 1 performs such serial/parallel connection.

In FIG. 1, 10 is a CPU, and 11 is its memory. The CPU10 refers to the memory 11 and stores data (
It sends out pin designation data (hereinafter referred to as pin designation data) and outputs a mode setting signal to the serial/parallel mode register 13.

The start bit register 14 receives 4-bit start bit data from the serial/parallel mode register 13. This 4-bit information is manually input to the first stage of each of the four shift registers 15a, 15b, 15e, and 15d.

The pin register 12 is, for example, a 128-bit register, and the parallel output corresponding to each bit is connected to the ANI) circuits 18a+18b, respectively.
+ 18c, tsct, 18e, e11
41 (128 pieces) are sent out to one of the human forces. Therefore,
The pin specification data here consists of 128 bits (16 bytes), and the bit positions 1 to 128 correspond to each connection pin 1 to 128, respectively, and the flag l" is set in the corresponding bit position. This indicates that the PMU having the pin number position and pin number is connected.

The drive clock generation circuit 16 here is composed of a 32-decimal counter, a four-stage shift register, etc., and according to a control signal from the serial/parallel mode register 13, the shift registers l 5 a + 15 b, 15 c, 15
d in parallel or in series.
It is controlled to operate serially as a wooden shift register, and gate control signals corresponding to these operations are sent to the gate circuit 17. Furthermore, this drive clock generation circuit 1
6 sends out a signal for resetting the start register 14, each register 14, and the rear register 14.

The gate circuit 17 includes four gate circuits 17a.

17b, 17c, and 17d, each of which receives the output of each stage of the four-stage shift register of the drive clock generation circuit 16 and the clock signal. When the bit stored in each of the four stages of shift registers of the driving clock generation circuit 16 is "1 pass", the clock signal is passed through to each shift register 15a, 15b.
, 15c, l5d. Further, 20 is a terminal to which this clock signal is input, and each shift register shift register 15a,
15b, 15c.

15d.

On the other hand, the shift register shift register 15a.

Here, 15b, 15c, and 15d are registers having a 32-bit configuration, which receive a start bit and shift it sequentially from the first stage to the final stage in accordance with a clock signal. Also, an AND circuit 18a.

18b + 18c, 18d, 18e, * * The other input of the fist is the four shift registers 15 a, l
5b+Receives the outputs of each stage of 15c and 15d, respectively.

Here, the shift register 15a corresponds to the connection relationship of the PMU 2 in FIG. 2, and controls the connection relationship between the PMU 2 and the pins. This adds the outputs of the first stage I and the second stage to the AND circuits 18a and 18e, respectively, and supplies the output of the next stage to four AND circuits. In other words, each stage is numbered 4n+1 [1 (where n is a positive integer)
The output is sent to the AND circuit.

Similarly, the shift register 15b controls the connection relationship between the PMU 3 and the pins. This causes the AND circuit 18b to
The output of the first stage is added, and the output of the next stage is supplied to four more AND circuits.

That is, each stage sends its output to the 4n+2nd AND circuit. The shift register 15c controls the connection relationship between the PMU 4 and the pins. This adds the output of the first stage to the AND circuit 18c, and supplies the output of the next stage to four additional AND circuits. That is, each stage has 4n+
The output is sent to a 3 Mrl AN circuit. Further, the shift register 15d controls the connection relationship between the PMU 5 and the pins. This causes the ANI) circuit 18d to have the first stage [
1 is added, and the output of the next stage is supplied to four more ANI) circuits. That is, each stage sends its output to the 4n+4th L1 AND circuit.

Each ANI) circuit 18a+ 18bv 18c*
18cL18e, ・Work・ is a drive signal generation circuit for driving the relay drive circuit, and its output is connected to relays Ri (i =1 to 128) drive circuit 19a
s 19b, 19ct 19d, 19e.

...(128 pieces).

Next, the operation will be described. The CPU 10 reads pin designation data from the memory 11 and stores it in the pin register 12 according to the designation of the serial/parallel connection type. The pin designation data indicates the connection between each connection pin and the PMU having the pin number by setting the flag at the bit position corresponding to the relay or pin number to be 1".

When set to serial mode, CPUl0
7 real/parallel mode register 13, and when parallel mode is set, serial/parallel mode register 1
Parallel mode control signals are output to each of the ports 3 and 3. When the serial/parallel mode register 13 receives a serial control signal or a parallel control signal, it sets each bit of the start bit register 14 to "l", and also sets the drive clock generation circuit 1 to "l" in serial control.
6 is set to the first stage of the 4-stage shift register, and in the case of parallel control, the 4-stage shift register of the drive clock generation circuit 16 is
Set "1" to each stage of the stage shift register.

Therefore, during serial control, the gate circuit 17
receives the "L" output from the first stage of the shift register of the drive clock generation circuit 16 at its gate 17a. Then, the gate 17a opens, the clock signal received from the terminal 20 is supplied to the shift register 15a, and the bit "1" information sent from the start pit register 14 is output to the first stage of the shift register 15a, and is sequentially shifted from the first stage. , which are sequentially output as outputs from each stage.

Note that the start bit corresponding to the shift register 15a is input to the drive clock generation circuit 16 at the time it is input to the first stage.
Cleared by This also applies to the following shift registers 15b, 15c, and 15d.

When the output of the final stage of the shift register 15a is completed, the counting of the 32-digit counter of the drive clock generation circuit 16 is also completed, and this completed output is used as the clock signal of the four-stage shift register of the drive clock generation circuit 16. The bit "1" in the first stage of the shift register is shifted to the next stage. As a result, the gate 17a closes, and this time,
The gate 17b opens, the shift register 15b receives a clock signal and is driven, and the start pit register 14
The information of bit “l” sent from shift register 1
5b is sequentially shifted from the first stage, and this is sequentially output as the output of each stage. In this way, the shift register 15
b, 15c, and 15d are sequentially driven serially to achieve 1J゛<.

As a result, ANI) circuits 18 a, 18 b,
l 8 c.

t8dt 18e* 41... are sequentially gated serially, and bit "1" of pin register 12 becomes ~
The AND condition is satisfied at the bit position y, and that AN
An output from the D circuit is generated and the corresponding relay Ri (i
= 1 to 128) drive circuit 19a + 19bv
19c* 19d, 19et *fist* (128
), and the relay Ri becomes connected each time. Therefore, the pins and the PMUs that receive them are serially connected in sequence, and measurements can be performed serially.

On the other hand, during parallel control, the gates 17a, 17b, 17c, and 17d of the gate circuit 17 simultaneously receive the 'l' output from each stage of the shift register of the drive clock generation circuit 16, and the clock signal received from the terminal 20 is transmitted to the shift register. 15a, 15b, 15c, and 15d at the same time.Then, the bit "1" information sent from the start bit register 14 is supplied to each shift register 15a, 15d.
b, 15c, and 15d at the same time, and this is sequentially shifted from the first stage in each shift register. Therefore, four shift registers 15a, 15b,
Outputs are generated sequentially in each stage of 15c and 15d, and each is sent to the AND circuit side. In addition, shift registers 15a, 15b, 15
The start bits corresponding to c, l5d are cleared by the drive clock generation circuit 16 at the time they are input to the first stage, as described above.

In this way, AND circuits 18a, 18b+
18ct 18cL 18e, ***, 4i
Each AND circuit from +1 to 4i+4 (i=1 to n) is gated at the same time. As a result, four gates are sequentially gated in parallel, and outputs from the AND circuit are generated in parallel for the signals for which the bit "1" of the pin register 12 is set, and the corresponding relays Ri (i=1 to 12
8) drive circuit 19a.

19bl 19c, 19d, 19e, *** (12
8) are sequentially sent to the corresponding ones. therefore,
If all bit designation data stored in pin register 12 is “l”, four relays Ri + RI+7
+ R1+2 * R1+J (however, i=1~n
) become connected at the same time. Therefore, the pins and the PMUs that receive them are connected in sequence, and measurements can be performed in parallel.

As can be understood from the explanation in 1- below, PMU2゜3.4
．． 5 and one of the plurality of pins each of these has can be specified by pin designation data stored in the pin register 12 in advance.

The connection switching speed is the shift register 15a, 15b
, 15c, l5d, which can be switched at high speed by a clock signal.

Moreover, it can be performed regardless of the machine cycle of CPU10.

Here, if it is possible to measure 128 pins like this,
Two 64-pin ICs are also measured simultaneously.

In such a case, set the 1st and 2nd pins of the first IC to 1ill+ using PMU2.3, and set the 2nd pin to 1ill+ using PMU4.5.
In order to measure the 1st and 2nd pins of one IC, it is possible to install a relay Ri in the - section in advance by iTUM, and connect it to other PMUs, so that the pin register 12 It is sufficient to simply switch the connection relationship of the PMU depending on the pin designation data to be set.

As explained above, in the example, the number of pins of the IC is 12.
Although an example of 8 pins is explained, the number of pins is of course not limited to 128 pins, and the measurement circuit is
Of course, it is not limited to U.

Further, although the flag as pin designation data set in the pin register is '1' in the description, it may be '0' in negative logic operation and does not depend on the content of the flag information.

In the embodiment, the relay drive circuit is driven by the AND of the output of the register that stores data specifying the connection state and the gate signal, but the gate in this case is limited to an AND circuit. Rather, its gate signal is
The present invention is not limited to those using shift registers. Multiplexers etc. may be used, other gating
) may be a generating circuit.

Further, in the embodiment, each output signal of the drive signal generation circuit consisting of the ANI) circuit is directly applied to the corresponding relay drive circuit, but it may also be applied via an amplifier, buffer amplifier, etc. Of course, each output may be used indirectly.

[Effects of the Invention] As can be understood from the above explanation, in this invention, each bit position corresponds to a register that stores data assigned to each relay, and a register that stores data that corresponds to each bit output of this data. a gate signal generation circuit that generates multiple gate signals; and a gate signal generation circuit that receives the output of each bit and uses each output as a signal for driving a relay corresponding to that bit position in accordance with the corresponding gate signal. and a drive signal generation circuit that outputs a drive signal, and the gate signal generation circuit selectively generates a plurality of gate signals sequentially or at least one of the plurality of gate signals simultaneously according to a clock signal. The relay to be connected is selected by setting a flag in a predetermined bit position of the data, so if the data is set in advance, the relay can be driven with only the gate signal. Connections between the measurement circuit and the pins can be switched at the speed of the gate signal.

Moreover, since a gate signal generation circuit is provided that selectively generates a plurality of gate signals sequentially or at least one of them simultaneously, serial/parallel scanning can be switched simply by WI.Furthermore, Since the connection relationship can be changed by changing the data contents, flexibility in changing the connection contents can be ensured.

Therefore, the connection relationship becomes flexible, and serial/parallel scanning can be easily changed, and high-speed measurement is possible without affecting the CPU machine cycle.

[Brief explanation of the drawing]

FIG. 1 is a block diagram mainly showing a drive circuit of an IC test device to which the present invention is applied, and FIG. 2 is a circuit diagram illustrating its pin connection relationship. ■...IC, 2, 3, 4, 5...DC δIII constant unit U), 10...CPU111...memory, 12...pin register, 13...serial/parallel mode register , 14... Start bit register, 15a, 15b, 15c, 15d... Shift register, 16... Drive clock generation circuit, 17-...
Gate circuit, 18 a, l 8 be 18 c-1
8d, 18e...AND circuit, 19...Relay Ri drive circuit, 20...Clock signal terminal.

Claims (3)

[Claims] (1) In an IC test device that selectively connects a measurement circuit and a plurality of pins of a device under test via respective relays provided corresponding to the pins, each bit position is connected to each of the relays. A register that stores correspondingly allocated data, a gate signal generation circuit that generates a plurality of gate signals in response to each bit output of this data, and a gate that receives and corresponds to the output of each of the bits. and a drive signal generation circuit that outputs each of these outputs as a signal for driving a relay corresponding to the bit position in accordance with the signal, and the gate signal generation circuit sequentially generates the plurality of gate signals in response to a clock signal. and selectively generates at least some of the plurality of gate signals simultaneously, and is characterized in that a relay to be connected is selected by setting a flag at a predetermined bit position of the data. I
C test equipment. (2) The device under test is an IC, the measurement circuit is a DC measurement circuit, and includes a plurality of these, and each of the DC measurement circuits is commonly connected to a plurality of relays. An IC test device according to claim 1. (3) The gate signal generation circuit is characterized by having a plurality of shift registers, and by driving the plurality of shift registers serially or in parallel, it generates gate signals sequentially or some of them simultaneously. An IC test device according to claim 1.