JPS63109678A - Teletext signal processing circuit - Google Patents

Abstract

PURPOSE:To make the circuit configuration of the titled circuit simple and inexpensive, by detecting the period during which a synchronizing signals exists from a clock for processing teletext signal data and a synchronizing signal containing an equalizing pulse, and removing the equalizing pulse from the synchronizing signal containing the equalizing pulse. CONSTITUTION:Signals outputted from a voltage controlled oscillator (VCO) 5 are supplied to an equalizing pulse removing circuit 7 as data sampling signals (clocks) having a frequency fsp. Moreover, horizontal synchronizing signals which are separated at a synchronizing separator circuit 8 and have a frequency fh are also supplied to the circuit 7. The circuit 7 detects the period during which horizontal synchronizing signals exist from the data sampling signals (clocks) (fsp) and horizontal synchronizing signals (fh) containing equalizing pulses. Then the circuit 7 removing the equalizing pulses from the horizontal synchronizing signals containing the equalizing pulses by using the detecting output and outputs the horizontal synchronizing signals from which the equalizing pulses are removed to an output terminal 9. Therefore, necessity of a shift register of one horizontal scanning period quantity can be eliminated and this circuit can be made simpler in circuit configuration and inexpensive in cost.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a teletext signal processing circuit, and particularly to a teletext signal processing circuit that receives a teletext signal superimposed within the vertical blanking period of a television signal, and The present invention relates to a teletext signal processing circuit that processes signals.

(Prior technology) Recently, a new broadcasting service has been teletext broadcasting (hereinafter referred to as
teletext) has been realized.

Furthermore, as a teletext system, there is a coded transmission system (code system) that has better transmission efficiency than the conventional pattern system.

Unlike regular television programs that are organized by time, teletext repeatedly transmits various information and entertainment programs consisting of text, graphics, and additional sounds, allowing viewers to access the information they want when they want it. This is a new broadcasting system that has made it possible to

The above information such as text and images is multiplexed with the television radio waves (video signals) from the broadcasting station currently being broadcast, and the recipient must prepare a receiving device or adapter that can receive teletext. Then, the user can select and enjoy the desired teletext program from among many teletext programs.

In addition, this teletext signal (text signal packet) is transmitted as a digital signal using the vertical blanking period of the current television broadcasting system, and the receiving device decodes the signal and sends it to the TV. It is now possible to view text programs by converting them into television signals, displaying images on the television screen, and generating additional sounds such as music.

(Problems to be Solved by the Invention) By the way, in the above-mentioned teletext broadcast using the encoded transmission method (code method), continuity (clock synchronization (CR), Byte synchronization (FC) is guaranteed, and the teletext signal is transmitted from the broadcasting station in such a way that the phase of data across fields of the television signal is not discontinuous. Therefore, on the receiving side, various circuit improvements have been made to teletext receiving adapters and receiving devices so that stable reception can be achieved by utilizing the continuity of the transmitted teletext signal.

In other words, the data sampling signal (clock) is obtained from the color subcarrier frequency of the television signal, and byte synchronization is achieved using a framing code.The data of the teletext signal is obtained by using a data sampling signal and further byte synchronization. Digital signal processing is performed by taking the Furthermore, the following relationship exists between the data sampling signal frequency (fsp) of the teletext signal, the horizontal scanning frequency (fh), and the color subcarrier frequency (fsc) of the television signal (composite video signal).

f sp = 4・fsc, fh = (2/455)
・fsc However, if the broadcasting station performs synchronization switching,
It may become impossible to maintain the above continuity due to various broadcasting station 4A conditions (for example, when switching broadcast programs on the same channel or when changing the relay location), and therefore, on the receiving side, the broadcast It is necessary for the station side to stably detect when the continuity of the transmitted teletext signal cannot be maintained by performing synchronization switching, etc., and thereby to be able to perform stable reception from now on.

In order to stably detect when the speed readability of the teletext signal transmitted as described above can no longer be maintained, it is necessary to
It is necessary to detect the equalization pulse period and to detect a stable horizontal periodic signal that does not include the equalization pulse. Furthermore, in order to detect a stable horizontal periodic signal that does not include such equalization pulses, it is necessary to use, for example, a shift register for one horizontal scanning period, which makes the circuit configuration complicated and increases costs. There are some problems.

Therefore, in view of the above-mentioned conventional technology, the present invention includes an equalization pulse for stably detecting when the broadcasting station side performs synchronization switching and the continuity of the transmitted teletext signal can no longer be maintained. To provide a teletext signal processing circuit which can obtain a stable horizontal periodic signal with no distortion and has a simple and inexpensive circuit configuration.

(1000 Ways to Solve the Problems) In order to achieve the above object, the present invention receives a teletext signal superimposed within the vertical blanking period of a television signal, and converts this teletext signal into a signal. A teletext signal processing circuit for processing a teletext signal data processing circuit, which obtains a teletext signal data processing clock having a frequency that is a predetermined multiple of the subcarrier frequency from the subcarrier of the television signal, and an equalization pulse from the television signal. a circuit for separating a periodic signal including the teletext signal data processing clock and a periodic signal including the equalization pulse; (b) provides a teletext signal processing circuit characterized in that it includes an equalization pulse removal circuit for removing equalization pulses from a signal;

(Function) In the teletext signal processing circuit configured as described above, the periodic signal is processed by the periodic signal containing the teletext signal data processing clock obtained from the subcarrier of the television signal and the snowflakes pulse separated from the television signal. The existing period is detected, and the detected output is used to remove the equalization pulse from the periodic signal containing the equalization pulse.

(Embodiment) An embodiment of the teletext signal processing circuit according to the present invention will be described below with reference to the drawings. - FIG. 1 is a block system diagram showing an embodiment of the teletext signal processing circuit according to the present invention.

In the figure, an input terminal 1 is supplied with a received television signal (composite video signal) transmitted from a broadcasting station. A character signal (character signal packet) of the encoded transmission method is superimposed on a specific horizontal scanning period within the vertical blanking period of this television signal.

2 is a subcarrier regeneration circuit, 3 is a sufficient frequency generator, 4 is a phase comparator circuit, 5 is a voltage controlled oscillator (hereinafter referred to as ■CO), 6 is a sufficient frequency generator, 7 is an equalization pulse removal circuit, and 8 is a synchronous separation circuit. 9 is an output terminal of the circuit. In addition, the frequency divider 31 phase comparator circuit 4. VCO5°) frequency divider 6 is a phase-locked
It constitutes a loop (PLL).

The n1 carrier regeneration circuit 2 receives the frequency fsc [= 3.58] from the television signal supplied via the input terminal 1.
Mllzl) Regenerate the IJ carrier wave (waveform a in FIG. 2) and supply it to the frequency generator 3. Then, the subcarrier frequency fsc is rotated forward to obtain a signal of the frequency sound fsc (waveform b in FIG. 2), which is supplied to the phase comparator circuit 4.

The phase comparator circuit 4 receives a signal (
The phases of waveform b) in Figure 2 and the signal supplied from the sufficient frequency divider 6 (wave id in Figure 2) that divides the output of the VCO 5 ↑ are compared, and there is a phase difference between them. At this time, an error voltage corresponding to the phase difference is generated and supplied to VCO5. Then, C05 draws in a signal of a new phase using this error voltage and outputs it. Furthermore, the signal output from this VCO 5 (waveform C in FIG. 2 (waveform C in FIG. 4)
')) is supplied to the equalization pulse removal circuit 7 as a data sampling signal (clock) with a frequency fhp[=5.7M1lz]. In addition, this equalization pulse removal circuit 7
The frequency fh [= 1] separated by the synchronization separation circuit 8 is
A horizontal periodic signal of 5.7 kllzl (waveform 100, which is an inversion of waveform e in FIG. 4) is supplied. Note that this horizontal periodic signal includes a snow formation pulse.

The equalization pulse removal circuit 7 detects a period in which a horizontal periodic signal exists from a data sampling signal (clock) (fsp) and a horizontal periodic signal (rh) including an equalization pulse, and uses this detection output to detect a period including a snowflake pulse. The equalization pulse is removed from the horizontal periodic signal, and the horizontal periodic signal from which the equalization pulse has been removed is output to the output terminal 9.

FIG. 3 shows an equalization pulse removal circuit 7 which is the main part of the circuit of the present invention.
FIG. 2 is a diagram showing a specific circuit.

In the same figure, terminals 10 and 11 are connected to data sampling signals (waveform C in FIG. 2 (waveform C in FIG.
A horizontal periodic signal (waveform e, which is an inversion of waveform e in FIG. 4) (fh) including a waveform C' ) ) (fsI)) in FIG. 4 and an equalization pulse is supplied.

The data sampling signal (
fsp) is supplied to the clock terminal of the counter 12, and is also supplied to the clock terminals of the counter 13 and counter 14. Further, the horizontal periodic signal (fh) containing the equalization pulse supplied via the terminal 11 is inverted via the inverter 15 to form the waveform e in FIG. 4, and is supplied to the clock terminal of the D flip-flop 16. Ru. Here, the fifth
The waveform e' in the figure changes the time axis of the waveform e in FIG.
One pulse of waveform e' in FIG. 5 corresponds to waveform e in FIG. 4.

The D flip-flop 16 is triggered on the rising edge of the waveform e (e') supplied to the clock terminal;
Waveform f supplied from the output of the NAND circuit 11, which will be described later.
reset by . And flip flop 1
6 is supplied to the DI terminal of this D flip-flop 16 and the reset terminal R of the counter 12.

When the D flip-flop 16 is triggered, the 0 output of the D flip-flop 16 becomes "yes", which enables the counter 12 to count. The counter 12 then starts counting the data sampling signal (f SD) of waveform C1C' supplied to the clock terminal.

C, D, E output terminals of counter 12 (i.e., 23.
A NAND circuit 17 is connected to the output terminal (24, 25 output terminal), and when the counter 12 detects a predetermined count la (28 in this connection), the NAND circuit 17 outputs a detection signal (in Fig. 4). A waveform f) is output, and this is supplied to the reset terminal R of the D flip-flop 16. Therefore, the outputs of the D flip-flops 1 and the like become 'L' during a period corresponding to 28 clock cycles, and the output of the D flip-flop 16 has a horizontal opening iI.
A signal (waveform opening, 0' in FIGS. 4 and 5) having a pulse width (approximately 49 μsec) substantially equal to the signal 19 is generated.

Here, the waveform Q' in FIG. 5 is similar to the relationship between the waveform e and the waveform e' described above, and the l181? of the waveform 9 in FIG.
! 1 of waveform Q' in Fig. 5.
The pulse corresponds to waveform q in FIG.

Further, the DE terminal of the D flip-flop 18 is supplied with the power supply Vcc, which is an H'' signal, and its clock terminal has a waveform QCQ' which is the output of the D flip-flop 1G.
is supplied. This D flip-flop 18 is triggered by the waveform g(Q'), and the NANO circuit 2 to be described later
It is reset with the waveform i output from 1, and its mouth output (
Waveform h) in FIG. 5 is supplied to the D terminal of the D flip-flop 19.

Furthermore, the output of the D flip-flop 18 is sent to the counter 13.
is supplied to the reset terminal R of the D flip-flop 20, and to the clock terminal of the D flip-flop 20.

Further, the D flip-flop 19 is triggered by the waveform l (to I'), and is reset by the waveform j output from the NAND circuit 22, which will be described later, and its output is supplied to the DI terminal of the D flip 7O block 20. . Furthermore, the output of the D flip-flop 19 is supplied to the reset terminal R of the counter 14.

In this way, since the D flip-flops 18 and 19 are connected in a subordinate manner, the D flip-flop 19 receives the clock (waveforms Q, Q') when the D flip-flop 18 is in the set state (H"). It will not be set unless input.

The counter 13 counts the data sampling signals (waveforms c, c') supplied to its clock terminal only when the D flip-flop 18 is in the set state, and counts the data sampling signals (waveforms c, c') supplied to its clock terminal, and counts the data sampling signals (waveforms c, c') supplied to its E, F, G, H output terminals (i.e., 25.2B, 27
．． A predetermined count value is detected by the NANO circuit 21 connected to the output terminal (28 output terminal), and a detection signal (waveform i in FIG. 5) is output from this NAND circuit 21. The counter 13 continues counting the data sampling signals (waveforms c, c') supplied to the clock terminal until the D flip-flop 18 is reset by this detection signal.

Here, the predetermined count value detected by the above-described NAND circuit 21 is set to a clock count corresponding to a period that is greater than th/2 (where th is the horizontal periodic signal frequency 111) and smaller than th. With this connection, the counter value is 3th/4: "'240"), and the D flip-flop 19 is not set during a period in which there is no equalization pulse.

Therefore, during the equalization pulse period, after the D flip-flop 18 is set, a clock (waveform Q, Q') is input to its clock terminal th/2 later, and at this time, the D flip-flop 18 is in the set state. Therefore, the D flip-flop 19 is turned on.

On the other hand, D flip-flop 19. The counter 14 and the NAND circuit 22 are connected to the D flip-flop 18 described above.
．． It has the same configuration as the counter 13 and the NAND circuit 21, and its operation is also the same.

That is, the counter 14 counts the data sampling signal (waveform C1c') supplied to its clock terminal only when the D flip-flop 19 is in the set state, and counts the data sampling signal (waveform C1c') supplied to its E, F, G, H output terminals (i.e., 25.
NAND circuit 2 connected to 26.27.28 output terminal)
2 detects a predetermined count value, and outputs a detection signal (waveform j in FIG. 5) from this NAND circuit 22. Then, until the D flip-flop 19 is reset by this detection signal, the counter 14 receives the data sampling signal (waveforms c, c') supplied to the clock terminal.
Count and pull the branch number.

Here, the predetermined count value detected by the NAND circuit 22 described above is set to th/2 (however, t
Set (connect as above) so that the clock count time corresponds to 391, which is larger than h (horizontal periodic signal period) and smaller than th (in this connection, the counter value is 3th/4: " 240”).

Therefore, a pulse train (waveform k) that is approximately 3th/4 "H" only during the equalization pulse period is generated at the output of the D flip-flop 19.

The output of the D flip-flop 19 (waveform k) is supplied to the D terminal of the D flip-flop 20, and the output of the D flip-flop 18 (inverted waveform) is supplied to the clock terminal of the D flip-flop 2G. be done. And the D flip-flop 20 is the D flip-flop 18
The equalization pulse period detection signal (waveform i) in which only the equalization pulse period is "H+t" is obtained at the beginning output (an inverted waveform of the waveform).

Also, the NA output terminals of the counter 13 are
ND circuit 23 is connected, and this NAND circuit 2
The count value of the counter 13 is set so as to detect a clock count value corresponding to a period in which 3 exceeds "0 (zero)" and is smaller than th/2 (in the case of this connection, the count value is th/4 : “80”).

The output (waveform m) of the NAND circuit 23 is output to the gate circuit 25
．． The output of the NANO circuit 21 (waveform i) is supplied to the set terminal S of the RS flip-flop 24.

Then, from the output terminal of the RS flip-flop 24, a gate signal (waveform n) is output which becomes "H" during the horizontal synchronization pulse period and "L 11" during the equalization pulse period.

By supplying this gate signal (waveform n) and the output of the D flip-flop 1G (waveforms Q, Q') to the AND circuit 27, the output terminal of the AND circuit 27 produces a horizontal periodic signal from which the equalized pulse has been removed. (Waveform 0) is obtained, and this is output via the terminal 28.

As described above, the Q output terminal of the D flip-flop 20 receives the equalization pulse period detection signal (waveform i) in which only the equalization pulse period is "HI+", and the output terminal of the AND circuit 27 outputs the equalization pulse period detection signal (waveform i). Horizontal synchronization (ffi) with removed horizontal synchronization (ffi)
Waveform 0) is multiplied by 11. Then, by using this equalized pulse period detection signal and the horizontal periodic signal from which the equalized pulse has been removed, it is possible to stably detect that the continuity of the teletext signal transmitted from the broadcasting station can no longer be maintained. Further, this detection signal can be supplied to, for example, a teletext receiving device or an adapter control device (signal processing control microcomputer) to perform signal processing control corresponding to this discontinuous state.

(Effects of the Invention) As described above, according to the teletext signal processing circuit of the present invention, the period in which the periodic signal exists is detected from the periodic signal including the teletext signal data processing clock and equalization pulse,
This detection output removes the equalization pulse from the periodic signal that includes the equalization pulse, so the broadcasting station can detect when the broadcasting station can no longer maintain the continuity of the teletext signal being transmitted due to synchronization switching, etc. It is possible to obtain a stable horizontal periodic signal that does not contain equalization pulses, and the circuit configuration is simple and inexpensive since there is no need to use a shift register for one horizontal scanning period.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram showing an embodiment of the teletext signal processing circuit according to the present invention, FIGS. 2, 4, and 5 are signal waveform diagrams of each part of the circuit according to the present invention, and FIG. 3 is a diagram showing a specific circuit of an equalization pulse removal circuit 7 which is a main part of the inventive circuit. FIG. 1... Input terminal, 2... Subcarrier regeneration circuit, 3...
- Front frequency generator, 4... Phase comparison circuit, 5... Voltage control 2I1 oscillator (VCO), 6... Front frequency generator, 7...
Equalization pulse removal circuit, 8...Synchronization I! i1 circuit, 9
...Output terminal, 10.11.28...Terminal, 12,
13.14...Counter, 15...Inverter, 1
6, 18.19.20...D flip-flop, 17
, 21.22.23...NΔAND circuit, 24...R
S flip-flop, 25.26...gate circuit, 2
7...AND circuit.

Claims (3)

[Claims] (1) A teletext signal processing circuit that receives a teletext signal superimposed within a vertical blanking period of a television signal and processes the teletext signal, the circuit processing the teletext signal from a subcarrier of the television signal. a circuit for obtaining a teletext signal data processing clock having a frequency that is a predetermined multiple of the subcarrier frequency; a circuit for separating a synchronization signal including an equalization pulse from the television signal; the teletext signal data processing clock and the The apparatus is characterized by comprising an equalization pulse removal circuit that detects a period in which a periodic signal exists from a synchronization signal including an equalization pulse, and removes the equalization pulse from the synchronization signal including the equalization pulse using the detected output. teletext signal processing circuit. (2) The teletext signal processing circuit according to claim 1, wherein the circuit for obtaining the clock for teletext signal data processing is constituted by a phase-locked loop circuit. (3) The equalization pulse removal circuit includes a flip-flop that detects the leading edge of the synchronization signal, a counter that can count based on the output of this flip-flop, and a detector that detects the period in which the synchronization signal exists based on the output of this counter. circuit and
2. The teletext signal processing circuit according to claim 1, further comprising a circuit that removes the equalization pulse from a periodic signal containing the equalization pulse based on the output of the detection circuit.