JPS5940781A - Reference signal generating circuit - Google Patents

Abstract

PURPOSE:To attain accurate synchronism to substantial vertical and horizontal synchronizing signals even if a noise signal such as ghost signal takes place, by using an equivalent pulse just after the vertical synchronizing signal so as to phase-lock of the vertical or horizontal reference signal to that of the horizontal and vertical synchronizing signals. CONSTITUTION:When an equivalent pulse EQ is outputted from a horizontal synchronizing signal separating circuit 37, a counter circuit 38 enabling to count a clock signal S1 up to the prescribed final count value at first is used and a signal Sh including a pulse having the entirely same phase as that of the equivalent pulse EQ is obtained at an output terminal of the counter circuit 38. A pulse obtained from the equivalent EQ pulse after the signal Sh, especially the vertical synchronizing signal VS, i.e., the signal Si, and a signal Sj obtained from an ROM41 according to the counting of a counter circuit 22 are compared for the phase, the final count value of the counter circuit 22 is increased/decreased at the existence period of the equivalent pulse EQ to shift the reset timing of the counter circuit 22. Thus, the horizontal and vertical reference signals are synchronized with the signals HS, VS.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a reference signal for producing a reference signal that is a phase reference for a vertical synchronization signal or horizontal synchronization signal No. 13 in a video signal in a ghost signal removal system or a teletext receiving system. Regarding generation circuits.

[Technical background of the invention]

Part 1 of a system for removing ghost signals generated in television broadcast signals? +J is a system that removes ghost signals using a circuit inside a fluorescent television set. This system focuses on the fact that the vertical 16 synchronization signal part of the video signal becomes a step waveform due to Goose 4J,
The aim is to detect all the superimposed phases of the ghost signal using this stellar I wave (1e). The reference signal that serves as a phase reference for reading the superimposed phase of this ghost signal must be generated in a state that is accurately synchronized with the vertical synchronization signal 1 in the video signal even if there is a dust signal or a noise signal.

A conventional circuit for generating such a reference signal uses an automatic frequency control circuit (hereinafter referred to as A2) with a phase-locked loop (PLL) configuration to generate a clock signal synchronized with a horizontal synchronization signal.
0 circuit) and frequency-divides it to create a vertical reference signal. FIG. 1 is a circuit diagram showing the circuit configuration. A video signal applied to a terminal 11 is separated from a horizontal synchronizing signal by a horizontal synchronizing signal separating circuit 12, and is supplied to a phase detection circuit 13. A voltage controlled oscillation circuit (VCO) 14 oscillates at a horizontal hill frequency (Ll) n times. The oscillation output signal of this 'pressure controlled oscillation 101 circuit 14 is divided by n in the frequency dividing circuit 15, and the frequency is 19. It is supplied to the phase detection iHL lpl path 13 as the prime signal of fH. The phase detection circuit 13 compares the phases of both human input signals, and
Based on the ratio @ result, 'tt<pressure control oscillation circuit 140 oscillation output frequency is changed. ``ry, pressure control pressure control oscillation circuit 1 0. The frequency +j of this frequency 21 is divided by 525 in the frequency dividing circuit 17, vertical iM running frequency - dam f
It is converted to the i number of st. The frequency dividing operation of the frequency dividing circuit 17 is separated from the video signal by the vertical synchronizing signal separating circuit 18. Reset by vertical sync signal. Therefore, the frequency dividing circuit J7 outputs a tC.vertical reference signal in phase synchronization with the vertical 1υ (signal) in the video signal.

[Problems with background technology]

However, the above configuration has the following problems.

-111-it of the output from the frequency dividing circuit 17
7! - The signal t largely depends on the vertical synchronizing signal, and more specifically on the horizontal synchronizing signal. Therefore, there is no problem when a video signal that has not been carved with a ghost signal or its lil noise number 1d arrives, but the video G+
If "j" is affected by a phytosound signal or other influences, a phase shift or jitter will occur in the reference signal. This is because when a ghost signal or other noise signal occurs, the horizontal synchronization signal separation circuit 12 In addition to the original horizontal sync signal, the sync signal in the picture part and ghost signal is separated,
Otherwise, the width of the separated horizontal synchronization signal will change. Additionally, the oscillation output frequency of the voltage controlled oscillation circuit 140 differs from that due to the original horizontal synchronization signal.

As a result, the phase of the divided output signal of the frequency dividing circuit 160 also differs from that of the original horizontal synchronizing signal, causing a phase shift and jitter in the vertical reference signal output from the frequency dividing circuit 17. This means that, for example, in the ``Ghost'' system, it is impossible to accurately detect the superimposed position of the ``Ghost'', and in the teletext system. , it becomes impossible to accurately extract data from the data packet. [Object of the Invention] This invention was developed to deal with the above-mentioned situation, and is designed to prevent noise signals such as DAST No. 46 and other noise signals from occurring in the video signal. Even if the original vertical synchronization signal and horizontal synchronization signal in the video signal
It is an object of the present invention to provide a reference signal generation path that can generate a reference signal that is a positive phase ζ (synchronized with (' and the reference f of these signals) r phase for the 1 and +1 signals.

[Summary of the invention]

This invention utilizes an equivalent noculus inserted immediately after the vertical IF synchronization signal in the video signal to
Alternatively, a horizontal reference signal is phase-synchronized with a horizontal synchronization signal and a vertical synchronization signal. For that reason,
means for separating a synchronizing signal from a video signal; A second counter means capable of counting clocks 1M up to a final count value and a tenth counter means capable of dividing the clock signal into a signal having a frequency of 2fH are provided. Then, during the existence period of the equivalent pulse after the vertical synchronization signal, the phase of the output signal of the second counter means and the output signal of the first counting means is compared, and based on the comparison result, , MiJ By increasing or decreasing the final count value of the first counter means, the counting operation of the first counter means is phase-synchronized with the equivalent of the first counter means.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. 2p and 2 are circuit diagrams of one embodiment. In the figure, a clock signal (S
+) is applied. For example, PLL or AFCIIjl I? Therefore, it may be a signal that is generated in phase synchronization with the burst signal, or it may be a signal that can be simply output from an oscillation circuit that oscillates freely. This clock signal (Sl) is counted by a counter circuit 22, and its count output is supplied to a coincidence circuit 23 as one input.

The other input of this mosquito circuit 23 is the Zube selection circuit 24.
output is supplied. When the values of both inputs match, the matching circuit 23 outputs a reset signal t11 to the counter circuit 22. The selection circuit 24 selects AND1 if the output of the stable multivibrator z5.26, which will be described in detail later, is
Since the blade of the 01 road 27 is 0''' and the way of the inverter circuit 28 is ``°1#'', the preset fixed value (Jin)
is supplied to the coincidence circuit 23 in the form of a binary number, and conversely, the output of the monostable multivibrator 25.26 becomes 1.
", selects the output of the adder circuit 3o. When the output signal (Sf) of the AND circuit 27 is °'1", as described above, the next binary number is supplied to the coincidence circuit 23 as the other input. Therefore, when the count value of the counter circuit 22 becomes , the coincidence signal from the coincidence circuit 23 is outputted from the coincidence circuit 23.
A reset signal for the reset circuit 22 is supplied, and the counter circuit 22 is reset. According to this, a clock signal (sl) having a frequency mfH is divided by -1 and a signal having a frequency 2fu is obtained. AND circuit zlt7
) tB force signal (8f) di"1' node @i, f[, the output of the adder circuit 3o is selected from 8, and this adder output and the count value -%M, L 7't: et, counter The circuit 22 is reset.The output signal of the AND circuit 27 is
The signal (Sf) reaches the 'v level once in one vertical scanning period, and this period is approximately half of one horizontal scanning period, as will be described later. Therefore, the final count value &: 1 message of the counter circuit 22 can be set at any time, but it is set to a value different from 7 only once in one vertical scanning period. In relation to the output No. 1g (Sf) of the circuit 27, the operation of the adder circuit V (2so, etc.), the configuration and operation of the K2+:y+ circuit will be explained in detail with reference to the No. 16 waveform diagram in Fig. 3. To explain, the video signal No. 4M (Sa) is applied to the terminal 31. The video signal (Sa) is applied to the terminal 31Z+.
Of Sa ), it shows especially the area around the a-synchronized partner number (VS). The p vertical synchronization signal 4g (VS) is separated from the video signal (S&) applied to the vertical synchronization signal (terminal 3 of the L circuit 32) and supplied to the counter circuit 33 as a reset signal. As shown in Fig. 3, the separated vertical synchronization signal (W (VS)) has an error in the vertical synchronization signal minute 320 time constant, an error before separation (t or slightly f), and a delay in the r phase.
included/? Lus Mlf has been filled, resulting in 9 russ.

The output signal 1g (Sc) of the counter circuit 33 is vertical synchronization A, and the output signal (Sb) of the signal separation circuit 32 is '1'.
The output of the inverter circuit 34 becomes ITN during this period, and the clock (W (S,)) applied to the terminal 35 is supplied to the counter circuit 33 via the AND circuit 36. Ru.

Vertical synchronization 4i separation circuit 3 to counter 11-' circuit 33
When the output of 2 becomes 0"911, the clock signal (s2) starts counting. Then, when the count number reaches the preset final count value, the counter circuit 33
The output 1st signal (Sc) changes from 60' to 1'', and the clock overflow (S2) is no longer input, so the counter circuit 330 stops counting. 33 output iki number (Sc)
The width of the vertical synchronization 4i (VS) is X'T+
is a Malus extended by the period of the clock signal (S2). Note that the clock signal (S2) is obtained by appropriately frequency-dividing the clock signal (Sl), for example.

Said monostable multivibrator 25.26F'l.

At the rising timing of the output signal (Sc) of the counter circuit 33, a Norse-like signal (
Sd)l(Se)′f: Output. In addition, the signal (so
), (sa) + It is of course possible to use a counter circuit instead of a monostable multivibrator to generate. The above-mentioned fc selection circuit 240 control signal (Sf) is obtained by ANDing the output signals (Se) and (Sd) of the monostable multivibrators 25 and 26 in the AND circuit 27, but in this case, the control signal (s
As mentioned above, the spacing of 1" in r ) is one horizontal scanning period (
The output M (Sd) + (S
@) width is set. Then, the control t=(sf
) is "1#", the count value of the counter circuit 220 is switched from receiving to the output of the adder circuit 30.

37 is a horizontal synchronization signal separation circuit. This horizontal synchronization signal separation circuit 37 has a time constant etc. of 1. It is set to a value of -f, % n, so that the horizontal synchronization signal (H8) and equivalent signal (EQ) can be separated. In this case, especially the equivalent nohirus (
EQ) - Designed for reliable separation.

The output signal (Sg) of the horizontal synchronizing signal separation circuit syJ serves as a reset force for the counter circuit 38, and resets the counter circuit 38 at the "0" level. The counter circuit 38 counts the clock signal (Sl), and if the final count is H+#k16, it starts counting.
3 n5ec, the upper calendar period is 16 x 9
3 n5ec is 1.49 μsec. In this case, equivalent/4' pulse lj:,'18LIf: about 2.5
4μBee, so the output signal of the counter circuit 38 (
sh ) il.

1 ”) of the equivalent pulse, during 1 tlJ / arm pulse is 1
It becomes an ID number that only stands up. Of course, in the case of wide period periods such as vertical synchronization signals (TTS) and vertical synchronization signals (VS), there are multiple signals in each period.
However, in this invention, the output signal (sh) of the counter circuit 38 is equal to the equivalent pulse (EQ
) is used.

The output signal (sh) of the counter circuit 38 and the output signal +F (sd) of the monostable multivibrator 25 are passed through a NAND circuit 39 and converted into No. 18 (St) as shown in FIG. In other words, the output signal (s
h), a 1c pulse corresponding to the equivalent pulse (EQ) after the vertical synchronizing signal (VS) is extracted. This signal (St) is supplied as a reset signal to a free-lag analog circuit 4θ consisting of NAND circuits 401 and 402. The signals (sj) and (sk) are both signals of a frequency (2 h I) output from a lint-only memory (hereinafter referred to as ROM) 41. In this case, the signal (Sj) iJ is ◎(gb (
Sk) is set at a constant width of 1 from the position of ∆ (Sj). h with the pulse. No. 11 (Sj) and (Sk) are both generated based on the output of Callan 1 of the counter circuit 22, so they are always the same (r'L phase relationship. ROM 4) is, in short, a famous dart circuit. (Jl combination jIy
Sa71. 1d month (Sj) when the count value of the counter circuit 22 becomes tatami.

(Sk) is output. Signal (Sj) l'' becomes the 1 frizzo flop circuit 400 set signal. As a result, the output terminal of the frizzo flop circuit 40 falls at the timing of (No. 5 (St)) and falls at the timing of signal (Sj). A rising signal (St) is obtained. This signal (S
t) is connected to the up/down input of the up/down counter 42.

The up/down counter 42 performs an up-count operation during the period when the signal (St) is 1#, and performs a down-count operation during the period when the signal (St) is 0''. Sl
) is used, but this clock signal (St
) is wart) (sk) is]” period/Kokeand I
! Up/down counter circuit 42 through I circuit 43
supplied to Therefore, the signal (Sk), (F
When the phase relationship such as 3t) is as shown in FIG. 3, the up/down counter circuit 42 always performs an up-count operation. Atsu 7'/When the count value of the down counter circuit 42 is "1", the signal (sr) is n
``'C2f>'', the output signal of the adder circuit 30 becomes 2+n.As a result, the counter circuit 22 becomes 2+n.
After counting n, a reset is applied after fcm, and the final count value increases. Then the signal (Sf)
becomes "+1", and the usual counting operation is performed. At this time, the signal (Sa) also becomes NO#, so the up/down counter circuit 42 is reset, and its output becomes 0 when the signal (Sa) again becomes "1".

In this way, in the circuit shown in the figure where n<2, 1
3, the phase of No. 43 (Sj) = (8k) is shifted to the right in Fig. 3 compared to the video (No. When you reply, Shinq (SS) ~ (St)
The phase relationship is as shown in FIG.

Fig. 4 1J: The time axis (horizontal axis) is enlarged compared to Fig. 3. In this state, the period of 1 up count operation and the period of down count operation are the same, r\1'i station a, 7
The output of the zo/down force counter circuit 42 becomes 0'' and 18
The phases of the moon'' (sj) and (sk) do not move.

In Fig. 4, if A, (Sj), and (Sk) are located a little to the left, the up-count operation period will be wider than the down-count operation period, and as a result, the signal (
sj), (skN:I same as above and shifted to the right J
do. On the other hand, if it were shifted to the right, the down-count operation period would be wider and the output of the adder circuit 30 would be smaller than the output of the adder circuit 30. As a result, the counter circuit 22 is reset early and the 91 signals (Sj), (Sk)
shifts to the left. After such an operation, when the width of the up-count operation period and the down-count operation period become equal, a convergence state is reached. The signal (Sj) or (Sk) obtained in this way can be used as a horizontal reference signal. Further, by passing these No. 16 (sj) or (Sk) through a frequency dividing circuit 17 as shown in FIG. 1, a vertical reference signal can be obtained.

As described in detail above, this embodiment uses a video signal (Sm
Based on the equivalent cell (EQ) after the vertical rt-f synchronization signal (VS) included in ), the horizontal measurement F is configured to generate a vertical reference signal f-). Specifically, the horizontal synchronizing signal separation circuit 37 generates an equivalent signal (EQ
) (Actually, a signal with the same polarity as this equivalent pulse (EQ) and a width greater than this equivalent pulse (EQ)) is input, the clock signal (S
A counter rr;+ path 38 is provided which can count up to the final count value predetermined by MQ. As a result, the output terminal of the counter circuit 38 receives an equivalent pulse (EQ).
No. 15 (Sh)'t, which contains exactly the same phase as No. 15 (Sh)'t
-Can be obtained. Of this signal (sh), especially the pulse obtained from the special pulse (EQ) after the vertical synchronization signal (VS), that is, the signal (81) and the counter circuit 2
The final count value of the color/recircuit circuit 22 is compared with the signal (S'') obtained from the ROM 41 according to the count 1191 operation of 2, and the final count value is usually added to the signal based on the comparison result. is increased or decreased during the existence period of the equivalent pulse (EQ) after the vertical synchronization signal (VS), thereby shifting the reset timing of the counter circuit 22.

Therefore, by repeating this operation in the full number type [a scanning period, the count error b of the counter circuit 22 can be reduced to an equivalent value t
'? (EQ), in other words can be synchronized to the horizontal and vertical synchronization signals (H8), (VS), resulting in horizontal and vertical -j,% quasi-signals to these signals +j(H8), (VS ) can be synchronized.

With such a configuration, when horizontal or vertical reference signals are obtained, the reason why these signals 1d are difficult to receive from the influence of cost signals and other noise signals will be explained below. First, to control the counting operation of the counter circuit 22, there is a t44 configuration that uses the Tonoura-9 pulse (E) of the direct synchronization pulse (VS). Since there is originally no picture signal in the area where the equivalent 9 Lus (IQ) exists, the conventional horizontal synchronization signal (H8) is used for the separated output near the area where the equivalent 9 Lus (, EQ') exists.
Unlike when using all images, the image components are not included. In addition, due to the absence of a picture signal, even if fN (goose) occurs in Figure 5, the waveform in the region where the equivalent pulse (IQ) exists will be an elementary waveform, and the separation level (V
By making EQ shallow, it is possible to prevent the ghost component of the equivalent signal (EQ) from being separated. (EQ+) and (EQ2) are the positive and negative polarity ghost components of the equivalent signal (EQ), respectively.In addition, the video signal (Sa) contains noise (No. 4) due to weak electric fields, etc. horizontal synchronization signal separation circuit 3
At the output end of 7, a separated output of the noise signal is obtained.

However, since 1WIl+:j of this noise signal is generally narrow, the counter times v, ? ! Even if T38 is set to the set state due to noise components, the clock signal (S
t) is reset before counting to the count value of 5 (06).Therefore, the signal (sh) almost never contains an A pulse due to a noise signal. For example, in the previous implementation 1211, it is basically to obtain a reference signal that is phase synchronized with the horizontal or vertical 1 ■ synchronization ID () Is), (VS) with positive UM. However, due to the difference in width between the up count and the down count, rough corrections may cause the book to crash. In this case, if IT'S is reduced to a fraction and supplied to the adder circuit 30,
The force counting operation of the counter circuit 220 can be precisely controlled, and the above-mentioned knock σ) can be prevented from occurring. In addition,
In this case, the up/down counter "il h'W 4
By shifting the count of 2 by n bits,
The π output of this count value can be obtained. As for the song method, the output signal (Sf)'(r of the AND circuit 27 is forced to ``(]''), and the output signal (Sf)'(r) of the AND circuit 27 is set to It is also possible to set the final count value of the circuit 22 early and use it.In this case, the horizontal and vertical synchronizing signals (H8)
, (VS)1, and a fC standard signal cannot be obtained. However, compared to the case where a book occurs, a reference signal of higher quality can be obtained.

-±1, the signal (s
l) As a means for controlling the counting operation of 'I'i22 in the counter cycle using e, there are an end/down counter circuit 42, an adder circuit 30, a coincidence circuit 23, and a selection circuit 24.
Any configuration other than the configuration using etc. may be used.

〔Effect of the invention〕

As described above, according to the present invention, there is no ghost 1 in the video signal.
Even if noise 1i4 and other noises occur in the fC field Q-, the original vertical synchronization signal 14 and horizontal synchronization in the video (g signal) rotate exactly at the same time as the signal, and the reference phase of these signals and It is possible to provide a reference signal generation circuit that can generate a reference signal that is /,

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional standard No. 111 generation circuit;
, g2 Figure t is a circuit diagram showing an embodiment of the reference signal generation circuit according to the present invention, ':, +53 Figure is a signal waveform diagram for explaining the operation of the circuit shown in Figure 2, and Figure 4 is the same. A diagram showing a part of the signal waveform in Figure 3 enlarged to further explain the operation in detail, Figure 5 V, and Figure 2. It1 waveform diagram to explain one of the effects of the circuit shown in Figure 2. It is. 21, 29, J 1, ? 5...terminal,
22.33゜38... Counter circuit, 23... Match circuit, 24... Selection circuit, 25.26... Single! /So constant multi-pipe lake, 27.36...AND circuit,
28.34...Inverter circuit, 30...Adder
Circuit, 32... Vertical synchronization signal separation circuit, 37... Horizontal synchronization signal separation circuit, 39... Su/do times It'l11
．． 4o... Frizzo flop circuit, 41... ROM
, , 12...up/down/counter circuit.

Claims (1)

[Claims] Clock signal total frequency 27u (c: horizontal scanning frequency 1
．． 1) first counter means capable of dividing the frequency of the signal by t=7;
A synchronizing signal separating means for separating a synchronizing signal from a video signal; and a synchronizing signal separating means for separating a synchronizing signal from a video signal; a second counter means capable of counting the clock signal 1d up to a maximum count value of 1.% set for the purpose of the present invention; a first count value setting means for setting the final count value of the counter means of M1 so that a signal with a frequency of 2 fH is obtained from the means; The phase of the frequency-divided output signal of the counter means is compared with the count output signal of the second color/counter means, and the final frequency of the first counter means is adjusted based on the result of the phase comparison so that both signals are phase-synchronized. A reference ID number generation circuit comprising second count value setting means capable of increasing or decreasing the count value.